Dual 2-A High-Speed,
Low-Side Gate Drivers
FAN3226, FAN3227,
FAN3228, FAN3229
Description
The FAN3226−29 family of dual 2 A gate drivers is designed to
drive N−channel enhancement−mode MOSFETs in low−side
switching applications by providing high peak current pulses during
the short switching intervals. The driver is available with either TTL
or CMOS input thresholds. Internal circuitry provides an
under−voltage lockout function by holding the output low until the
supply voltage is within the operating range. In addition, the drivers
feature matched internal propagation delays between A and B
channels for applications requiring dual gate drives with critical
timing, such as synchronous rectifiers. This enables connecting two
drivers in parallel to effectively double the current capability driving
a single MOSFET.
The FAN322X drivers incorporate MillerDrivet architecture for
the final output stage. This bipolar−MOSFET combination provides
high current during the Miller plateau stage of the MOSFET turn−on/
turn−off process to minimize switching loss, while providing
rail−to−rail voltage swing and reverse current capability.
The FAN3226 offers two inverting drivers and the FAN3227 offers
two non−inverting drivers. Each device has dual independent enable
pins that default to ON if not connected. In the FAN3228 and
FAN3229, each channel has dual inputs of opposite polarity, which
allows configuration as non−inverting or inverting with an optional
enable function using the second input. If one or both inputs are left
unconnected, internal resistors bias the inputs such that the output is
pulled low to hold the power MOSFET off.
Features
•
•
•
•
•
•
•
•
•
•
•
Industry−Standard Pinouts
4.5−V to 18−V Operating Range
3−A Peak Sink/Source at VDD = 12 V
2.4 A−Sink/1.6−A Source at VOUT = 6 V
Choice of TTL or CMOS Input Thresholds
Four Versions of Dual Independent Drivers:
♦ Dual Inverting + Enable (FAN3226)
♦ Dual Non−Inverting + Enable (FAN3227)
♦ Dual Inputs in Two Pin−Out Configurations:
− Compatible with FAN3225x (FAN3228)
− Compatible with TPS2814D (FAN3229)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive Technology
12−ns/9−ns Typical Rise/Fall Times (1−nF Load)
Under 20−ns Typical Propagation Delay Matched within 1 ns to
the Other Channel
Double Current Capability by Paralleling Channels
© Semiconductor Components Industries, LLC, 2019
November, 2020 − Rev. 4
1
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8
1
SOIC8
CASE 751EB
MARKING DIAGRAM
8
$Y&Z&2&K
FAN
XXXXX
1
$Y
&Z
&2
&K
= ON Semiconductor Logo Graphic
= Assembly Plant Code
= 2−Digit Data Code (Year & Week)
= 2−Digit Lot Run Traceability Code
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
Features (Continued)
•
•
•
•
8−Lead SOIC Package
Rated from –40°C to +125°C Ambient
AEC−Q100 Qualified and PPAP Capable
These are Pb−Free Devices
Applications
•
•
•
•
•
•
•
Switch−Mode Power Supplies
High−Efficiency MOSFET Switching
Synchronous Rectifier Circuits
DC−to−DC Converters
Motor Control
Servers
Automotive−Qualified Systems
Publication Order Number:
FAN3229T−F085/D
FAN3226, FAN3227, FAN3228, FAN3229
PIN CONFIGURATIONS
ENA
1
INA
2
GND
3
INB
4
8
A
B
ENB
ENA
1
7
OUTA
INA
2
6
VDD
GND
3
5
OUTB
INB
4
FAN3226
8
A
B
INA− 1
ENB
7
OUTA
INB+
2
6
VDD
GND
3
5
OUTB
INB−
4
FAN3227
8
+
A
−
+
B
−
INA+
INA+
1
7
OUTA
INA− 2
6
VDD
INB+
3
5
OUTB
INB−
4
FAN3228
+
A
−
+
B
−
8
GND
7
OUTA
6
VDD
5
OUTB
FAN3229
Figure 1. Pin Configurations
PACKAGE OUTLINES
1
8
2
7
3
6
4
5
Figure 2. SOIC−8 (Top View)
THERMAL CHARACTERISTICS (Note 1)
Package
8−Pin Small Outline Integrated Circuit (SOIC)
QJL
(Note 2)
QJT
(Note 3)
QJA
(Note 4)
YJB
(Note 5)
YJT
(Note 6)
Unit
40
31
89
43
3.0
°C/W
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL (QJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad)
that are typically soldered to a PCB.
3. Theta_JT (QJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform
temperature by a top−side heatsink.
4. Theta_JA (QJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given
is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7,
as appropriate.
5. Psi_JB (YJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application
circuit board reference point for the thermal environment defined in Note 4. For the SOIC−8 package, the board reference is defined as the
PCB copper adjacent to pin 6.
6. Psi_JT (YJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of
the top of the package for the thermal environment defined in Note 4.
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FAN3226, FAN3227, FAN3228, FAN3229
PIN DEFINITIONS
Name
Description
ENA
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and CMOS INx
threshold.
ENB
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and CMOS INx
threshold.
GND
Ground. Common ground reference for input and output circuits.
INA
Input to Channel A.
INA+
Non−Inverting Input to Channel A. Connect to VDD to enable output.
INA−
Inverting Input to Channel A. Connect to GND to enable output.
INB
Input to Channel B.
INB+
Non−Inverting Input to Channel B. Connect to VDD to enable output.
INB−
Inverting Input to Channel B. Connect to GND to enable output.
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTB
Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is above UVLO
threshold.
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is above UVLO
threshold.
VDD
ENA
1
INA
2
GND
3
INB
4
Supply Voltage. Provides power to the IC.
A
B
8
ENB
ENA
1
7
OUTA
INA
2
6
VDD
GND
3
5
OUTB
INB
4
FAN3226
A
B
8
ENB
INA− 1
7
OUTA
INB+
2
6
VDD
GND
3
5
OUTB
INB−
4
+
A
−
+
B
−
FAN3227
8
INA+
INA+
7
OUTA
INA− 2
6
VDD
INB+
3
5
OUTB
INB−
4
FAN3228
1
+
A
−
+
B
−
8
GND
7
OUTA
6
VDD
5
OUTB
FAN3229
Figure 3. Pin Configurations (Repeated)
OUTPUT LOGIC
FAN3226 (x = A or B)
FAN3228 and FAN3229 (x = A or B)
ENx
INx
OUTx
INx+
INx−
OUTx
0
0
0
0 (Note 7)
0
0
0
1 (Note 7)
0
0 (Note 7)
1 (Note 7)
0
1 (Note 7)
0
1
1
0
1
1 (Note 7)
1 (Note 7)
0
1
1 (Note 7)
0
FAN3227 (x = A or B)
ENx
INx
OUTx
0
0 (Note 7)
0
0
1
0
1 (Note 7)
0 (Note 7)
0
1 (Note 7)
1
1
7. Default input signal if no external connection is made.
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FAN3226, FAN3227, FAN3228, FAN3229
BLOCK DIAGRAMS
VDD
VDD
100kΩ
100kΩ
ENA 1
8
ENB
VDD
100kΩ
INA
2
7
OUTA
100kΩ
GND 3
UVLO
6
VDD
VDD_OK
VDD
100kΩ
INB
5
4
OUTB
100kΩ
Figure 4. FAN3226 Block Diagram
VDD
VDD
100kΩ
100kΩ
ENA 1
8
INA 2
7
100kΩ
OUTA
100kΩ
UVLO
GND 3
ENB
6
VDD
VDD_OK
INB 4
5
OUTB
100kΩ
100kΩ
Figure 5. FAN3227 Block Diagram
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4
FAN3226, FAN3227, FAN3228, FAN3229
VDD
INA+ 8
100kΩ
INA− 1
7
100kΩ
OUTA
100kΩ
VDD_OK
GND 3
UVLO
VDD
6
VDD
5
OUTB
INB+ 2
100kΩ
INB− 4
100kΩ
100kΩ
Figure 6. FAN3228 Block Diagram
VDD
INA+ 1
8
GND
7
OUTA
6
VDD
5
OUTB
100kΩ
INA− 2
100kΩ
100kΩ
VDD_OK
UVLO
VDD
INB+ 3
100kΩ
INB− 4
100kΩ
100kΩ
Figure 7. FAN3229 Block Diagram
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5
FAN3226, FAN3227, FAN3228, FAN3229
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
−0.3
20.0
V
ENA and ENB to GND
GND − 0.3
VDD + 0.3
V
INA, INA+, INA−, INB, INB+ and INB− to GND
GND − 0.3
VDD + 0.3
V
OUTA and OUTB to GND
GND − 0.3
VDD + 0.3
V
−
+260
°C
VDD
VDD to GND
VEN
VIN
VOUT
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
−55
+150
°C
TSTG
Storage Temperature
−65
+150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
4.5
18.0
V
Enable Voltage ENA and ENB
0
VDD
V
VIN
Input Voltage INA, INA+, INA−, INB, INB+ and INB−
0
VDD
V
TA
Operating Ambient Temperature
−40
+125
°C
VDD
Supply Voltage Range
VEN
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (VDD = 12 V and TJ = −40°C to +125°C unless otherwise noted. Currents are defined as
positive into the device and negative out of the device.)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
4.5
−
18.0
V
mA
SUPPLY
VDD
Operating Range
IDD
Supply Current, Inputs/EN
Not Connected
TTL
−
0.75
1.20
CMOS (Note 8)
−
0.65
1.05
VON
Turn−On Voltage
INA = ENA = VDD,
INB = ENB = 0 V
3.3
3.9
4.5
V
VOFF
Turn−Off Voltage
INA = ENA = VDD,
INB = ENB = 0 V
3.1
3.7
4.3
V
INPUTS (TTL, FAN322XT) (Note 9)
VINL_T
INx Logic Low Threshold
0.8
1.2
−
V
VINH_T
INx Logic High Threshold
−
1.6
2.0
V
VHYS_T
TTL Logic Hysteresis Voltage
0.2
0.4
0.8
V
IINx_T
Non−Inverting Input Current
IN = 0 V
−1.5
−
1.5
mA
IINx_T
Non−Inverting Input Current
IN = VDD
90
120
175
mA
IINx_T
Inverting Input Current
IN = 0 V
−175
−120
−90
mA
IINx_T
Inverting Input Current
IN = VDD
−1.5
−
1.5
mA
INPUTS (FAN322xC) (Note 9)
VINL_C
INx Logic Low Threshold
30
38
−
%VDD
VINH_C
INx Logic High Threshold
−
55
70
%VDD
VHYS_C
CMOS Logic Hysteresis Voltage
−
17
−
%VDD
IINx_T
Non−Inverting Input Current
IN = 0 V
−1.5
−
1.5
mA
IINx_T
Non−Inverting Input Current
IN = VDD
90
120
175
mA
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FAN3226, FAN3227, FAN3228, FAN3229
ELECTRICAL CHARACTERISTICS (VDD = 12 V and TJ = −40°C to +125°C unless otherwise noted. Currents are defined as
positive into the device and negative out of the device.) (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
IINx_T
Inverting Input Current
IN = 0 V
−175
−120
−90
mA
IINx_T
Inverting Input Current
IN = VDD
−1.5
−
1.5
mA
ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T)
VENL
Enable Logic Low Threshold
EN from 5 V to 0 V
0.8
1.2
−
V
VENH
Enable Logic High Threshold
EN from 0 V to 5 V
−
1.6
2.0
V
VHYS_T
TTL Logic Hysteresis Voltage
−
0.4
−
V
RPU
Enable Pull−up Resistance
−
100
−
kW
tD3
EN to Output Propagation Delay (Note 11)
0 V to 5 V EN, 1 V/ns Slew Rate
8
19
35
ns
5 V to 0 V EN, 1 V/ns Slew Rate
8
18
35
ns
OUT Current, Mid−Voltage, Sinking (Note 10)
OUT at VDD / 2, CLOAD = 0.1 mF,
f = 1 kHz
−
2.4
−
A
ISOURCE
OUT Current, Mid−Voltage, Sourcing (Note 10)
OUT at VDD / 2, CLOAD = 0.1 mF,
f = 1 kHz
−
−1.6
−
A
IPK_SINK
OUT Current, Peak, Sinking (Note 10)
CLOAD = 0.1 mF, f = 1 kHz
−
3
−
A
OUT Current, Peak, Sourcing (Note 10)
CLOAD = 0.1 mF, f = 1 kHz
−
−3
−
A
tRISE
Output Rise Time (Note 11)
CLOAD = 1000 pF
−
12
22
ns
tFALL
Output Fall Time (Note 11)
CLOAD = 1000 pF
−
9
17
ns
IRVS
Output Reverse Current Withstand (Note 10)
−
500
−
mA
CMOS Input
7
15
33
ns
CMOS Input
6
15
42
ns
TTL Input
9
19
34
ns
TTL Input
9
18
32
ns
Propagation Matching Between Channels
(Note 12)
INA = INB, OUTA and OUTB at
50% Point
−
2
4
ns
VOH
High Level Output Voltage
VOH = VDD – VOUT, IOUT= –1 mA
−
15
35
mV
VOL
Low Level Output Voltage
IOUT= 1 mA
−
10
25
mV
tD4
OUTPUTS
ISINK
IPK_SOURCE
FAN322xT, FAN322xC
tD1
Output Propagation Delay, CMOS Inputs (Note 12)
tD2
tD1
Output Propagation Delay, TTL Inputs (Note 12)
tD2
tDEL.MATCH
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Lower supply current due to inactive TTL circuitry.
9. EN inputs have modified TTL thresholds; refer to the ENABLE section.
10. Not tested in production.
11. See Timing Diagrams of Figure 10 and Figure 11.
12. See Timing Diagrams of Figure 8 and Figure 9.
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FAN3226, FAN3227, FAN3228, FAN3229
TIMING DIAGRAMS
90%
90%
Output
Output
10%
Input
10%
VINH
Input
VINL
VINH
VINL
tD2
tD1
tRISE
tFALL
tFALL
Figure 8. Non−Inverting (EN HIGH or Floating)
tRISE
Figure 9. Inverting (EN HIGH or Floating)
HIGH
HIGH
Input
Input
LOW
LOW
90%
90%
Output
Output
10%
Enable
tD2
tD1
10%
VENH
Enable
VENL
VENH
VENL
tD4
tD3
tRISE
tD4
tD3
tFALL
tRISE
Figure 10. Non−Inverting (IN HIGH)
tFALL
Figure 11. Inverting (IN LOW)
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FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL PERFORMANCE CHARACTERISTICS
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
1.6
1.6
FAN3226C, 27C
1.2
1.0
1.0
0.8
0.6
0.4
0.8
0.6
0.4
Inputs and Enables
Floating, Outputs
0.2
TTL Input
1.4
1.2
IDD (mA)
IDD (mA)
1.4
Inputs and Enables
Floating, Outputs Low
0.2
0.0
0.0
4
6
8
10
12
14
16
4
18
6
8
10
12
14
16
18
Supply Voltage (V)
Supply Voltage (V)
Figure 12. IDD (Static) vs. Supply Voltage (Note 13)
Figure 13. IDD (Static) vs. Supply Voltage (Note 13)
1.6
FAN3228C, 29C
1.4
IDD (mA)
1.2
1.0
All Inputs Floating,
Outputs Low
0.8
0.6
0.4
0.2
0.0
4
6
8
10
12
14
16
V DD − Supply Voltage (V)
18
Figure 14. IDD (Static) vs. Supply Voltage (Note 13)
Figure 15. IDD (No−Load) vs. Frequency
Figure 16. IDD (No−Load) vs. Frequency
Figure 17. IDD (1 nF Load) vs. Frequency
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FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
1.6
FAN3226C, 27C
1.4
IDD (mA)
1.2
1.0
0.8
0.6
Inputs and Enables
Floating, Outputs
0.4
0.2
0.0
−50
Figure 18. IDD (1 nF Load) vs. Frequency
1.4
1.2
1.0
1.0
IDD (mA)
IDD (mA)
25
50
75
Temperature (5C)
100
125
1.6
TTL Input
1.2
0.8
0.6
Inputs andEnables
Floating, Outputs
0.4
0.2
0.0
−50
0
Figure 19. IDD (Static) vs. Temperature (Note 13)
1.6
1.4
−25
−25
0
25
50
75
100
FAN3228C, 29C
0.8
0.6
0.4
All Inputs Floating,
Outputs Low
0.2
0.0
−50
125
Temperature (5C)
−25
0
25
50
75
Temperature (5C)
100
125
Figure 20. IDD (Static) vs. Temperature (Note 13)
Figure 21. IDD (Static) vs. Temperature (Note 13)
Figure 22. Input Thresholds vs. Supply Voltage
Figure 23. Input Thresholds vs. Supply Voltage
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FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
Figure 24. Input Threshold % vs. Supply Voltage
Figure 25. Input Thresholds vs. Temperature
Figure 26. Input Thresholds vs. Temperature
Figure 27. UVLO Thresholds vs. Temperature
Figure 28. UVLO Thresholds vs. Temperature
Figure 29. Propagation Delay vs. Supply Voltage
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FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
Figure 30. Propagation Delay vs. Supply Voltage
Figure 31. Propagation Delay vs. Supply Voltage
Figure 32. Propagation Delay vs. Supply Voltage
Figure 33. Propagation Delays vs. Temperature
Figure 34. Propagation Delays vs. Temperature
Figure 35. Propagation Delays vs. Temperature
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FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
Figure 36. Propagation Delays vs. Temperature
Figure 37. Fall Time vs. Supply Voltage
Figure 38. Rise Time vs. Supply Voltage
Figure 39. Rise and Fall Times vs. Temperature
Figure 40. Rise / Fall Waveforms with 1 nF Load
Figure 41. Rise / Fall Waveforms with 10 nF Load
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FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted)
Figure 42. Quasi−Static Source Current with VDD = 12 V
Figure 43. Quasi−Static Sink Current with VDD = 12 V
Figure 44. Quasi−Static Source Current with VDD = 8 V
Figure 45. Quasi−Static Sink Current with VDD = 8 V
13. For any inverting inputs pulled LOW, non−inverting inputs pulled HIGH, or outputs driven HIGH; static IDD increases by the current flowing
through the corresponding pull−up/down resistor, shown in Figure 4.
TEST CIRCUIT
V DD
120 mF
Al. El.
4.7 mF
ceramic
Current Probe
LACROY AP015
IN
1 kHz
I OUT
1 mF
ceramic
V OUT
C LOAD
0.1 mF
Figure 46. Quasi−Static IOUT / VOUT Test Circuit
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FAN3226, FAN3227, FAN3228, FAN3229
APPLICATIONS INFORMATION
Input Thresholds
a combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the bulk of
the current as OUT swings between 1/3 to 2/3 VDD and the
MOS devices pull the output to the high or low rail.
The purpose of the MillerDrive architecture is to speed up
switching by providing high current during the Miller
plateau region when the gate−drain capacitance of the
MOSFET is being charged or discharged as part of the
turn−on/turn−off process.
For applications that have zero voltage switching during
the MOSFET turn−on or turn−off interval, the driver
supplies high peak current for fast switching even though the
Miller plateau is not present. This situation often occurs in
synchronous rectifier applications because the body diode is
generally conducting before the MOSFET is switched on.
The output pin slew rate is determined by VDD voltage and
the load on the output. It is not user adjustable, but a series
resistor can be added if a slower rise or fall time at the
MOSFET gate is needed.
Each member of the FAN322x driver family consists of
two identical channels that may be used independently at
rated current or connected in parallel to double the
individual current capacity. In the FAN3226 and FAN3227,
channels A and B can be enabled or disabled independently
using ENA or ENB, respectively. The EN pin has TTL
thresholds for parts with either CMOS or TTL input
thresholds. If ENA and ENB are not connected, an internal
pull−up resistor enables the driver channels by default. If the
channel A and channel B inputs and outputs are connected
in parallel to increase the driver current capacity, ENA and
ENB should be connected and driven together.
The FAN322x family offers versions in either TTL or
CMOS input thresholds. In the FAN322xT, the input
thresholds meet industry−standard TTL−logic thresholds
independent of the VDD voltage, and there is a hysteresis
voltage of approximately 0.4 V. These levels permit the
inputs to be driven from a range of input logic signal levels
for which a voltage over 2 V is considered logic high. The
driving signal for the TTL inputs should have fast rising and
falling edges with a slew rate of 6 V/ms or faster, so a rise
time from 0 to 3.3 V should be 550 ns or less. With reduced
slew rate, circuit noise could cause the driver input voltage
to exceed the hysteresis voltage and retrigger the driver
input, causing erratic operation.
In the FAN322xC, the logic input thresholds are
dependent on the VDD level and, with VDD of 12 V, the logic
rising edge threshold is approximately 55% of VDD and the
input falling edge threshold is approximately 38% of VDD.
The CMOS input configuration offers a hysteresis voltage of
approximately 17% of VDD. The CMOS inputs can be used
with relatively slow edges (approaching DC) if good
decoupling and bypass techniques are incorporated in the
system design to prevent noise from violating the input
voltage hysteresis window. This allows setting precise
timing intervals by fitting an R−C circuit between the
controlling signal and the IN pin of the driver. The slow
rising edge at the IN pin of the driver introduces a delay
between the controlling signal and the OUT pin of the driver.
V DD
Input
stage
V OUT
Figure 47. Miller Drive Output Architecture
Under−Voltage Lockout (UVLO)
Static Supply Current
The FAN322x startup logic is optimized to drive
ground−referenced N−channel MOSFETs with an
under−voltage lockout (UVLO) function to ensure that the
IC starts up in an orderly fashion. When VDD is rising, yet
below the 3.9 V operational level, this circuit holds the
output low, regardless of the status of the input pins. After
the part is active, the supply voltage must drop 0.2 V before
the part shuts down. This hysteresis helps prevent chatter
when low VDD supply voltages have noise from the power
switching. This configuration is not suitable for driving
high−side P−channel MOSFETs because the low output
voltage of the driver would turn the P−channel MOSFET on
with VDD below 3.9 V.
In the IDD (static) typical performance characteristics (see
Figure 12 − Figure 14 and Figure 19 − Figure 21), the curve
is produced with all inputs / enables floating (OUT is low)
and indicates the lowest static IDD current for the tested
configuration. For other states, additional current flows
through the 100 kW resistors on the inputs and outputs
shown in the block diagram of each part (see Figure 4 −
Figure 7). In these cases, the actual static IDD current is the
value obtained from the curves plus this additional current.
MillerDrive Gate−Drive Technology
FAN322x gate drivers incorporate the MillerDrive
architecture shown in Figure 47. For the output stage,
www.onsemi.com
15
FAN3226, FAN3227, FAN3228, FAN3229
VDD Bypass Capacitor Guidelines
To enable this IC to turn a device on quickly, a local
high−frequency bypass capacitor CBYP with low ESR and
ESL should be connected between the VDD and GND pins
with minimal trace length. This capacitor is in addition to
bulk electrolytic capacitance of 10 mF to 47 mF commonly
found on driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the ripple voltage on the VDD supply to ≤5%. This is
often achieved with a value ≥20 times the equivalent load
capacitance CEQV, defined here as QGATE/VDD. Ceramic
capacitors of 0.1 mF to 1 mF or larger are common choices,
as are dielectrics, such as X5R and X7R with good
temperature characteristics and high pulse current
capability.
If circuit noise affects normal operation, the value of CBYP
may be increased to 50−100 times the CEQV, or CBYP may
be split into two capacitors. One should be a larger value,
based on equivalent load capacitance, and the other a smaller
value, such as 1−10 nF mounted closest to the VDD and
GND pins to carry the higher frequency components of the
current pulses. The bypass capacitor must provide the pulsed
current from both of the driver channels and, if the drivers
are switching simultaneously, the combined peak current
sourced from the CBYP would be twice as large as when
a single channel is switching.
•
•
effects can be obvious if the circuit is tested in breadboard
or non−optimal circuit layouts with long input, enable, or
output leads. For best results, make connections to all pins
as short and direct as possible.
The FAN322x is compatible with many other
industry−standard drivers. In single input parts with
enable pins, there is an internal 100 kW resistor tied to
VDD to enable the driver by default; this should be
considered in the PCB layout.
The turn−on and turn−off current paths should be
minimized, as discussed in the following section.
Figure 48 shows the pulsed gate drive current path when
the gate driver is supplying gate charge to turn the MOSFET
on. The current is supplied from the local bypass capacitor,
CBYP, and flows through the driver to the MOSFET gate and
to ground. To reach the high peak currents possible, the
resistance and inductance in the path should be minimized.
The localized CBYP acts to contain the high peak current
pulses within this driver−MOSFET circuit, preventing them
from disturbing the sensitive analog circuitry in the PWM
controller.
V DD
V DS
C BYP
Layout and Connection Guidelines
The FAN3226−26 family of gate drivers incorporates
fast−reacting input circuits, short propagation delays, and
powerful output stages capable of delivering current peaks
over 2 A to facilitate voltage transition times from under
10 ns to over 150 ns. The following layout and connection
guidelines are strongly recommended:
• Keep high−current output and power ground paths
separate logic and enable input signals and signal ground
paths. This is especially critical when dealing with
TTL−level logic thresholds at driver inputs and enable
pins.
• Keep the driver as close to the load as possible to
minimize the length of high−current traces. This reduces
the series inductance to improve high−speed switching,
while reducing the loop area that can radiate EMI to the
driver inputs and surrounding circuitry.
• If the inputs to a channel are not externally connected, the
internal 100 kW resistors indicated on block diagrams
command a low output. In noisy environments, it may be
necessary to tie inputs of an unused channel to VDD or
GND using short traces to prevent noise from causing
spurious output switching.
• Many high−speed power circuits can be susceptible to
noise injected from their own output or other external
sources, possibly causing output re−triggering. These
FAN322x
PWM
Figure 48. Current Path for MOSFET Turn−On
Figure 49 shows the current path when the gate driver
turns the MOSFET off. Ideally, the driver shunts the current
directly to the source of the MOSFET in a small circuit loop.
For fast turn−off times, the resistance and inductance in this
path should be minimized.
V DD
V DS
C BYP
FAN322x
PWM
Figure 49. Current Path for MOSFET Turn−Off
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16
FAN3226, FAN3227, FAN3228, FAN3229
Truth Table of Logic Operation
Operational Waveforms
The FAN3228/FAN3229 truth table indicates the
operational states using the dual−input configuration. In
a non−inverting driver configuration, the IN− pin should be
a logic low signal. If the IN− pin is connected to logic high,
a disable function is realized, and the driver output remains
low regardless of the state of the IN+ pin.
At power−up, the driver output remains low until the VDD
voltage reaches the turn−on threshold. The magnitude of the
OUT pulses rises with VDD until steady−state VDD is
reached. The non−inverting operation illustrated in
Figure 52 shows that the output remains low until the UVLO
threshold is reached, the output is in−phase with the input.
Table 1. TRUTH TABLE OF LOGIC OPERATION
IN+
IN−
OUT
0
0
0
0
1
0
1
0
1
1
1
0
V DD
IN−
In the non−inverting driver configuration in Figure 50, the
IN− pin is tied to ground and the input signal (PWM) is
applied to IN+ pin. The IN− pin can be connected to logic
high to disable the driver and the output remains low,
regardless of the state of the IN+ pin.
IN+
OUT
VDD
PWM
IN+
IN−
FAN3228/9
Figure 52. Non−Inverting Startup Waveforms
OUT
For the inverting configuration of Figure 51, startup
waveforms are shown in Figure 53. With IN+ tied to VDD
and the input signal applied to IN–, the OUT pulses are
inverted with respect to the input. At power−up, the inverted
output remains low until the VDD voltage reaches the
turn−on threshold, then it follows the input with inverted
phase.
GND
Figure 50. Dual−Input Driver Enabled,
Non−Inverting Configuration
V DD
In the inverting driver application in Figure 51, the IN+
pin is tied high. Pulling the IN+ pin to GND forces the output
low, regardless of the state of the IN− pin.
VDD
IN−
FAN3228/9
Turn−on threshold
IN−
IN+
PWM
Turn−on threshold
IN+
(VDD)
OUT
GND
OUT
Figure 51. Dual−Input Driver Enabled,
Inverting Configuration
Figure 53. Inverting Startup Waveforms
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17
FAN3226, FAN3227, FAN3228, FAN3229
Thermal Guidelines
In the forward converter with synchronous rectifier
shown in the typical application diagrams, the FDMS8660S
is a reasonable MOSFET selection. The gate charge for each
SR MOSFET would be 60 nC with VGS = VDD = 7 V. At
a switching frequency of 500 kHz, the total power
dissipation is:
Gate drivers used to switch MOSFETs and IGBTs at high
frequencies can dissipate significant amounts of power. It is
important to determine the driver power dissipation and the
resulting junction temperature in the application to ensure
that the part is operating within acceptable temperature
limits.
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
P TOTAL + P GATE ) P DYNAMIC
(eq. 1)
(eq. 2)
n is the number of driver channels in use (1 or 2).
Dynamic Pre−drive / Shoot−through Current: A power
loss resulting from internal current consumption under
dynamic operating conditions, including pin pull−up /
pull−down resistors, can be obtained using the “IDD
(No−Load) vs. Frequency” graphs in Typical
Performance Characteristics to determine the current
IDYNAMIC drawn from VDD under actual operating
conditions:
P DYMANIC + I DYNAMIC @ V DD @ n
P DYNAMIC + 3 mA @ 7 V @ 2 + 0.042 W
(eq. 6)
P TOTAL + 0.46 W
(eq. 7)
T B + T J * P TOTAL @ Y JB
(eq. 8)
T B + 120°C * 0.46 W @ 43°CńW + 100°C
(eq. 9)
Consider tradeoffs between reducing overall circuit size
with junction temperature reduction for increased
reliability.
(eq. 3)
Once the power dissipated in the driver is determined, the
driver junction rise with respect to circuit board can be
evaluated using the following thermal equation, assuming
yJB was determined for a similar thermal design (heat
sinking and air flow):
T J + P TOTAL @ Y JB ) T B
(eq. 5)
The SOIC−8 has a junction−to−board thermal
characterization parameter of yJB = 43°C/W. In a system
application, the localized temperature around the device is
a function of the layout and construction of the PCB along
with airflow across the surfaces. To ensure reliable
operation, the maximum junction temperature of the device
must be prevented from exceeding the maximum rating of
150°C; with 80% derating, TJ would be limited to 120°C.
Rearranging Equation 4 determines the board temperature
required to maintain the junction temperature below 120°C:
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit time)
to switch the load MOSFET on and off at the switching
frequency. The power dissipation that results from driving
a MOSFET at a specified gate−source voltage, VGS, with
gate charge, QG, at switching frequency, fSW, is
determined by:
P GATE + Q G @ V GS @ f SW @ n
P GATE + 60 nC @ 7 V @ 500 kHz @ 2 + 0.42 W
(eq. 4)
where:
TJ = driver junction temperature;
yJB = (psi) thermal characterization parameter relating
temperature rise to total power dissipation; and
TB = board temperature in location as defined in the
Thermal Characteristics table.
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18
FAN3226, FAN3227, FAN3228, FAN3229
TYPICAL APPLICATION DIAGRAMS
VIN
VIN
VOUT
FAN3227
PWM
Timing/
Isolation
1
8
2
7
1
8
PWMA
2
7
GND
3
6
3
6
PWMB
4
5
4
5
Vbias
OUTA
VDD
OUTB
FAN3227
Figure 54. Forward Converter with Synchronous
Rectification
Figure 55. Primary−Side Dual Driver in
a Push−Pull Converter
VIN
FAN3227
PWM−A
ENB 8
1 ENA
2
A
3 GND
PWM−B
4
7
VDD 6
B
5
Vbias
FAN3227
PWM−C
Phase Shift
Controller
PWM−D
ENB 8
1 ENA
A
2
3 GND
4
7
VDD 6
B
Vbias
5
Figure 56. Phase−Shifted Full−Bridge with Two Gate Drive Transformers (Simplified)
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19
FAN3226, FAN3227, FAN3228, FAN3229
ORDERING INFORMATION
Input Threshold
Package
Shipping†
CMOS
SOIC−8
2,500 / Tape & Reel
TTL
SOIC−8
2,500 / Tape & Reel
Dual Non−Inverting Channels +
Dual Enable
CMOS
SOIC−8
2,500 / Tape & Reel
TTL
SOIC−8
2,500 / Tape & Reel
Dual Channels of Two−Input /
One−Output Drivers, Pin Configuration 1
CMOS
SOIC−8
2,500 / Tape & Reel
TTL
SOIC−8
2,500 / Tape & Reel
Dual Channels of Two−Input /
One−Output Drivers, Pin Configuration 2
CMOS
SOIC−8
2,500 / Tape & Reel
TTL
SOIC−8
2,500 / Tape & Reel
Part Number
FAN3226CMX−F085
Logic
Dual Inverting Channels + Dual Enable
FAN3226TMX−F085
FAN3227CMX−F085
FAN3227TMX−F085
FAN3228CMX−F085
FAN3228TMX−F085
FAN3229CMX−F085
FAN3229TMX−F085
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 2. RELATED PRODUCTS
Type
Part Number
Gate Drive
(Note 14)
(Sink/Src)
Dual 2 A
FAN3216T
+2.4 A / −1.6 A
Dual 2 A
FAN3217T
+2.4 A / −1.6 A
TTL
Dual Non−Inverting Channels
SOIC8
Dual 2 A
FAN3226C
+2.4 A / −1.6 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8
Dual 2 A
FAN3226T
+2.4 A / −1.6 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8
Dual 2 A
FAN3227C
+2.4 A / −1.6 A
CMOS
Dual Non−Inverting Channels + Dual Enable
SOIC8
Dual 2 A
FAN3227T
+2.4 A / −1.6 A
TTL
Dual Non−Inverting Channels + Dual Enable
SOIC8
Dual 2 A
FAN3228C
+2.4 A / −1.6 A
CMOS
Dual Channels of Two−Input/One−Output,
Pin Config.1
SOIC8
Dual 2 A
FAN3228T
+2.4 A / −1.6 A
TTL
Dual Channels of Two−Input/One−Output,
Pin Config.1
SOIC8
Dual 2 A
FAN3229C
+2.4 A / −1.6 A
CMOS
Dual Channels of Two−Input/One−Output,
Pin Config.2
SOIC8
Dual 2 A
FAN3229T
+2.4 A / −1.6 A
TTL
Dual Channels of Two−Input/One−Output,
Pin Config.2
SOIC8
Dual 2 A
FAN3268T
+2.4 A / −1.6 A
TTL
20 V Non−Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A
FAN3213T
+2.5 A / −1.8 A
TTL
Dual Inverting Channels
SOIC8
Dual 4 A
FAN3214T
+2.5 A / −1.8 A
TTL
Dual Non−Inverting Channels
SOIC8
Dual 4 A
FAN3223C
+4.3 A / −2.8 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8
Dual 4 A
FAN3223T
+4.3 A / −2.8 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8
Dual 4 A
FAN3224C
+4.3 A / −2.8 A
CMOS
Dual Non−Inverting Channels + Dual Enable
SOIC8
Dual 4 A
FAN3224T
+4.3 A / −2.8 A
TTL
Dual Non−Inverting Channels + Dual Enable
SOIC8, SOIC8−EP
Dual 4 A
FAN3225C
+4.3 A / −2.8 A
CMOS
Dual Channels of Two−Input/One−Output
SOIC8
Input
Threshold
TTL
Dual Inverting Channels
SOIC8
Logic
Package
Dual 4 A
FAN3225T
+4.3 A / −2.8 A
TTL
Dual Channels of Two−Input/One−Output
SOIC8
Single 9 A
FAN3121C
+9.7 A / −7.1 A
CMOS
Single Inverting Channel + Enable
SOIC8
Single 9 A
FAN3121T
+9.7 A / −7.1 A
TTL
Single Inverting Channel + Enable
SOIC8
Single 9 A
FAN3122C
+9.7 A / −7.1 A
CMOS
Single Non−Inverting Channel + Enable
SOIC8
Single 9 A
FAN3122T
+9.7 A / −7.1 A
TTL
Single Non−Inverting Channel + Enable
SOIC8, SOIC8−EP
14. Typical currents with OUTx at 6 V and VDD = 12 V.
15. Thresholds proportional to an externally supplied reference voltage.
MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
DATE 24 AUG 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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