Features
Description
Industry-Standard Pinouts
The FA N3226-29 family of dual 2 A gate dr ivers is
designed to drive N-channel enhancement- mode
MOSFETs in low -side sw itching applications by
providing high peak current pulses dur ing the short
sw itching intervals. The driver is available w ith either
TTL or CMOS input thresholds. Internal circuitry
provides an under-voltage lockout function by holding
the output low until the supply voltage is w ithin the
operating range. In addition, the drivers feature matched
internal propagation delays betw een A and B channels
for applications requiring dual gate drives w ith critical
timing, such as synchronous rectifiers. This enables
connecting tw o drivers in parallel to effectively double
the current capability driving a single MOSFET.
4.5-V to 18-V Operating Range
3-A Peak Sink/Source at V DD = 12 V
2.4 A-Sink / 1.6-A Source at V OUT = 6 V
Choice of TTL or CMOS Input Thresholds
Four Versions of Dual Independent Drivers:
-
Dual Inverting + Enable (FAN3226)
Dual Non-Inverting + Enable (FAN3227)
Dual Inputs in Tw o Pin-Out Configurations:
o
o
Compatible w ith FAN3225x (FAN3228)
Compatible w ith TPS2814D (FAN3229)
Internal Resistors Turn Driver Off If No Inputs
MillerDrive™ Technology
12-ns / 9-ns Typical Rise/Fall Times (1-nF Load)
Under 20-ns Typical Propagation Delay Matched
w ithin 1 ns to the Other Channel
Double Current Capability by Paralleling Channels
8-Lead 3x3 mm MLP or 8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Version)
Applications
Sw itch-Mode Pow er Supplies
The FA N322X drivers incorporate Miller Drive™
architecture for the final output stage. This bipolarMOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize sw itching loss, w hile providing railto-rail voltage sw ing and reverse current capability.
The FAN3226 offers two inverting drivers and the
FA N3227 offers tw o non-inverting drivers. Each device
has dual independent enable pins that default to ON if
not connected. In the FAN3228 and FAN3229, each
channel has dual inputs of opposite polarity, w hich
allows configuration as non- inverting or inverting w ith an
optional enable function using the second input. If one
or both inputs are left unconnected, internal resistors
bias the inputs such that the output is pulled low to hold
the pow er MOSFET off.
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circuits
Related Resources
DC-to-DC Converters
http://w w w.onsemi.com/pub/Collateral/A N-6069.pdf.pdf
Motor Control
Servers
Automotive-Qualified Systems (F085 version)
ENA
1
INA
2
GND
3
INB
4
A
B
8
ENB
7
OUTA
6
VDD
5
OUTB
ENA
1
INA
2
GND
3
INB
4
FAN3226
A
B
FAN3227
8
ENB
INA- 1
7
OUTA
INB+
6
VDD
GND
3
5
OUTB
INB-
4
2
+
A
+
B
-
FAN3228
8
INA+
INA+
1
7
OUTA
INA-
2
6
VDD
INB+
3
5
OUTB
INB-
4
+
A
+
B
-
8
GND
7
OUTA
6
VDD
5
OUTB
FAN3229
Figure 1. Pin Configurations
© 2007 Semiconductor Components Industries, LLC.
October-2017, Rev. 2
Publication Order Number:
FAN3229T-F085/D
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
Dual 2-A High-Speed, Low-Side Gate Drivers
Package
Packing
Method
Quantity
per Reel
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
FAN3226TMX-F085
SOIC-8
Tape & Reel
2,500
FAN3227CMPX
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
CMOS
SOIC-8
Tape & Reel
2,500
TTL
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
Part Number
Input
Threshold
Logic
FAN3226CMPX
FAN3226CMX
CMOS
FAN3226CMX-F085
(1)
FAN3226TMPX
Dual Inverting Channels + Dual
Enable
FAN3226TMX
TTL
(1)
FAN3227CMX
CMOS
FAN3227CMX-F085
(1)
FAN3227TMPX
Dual Non-Inverting Channels +
Dual Enable
FAN3227TMX
TTL
(1)
FAN3227TMX-F085
FAN3228CMX-F085
(1)
(1)
FAN3228TMX-F085
Dual Channels of Two-Input /
One-Output Drivers, Pin
Configuration 1
FAN3229CMPX
FAN3229CMX
CMOS
FAN3229CMX-F085
(1)
FAN3229TMPX
Dual Channels of Two-Input /
One-Output Drivers, Pin
Configuration 2
FAN3229TMX
TTL
(1)
FAN3229TMX-F085
Note:
1. Qualified to AEC-Q100
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2
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Ordering Information
1
8
2
7
3
6
4
5
Figure 2. 3x3 m m MLP-8 (Top View )
1
8
2
7
3
6
4
5
Figure 3. SOIC-8 (Top View )
Thermal Characteristics(2)
ΘJL(3)
ΘJT(4)
ΘJA(5)
Ψ JB(6)
Ψ JT(7)
Unit
8-Lead 3x3 mm Molded Leadless Package (MLP)
1.6
68
43
3.5
0.8
°C/W
8-Pin Small Outline Integrated Circuit (SOIC)
40
31
89
43
3.0
°C/W
Package
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
4.
5.
6.
7.
thermal pad) that are typically soldered to a PCB.
Theta_JT (ΘJT ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
held at a uniform temperature by a top-side heatsink.
Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2,
JESD51-5, and JESD51-7, as appropriate.
Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
application circuit board reference point for the thermal environment defined in Note 5. For the MLP-8 package, the board
reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the
SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
Psi_JT (ΨJT ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
the center of the top of the package for the thermal environment defined in Note 5.
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3
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Package Outlines
1
INA
2
GND
3
INB
A
B
4
8
ENB
7
OUTA
6
VDD
5
ENA
1
INA
2
GND
3
OUTB
INB
4
FAN3226
A
B
8
ENB
INA- 1
7
OUTA
INB+
2
6
VDD
GND
3
OUTB
5
INB-
4
FAN3227
+
A
+
B
-
8
INA+
INA+
7
OUTA
INA- 2
6
VDD
INB+
5
INB-
OUTB
FAN3228
1
+
A
-
3
+
B
-
4
8
GND
7
OUTA
6
VDD
5
OUTB
FAN3229
Figure 4. Pin Configurations (Repeated)
Pin Definitions
Name
Pin Description
ENA
Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and
CMOS INx threshold.
ENB
Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and
CMOS INx threshold.
GND
Ground. Common ground reference for input and output circuits.
INA
Input to Channel A.
INA+
Non-Inverting Input to Channel A. Connect to VDD to enable output.
INA-
Inverting Input to Channel A. Connect to GND to enable output.
INB
Input to Channel B.
INB+
Non-Inverting Input to Channel B. Connect to VDD to enable output.
INB-
Inverting Input to Channel B. Connect to GND to enable output.
OUTA
Gate Drive Output A: Held LOW unless required input(s) are present and V DD is above UVLO threshold.
OUTB
Gate Drive Output B: Held LOW unless required input(s) are present and V DD is above UVLO threshold.
OUTA
Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V DD is
above UVLO threshold.
OUTB
Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V DD is
above UVLO threshold.
Therm al Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected
to GND; NOT suitable for carrying current.
P1
VDD
Supply Voltage. Provides pow er to the IC.
Output Logic
FAN3226 (x=A or B)
FAN3227 (x=A or B)
ENx
INx
OUTx
ENx
0
0
0
0
0
(8)
(8)
1
(8)
1
1
INx
(8)
0
OUTx
0
FAN3228 and FAN3229
(x=A or B)
INx+
INx−
OUTx
(8)
0
0
(8)
(8)
0
0
1
(8)
0
0
0
0
1
0
0
1
(8)
1
(8)
0
1
(8)
0
1
1
1
1
1
0
(8)
Note:
8. Default input signal if no external connection is made.
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4
0
1
1
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
ENA
VDD
VDD
100kΩ
100kΩ
ENA 1
8
ENB
VDD
100kΩ
INA
2
7
OUTA
100kΩ
GND 3
UVLO
6
VDD
VDD_OK
VDD
100kΩ
INB
5
4
OUTB
100kΩ
Figure 5. FAN3226 Block Diagram
VDD
VDD
100kΩ
100kΩ
ENA 1
8
ENB
INA 2
7
OUTA
100kΩ
100kΩ
UVLO
GND 3
6
VDD
VDD_OK
INB 4
5
OUTB
100kΩ
100kΩ
Figure 6. FAN3227 Block Diagram
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5
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Block Diagrams
VDD
INA+ 8
100kΩ
INA-
1
100kΩ
7
OUTA
6
VDD
5
OUTB
8
GND
7
OUTA
6
VDD
5
OUTB
100kΩ
VDD_OK
GND 3
UVLO
VDD
INB+ 2
100kΩ
INB- 4
100kΩ
100kΩ
Figure 7. FAN3228 Block Diagram
VDD
INA+ 1
100kΩ
INA-
2
100kΩ
100kΩ
VDD_OK
UVLO
VDD
INB+ 3
100kΩ
INB-
4
100kΩ
100kΩ
Figure 8. FAN3229 Block Diagram
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6
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Block Diagrams
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
V DD
VDD to PGND
V EN
ENA and ENB to GND
GND - 0.3 V DD + 0.3
V
V IN
INA, INA+, INA–, INB, INB+ and INB– to GND
GND - 0.3 V DD + 0.3
V
OUTA and OUTB to GND
GND - 0.3 V DD + 0.3
V
V OUT
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
+260
ºC
-55
+150
ºC
-65
+150
ºC
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
4.5
18.0
V
V DD
Supply Voltage Range
V EN
Enable Voltage ENA and ENB
0
V DD
V
V IN
Input Voltage INA, INA+, INA–, INB, INB+ and INB–
0
V DD
V
TA
Operating Ambient Temperature
-40
+125
ºC
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7
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Absolute Maximum Ratings
Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min.
Typ. Max. Unit
4.5
18.0
V
0.75
1.20
mA
Supply
V DD
Operating Range
IDD
Supply Current Inputs / EN
Not Connected
TTL
0.65
1.05
mA
V ON
Turn-On Voltage
INA=ENA=V DD, INB=ENB=0 V
3.5
3.9
4.3
V
V OFF
Turn-Off Voltage
INA=ENA=V DD, INB=ENB=0 V
3.3
3.7
4.1
V
(9)
CMOS
FAN322xCMX_F085, FAN322xTMX_F085 (Automotive-Qualified Versions)
V ON
V OFF
(14)
INA=ENA=V DD, INB=ENB=0 V
3.3
3.9
4.5
V
(14)
INA=ENA=V DD, INB=ENB=0 V
3.1
3.7
4.3
V
0.8
1.2
Turn-On Voltage
Turn-Off Voltage
Inputs (FAN322xT)
(10)
V INL_T
INx Logic Low Threshold
V INH_T
INx Logic High Threshold
V HYS_T
TTL Logic Hysteresis Voltage
0.2
V
1.6
2.0
V
0.4
0.8
V
FAN322xT
IIN+
Non-Inverting Input Current
IN from 0 to V DD
-1
175
µA
IIN-
Inverting Input Current
IN from 0 to V DD
-175
1
µA
FAN322xTMX_F085 (Automotive-Qualified Versions)
(14)
IN=0 V
-1.5
1.5
µA
(14)
IN=V DD
90
120
175.0
µA
(14)
IN=0 V
-175
-120
-90
µA
(14)
IN=V DD
-1.5
1.5
µA
IINx_T
Non-inverting Input Current
IINx_T
Non-inverting Input Current
IINx_T
IINx_T
Inverting Input Current
Inverting Input Current
Inputs (FAN322xC)
(10)
V INL_C
INx Logic Low Threshold
30
38
V INH_C
INx Logic High Threshold
55
V HYS_C
CMOS Logic Hysteresis Voltage
17
%V DD
70
%V DD
%V DD
FAN322xC
IIN+
Non-Inverting Input Current
IN from 0 to V DD
-1
175
µA
IIN-
Inverting Input Current
IN from 0 to V DD
-175
1
µA
1.5
µA
FAN322xCMX_F085 (Automotive-Qualified Versions)
IINx_T
IINx_T
(14)
IN=0 V
-1.5
(14)
Non-inverting Input Current
Non-inverting Input Current
IN=V DD
90
120
175.0
µA
(14)
IN=0 V
-175
-120
-90
µA
(14)
IN=V DD
-1.5
1.5
µA
IINx_T
Inverting Input Current
IINx_T
Inverting Input Current
ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T)
V ENL
Enable Logic Low Threshold
EN from 5 V to 0 V
V ENH
Enable Logic High Threshold
EN from 0 V to 5 V
V HYS_T
RPU
(11)
TTL Logic Hysteresis Voltage
(11)
Enable Pull-up Resistance
0.8
1.2
1.6
V
2.0
V
0.4
V
100
kΩ
Continued on the following page…
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8
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Electrical Characteristics
(Continued)
Unless otherw ise noted, V DD=12 V, TJ =-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T) (continued)
tD3
tD4
EN to Output Propagation Delay
(12)
0 V to 5 V EN, 1 V/ns Slew Rate
10
19
34
ns
5 V to 0 V EN, 1 V/ns Slew Rate
10
18
32
ns
FAN3226CMX, FAN3226TMX, FAN3227CMX, FAN3227TMX_F085 (Automotive-Qualified Versions)
tD3
EN to Output Propagation Delay
(12),(14)
tD4
0 V to 5 V EN, 1 V/ns Slew Rate
8
19
35
ns
5 V to 0 V EN, 1 V/ns Slew Rate
8
18
35
ns
Outputs
OUT Current, Mid-Voltage, Sinking
OUT at V DD/2,
CLOAD=0.1 µF, f=1 kHz
2.4
A
ISOURCE
OUT Current, Mid-Voltage,
(11)
Sourcing
OUT at V DD/2,
CLOAD=0.1 µF, f=1 kHz
-1.6
A
IPK_SINK
OUT Current, Peak, Sinking
CLOAD=0.1 µF, f=1 kHz
3
A
CLOAD=0.1 µF, f=1 kHz
-3
A
CLOAD=1000 pF
12
22
ns
CLOAD=1000 pF
9
17
ns
ISINK
IPK_SOURCE
tRISE
tFALL
IRVS
(11)
(11)
(11)
OUT Current, Peak, Sourcing
(13)
Output Rise Time
(13)
Output Fall Time
(11)
Output Reverse Current Withstand
500
mA
FAN322xT, FAN322xC
tD1
tD2
tD1
tD2
tDEL.MATCH
Output Propagation Delay, CMOS
(13)
Inputs
CMOS Input
7
15
30
CMOS Input
6
15
29
Output Propagation Delay, TTL
(13)
Inputs
TTL Input
10
19
34
TTL Input
10
18
32
Propagation Matching Betw een
(14)
Channels
INA=INB, OUTA and OUTB at
50% Point
1
2
ns
ns
ns
FAN322xTMX_F085, FAN322xCMX_F085 (Automotive-Qualified Versions)
tD1
tD2
tD1
tD2
tDEL.MATCH
Output Propagation Delay, CMOS
(13),(14)
Inputs
CMOS Input
7
15
33
CMOS Input
6
15
42
ns
Output Propagation Delay, TTL
(13),(14)
Inputs
TTL Input
9
19
34
TTL Input
9
18
32
Propagation Matching Betw een
(14)
Channels
INA=INB, OUTA and OUTB at
50% Point
2
4
ns
(14)
V OH =V DD–V OUT, IOUT=–1 mA
15
35
mV
(14)
IOUT = 1 mA
10
25
mV
V OH
High Level Output Voltage
V OL
Low Level Output Voltage
Notes:
9. Low er supply current due to inactive TTL circuitry.
10. EN inputs have TTL thresholds; refer to the ENABLE section.
11. Not tested in production.
12. See Timing Diagrams of Figure 11 and Figure 12.
13. See Timing Diagrams of Figure 9 and Figure 10.
14. Apply to only F085 Version
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9
ns
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Electrical Characteristics
90%
90%
Output
Output
10%
Input
10%
VINH
Input
VINL
tD1
VINL
tD2
tD2
tD1
t FALL
t RISE
tRISE
tFALL
Figure 9. Non-Inverting (EN HIGH or Floating)
Figure 10. Inverting (EN HIGH or Floating)
HIGH
HIGH
Input
Input
LOW
LOW
90%
90%
Output
Output
10%
10%
Enable
VINH
VENH
Enable
VENL
tD3
VENL
tD3
tD4
t RISE
VENH
t FALL
Figure 11. Non-Inverting (IN HIGH)
tD4
t RISE
Figure 12. Inverting (IN LOW)
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10
t FALL
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Timing Diagrams
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
1.6
1.6
1.2
1.2
1.0
1.0
0.8
0.6
0.4
0.8
0.6
0.4
Inputs and Enables
Floating, Outputs
0.2
TTL Input
1.4
FAN3226C, 27C
IDD (mA)
IDD (mA)
1.4
Inputs and Enables
Floating, Outputs Low
0.2
0.0
0.0
4
6
8
10
12
14
16
18
4
6
Supply Voltage (V)
8
10
12
14
16
18
Supply Voltage (V)
Figure 13. IDD (Static) vs. Supply Voltage
(15)
Figure 14. IDD (Static) vs. Supply Voltage
(15)
1.6
FAN3228C, 29C
1.4
IDD (mA)
1.2
1.0
All Inputs Floating,
Outputs Low
0.8
0.6
0.4
0.2
0.0
4
6
8
10
12
14
16
V DD - Supply Voltage (V)
Figure 15. IDD (Static) vs. Supply Voltage
Figure 16. IDD (No-Load) vs. Frequency
18
(15)
Figure 17. IDD (No-Load) vs. Frequency
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11
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 18. IDD (1 nF Load) vs. Frequency
Figure 19. IDD (1 nF Load) vs. Frequency
1.6
1.4
1.2
1.0
1.0
IDD (mA)
1.2
0.8
0.6
Inputs and Enables
Floating, Outputs
0.4
0.2
0.0
-50
-25
0
25
50
75
Tem perature (°C)
100
Figure 20. IDD (Static) vs. Tem perature
TTL Input
0.8
0.6
Inputs and Enables
Floating, Outputs
0.4
0.2
125
(15)
0.0
-50
-25
0
25
50
75
Tem perature (°C)
1.4
FAN3228C, 29C
1.2
1.0
0.8
0.6
0.4
All Inputs Floating,
Outputs Low
0.2
0.0
-50
-25
100
Figure 21. IDD (Static) vs. Tem perature
1.6
IDD (mA)
IDD (mA)
1.4
1.6
FAN3226C, 27C
75
0
25
50
Tem perature (°C)
100
Figure 22. IDD (Static) vs. Tem perature
www.onsemi.com
12
(15)
125
(15)
125
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 23. Input Thresholds vs. Supply Voltage
Figure 24. Input Thresholds vs. Supply Voltage
Figure 25. Input Threshold % vs. Supply Voltage
Figure 26. Input Thresholds vs. Tem perature
Figure 27. Input Thresholds vs. Tem perature
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13
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 28. UVLO Thresholds vs. Tem perature
Figure 29. UVLO Threshold vs. Tem perature
Figure 30. Propagation Delays vs. Supply Voltage
Figure 31. Propagation Delays vs. Supply Voltage
Figure 32. Propagation Delays vs. Supply Voltage
Figure 33. Propagation Delays vs. Supply Voltage
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14
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 34. Propagation Delays vs. Tem perature
Figure 35. Propagation Delays vs. Tem perature
Figure 36. Propagation Delays vs. Tem perature
Figure 37. Propagation Delays vs. Tem perature
Figure 38. Fall Tim e vs. Supply Voltage
Figure 39. Rise Tim e vs. Supply Voltage
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15
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 40. Rise and Fall Tim es vs. Tem perature
Figure 41. Rise/Fall Waveform s w ith 1 nF Load
Figure 42. Rise/Fall Waveform s w ith 10 nF Load
Figure 43. Quasi-Static Source Current w ith V DD=12 V
Figure 44. Quasi-Static Sink Current w ith V DD=12 V
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16
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Typical characteristics are provided at 25°C and V DD=12 V unless otherw ise noted.
Figure 45. Quasi-Static Source Current w ith V DD=8 V
Figure 46. Quasi-Static Sink Current w ith V DD=8 V
Note:
15. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high, static IDD increases by
the current flow ing through the corresponding pull-up/dow n resistor show n in the block diagram.
Test Circuit
VDD
120µF
Al. El.
4.7µF
ceramic
Current Probe
LECROY AP015
IN
1kHz
IOUT
1µF
ceramic
VOUT
CLOAD
0.1µF
Figure 47. Quasi-Static IOUT / V OUT Test Circuit
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17
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Performance Characteristics
Input Thresholds
MillerDrive™ Gate Drive Technology
Each member of the FA N322x driver family consists of
tw o identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FA N3226 and
FA N3227, channels A and B can be enabled or disabled
independently using ENA or ENB, respectively. The EN
pin has TTL thresholds for parts w ith either CMOS or
TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the dr iver
channels by default. If the channel A and channel B
inputs and outputs are connected in parallel to increase
the driver current capacity, ENA and ENB should be
connected and driven together.
FA N322x gate drivers incorporate the Miller Drive™
architecture show n in Figure 48. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a w ide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT sw ings betw een 1/3 to 2/3
V DD and the MOS devices pull the output to the high or
low rail.
The FA N322x family offers versions in either TTL or
CMOS input thresholds. In the FA N322x T, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the V DD voltage, and there is a
hysteresis voltage of approximately 0.4 V. These levels
per mit the inputs to be driven from a range of input logic
signal levels for w hich a voltage over 2 V is considered
logic high. The dr iving signal for the TTL inputs should
have fast rising and falling edges w ith a slew rate of
6 V/µs or faster, so a r ise time from 0 to 3.3 V should be
550 ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the dr iver input, causing
erratic operation.
For applications that have zero voltage sw itching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast sw itching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectif ier applications
because the body diode is generally conducting before
the MOSFET is sw itched on.
In the FA N322x C, the logic input thresholds are
dependent on the V DD level and, w ith VDD of 12 V, the
logic rising edge threshold is approximately 55% of V DD
and the input falling edge threshold is approximately
38% of V DD. The CMOS input configuration offers a
hysteresis voltage of approximately 17% of V DD. The
CMOS inputs can be used w ith relatively s low edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
w indow . This allow s setting precise timing intervals by
fitting an R- C c ircuit betw een the controlling signal and
the IN pin of the dr iver. The s low rising edge at the IN
pin of the driver introduces a delay betw een the
controlling signal and the OUT pin of the driver.
Static Supply Current
In the IDD (static) typical performance characteristics
(see Figure 13 - Figure 15 and Figure 20 - Figure 22),
the curve is produced w ith all inputs / enables floating
(OUT is low ) and indicates the low est static IDD current
for the tested configuration. For other states, additional
current flows through the 100 kΩ resistors on the inputs
and outputs show n in the block diagram of each part
(see Figure 5 - Figure 8). In these cases, the actual
static IDD current is the value obtained from the curves
plus this additional current.
The purpose of the Miller Drive™ architecture is to
speed up sw itching by providing high current during the
Miller plateau region w hen the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
The output pin slew rate is determined by V DD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slow er rise or fall time
at the MOSFET gate is needed.
VDD
Input
stage
VOUT
Figure 48. MillerDrive™ Output Architecture
Under-Voltage Lockout
The FAN322x startup logic is optimized to drive groundreferenced N-channel MOSFETs w ith an under-voltage
lockout ( UVLO) function to ensure that the IC starts up
in an orderly fashion. When V DD is rising, yet below the
3.9 V operational level, this circuit holds the output low ,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.2 V before the
part shuts dow n. This hysteresis helps prevent chatter
when low V DD supply voltages have noise from the
pow er sw itching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver w ould turn the P-channel
MOSFET on w ith V DD below 3.9 V.
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18
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Applications Information
To enable this IC to turn a device on quickly, a local highfrequency bypass capacitor CBYP w ith low ESR and ESL
should be connected betw een the VDD and GND pins
with minimal trace length. This capacitor is in addition to
bulk electrolytic capacitance of 10 µF to 47 µF commonly
found on driver and controller bias circuits.
A typical criterion for choosing the value of CBYP is to
keep the r ipple voltage on the V DD supply to ≤5%. This
is often achieved w ith a value ≥20 times the equivalent
load capacitance CEQV, defined here as QGATE/V DD.
Ceramic capacitors of 0.1 µF to 1 µF or larger are
common choices, as are dielectrics, such as X5R and
X7R w ith good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
CBYP may be increased to 50-100 times the CEQV, or
CBYP may be split into tw o capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a s maller value, such as 1-10 nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
sw itching simultaneously, the combined peak current
sourced from the CBYP w ould be tw ice as large as w hen
a single channel is sw itching.
best results, make connections to all pins as short
and direct as possible.
The FAN322x is compatible w ith many other
industry-standard drivers. In single input parts w ith
enable pins, there is an internal 100 kΩ res istor tied
to V DD to enable the driver by default; this should be
considered in the PCB layout.
The turn-on and turn-off current paths should be
minimized, as discussed in the follow ing section.
Figure 49 show s the pulsed gate drive current path
when the gate dr iver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor, CBYP, and flow s through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized CBYP acts
to contain the high peak current pulses w ithin this driverMOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
VDD
CBYP
Layout and Connection Guidelines
FAN322x
The FA N3226-26 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and pow erful output stages capable of delivering current
peaks over 2 A to facilitate voltage transition times from
under 10 ns to over 150 ns. The follow ing layout and
connection guidelines are strongly recommended:
Keep high-current output and pow er ground paths
separate logic and enable input signals and signal
ground paths. This is espec ially critical w hen
dealing w ith TTL-level logic thresholds at driver
inputs and enable pins.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the ser ies inductance to improve highspeed sw itching, w hile reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
PWM
Figure 49. Current Path for MOSFET Turn-on
Figure 50 show s the current path w hen the gate dr iver
turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a s mall
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
VDD
VDS
CBYP
If the inputs to a channel are not externally
connected, the internal 100 kΩ resistors indicated
on bloc k diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to V DD or GND using short
traces to prevent noise from causing spur ious
output sw itching.
Many high-speed pow er circuits can be susceptible
to noise injected from their ow n output or other
external sources, possibly caus ing output retriggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts w ith long input, enable, or output leads. For
VDS
FAN322x
PWM
Figure 50. Current Path for MOSFET Turn-off
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19
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
VDD Bypass Capacitor Guidelines
Operational Waveforms
The FAN3228/FA N3229 truth table indicates the
operational states using the dual- input configuration. In
a non-inverting driver configuration, the IN- pin should
be a logic low signal. If the IN- pin is connected to logic
high, a disable function is realized, and the driver output
remains low regardless of the state of the IN+ pin.
At pow er-up, the driver output remains low until the V DD
voltage reaches the turn-on threshold. The magnitude of
the OUT pulses rises w ith V DD until steady-state V DD is
reached. The non-inverting operation illustrated in
Figure 53 show s that the output remains low until the
UVLO threshold is reached, the output is in-phase w ith
the input.
IN+
IN-
OUT
0
0
0
0
1
0
1
0
1
1
1
0
VDD
In the non- inverting dr iver configuration in Figure 51, the
IN- pin is tied to ground and the input signal ( PWM) is
applied to IN+ pin. The IN- pin can be connected to logic
high to disable the dr iver and the output remains low ,
regardless of the state of the IN+ pin.
Turn-on threshold
IN-
IN+
VDD
PWM
IN+
IN-
FAN3228/9
OUT
OUT
Figure 53. Non-Inverting Startup Waveform s
GND
For the inverting configuration of Figure 52, startup
waveforms are show n in Figure 54. With IN+ tied to V DD
and the input signal applied to IN–, the OUT pulses are
inverted w ith respect to the input. At pow er-up, the
inverted output remains low until the V DD voltage
reaches the turn-on threshold, then it follow s the input
w ith inverted phase.
Figure 51. Dual-Input Driver Enabled,
Non-Inverting Configuration
In the inverting driver application in Figure 52, the IN+
pin is tied high. Pulling the IN+ pin to GND forces the
output low , regardless of the state of the IN- pin.
VDD
Turn-on threshold
VDD
IN-
IN+
PWM
IN-
FAN3228/9
OUT
IN+
(VDD)
GND
OUT
Figure 52. Dual-Input Driver Enabled,
Inverting Configuration
Figure 54. Inverting Startup Waveform s
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20
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Truth Table of Logic Operation
Gate dr ivers used to sw itch MOSFETs and IGBTs at
high frequencies can dissipate s ignificant amounts of
pow er. It is important to deter mine the driver pow er
dissipation and the resulting junction temperature in the
application to ensure that the part is operating w ithin
acceptable temperature limits.
The total pow er dissipation in a gate dr iver is the sum of
tw o components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
Gate Dr iving Loss: The most significant pow er loss
results from supplying gate current (charge per unit
time) to sw itch the load MOSFET on and off at the
sw itching frequency. The pow er dissipation that
results from driving a MOSFET at a specified gatesource voltage, V GS, w ith gate charge, QG, at
sw itching frequency, f SW, is determined by:
PGATE = QG • V GS • f SW • n
(2)
n is the number of driver channels in use (1 or 2).
Dynamic Pr e-drive / Shoot-through Current: A
pow er loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-dow n resistors, can be
obtained using the “ IDD ( No-Load) vs. Frequency”
graphs in Typical Performance Character istics to
deter mine the current IDYNAMIC draw n from V DD
under actual operating conditions:
PDYNAMIC = IDYNAMIC • V DD • n
(3)
Once the pow er dissipated in the driver is deter mined,
the driver junction rise w ith respect to circuit board can
be evaluated using the follow ing ther mal equation,
assuming ψ JB w as determined for a similar ther mal
design (heat sinking and air flow ):
TJ
= PTOTAL • ψ JB + TB
In the forw ard converter w ith synchronous rectifier
show n in the typical application diagrams, the
FDMS8660S is a reasonable MOSFET selection. The
gate charge for each SR MOSFET w ould be 60 nC w ith
V GS = VDD = 7V. At a sw itching frequency of 500 kHz,
the total pow er dissipation is:
PGATE = 60 nC • 7 V • 500 kHz • 2 = 0.42 W
(5)
PDYNAMIC = 3 mA • 7 V • 2 = 0.042 W
(6)
PTOTAL = 0.46 W
(7)
The SOIC-8 has a junction-to-board ther mal
characterization parameter of ψJB = 43°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along w ith airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; w ith 80%
derating, TJ w ould be limited to 120°C. Rearranging
Equation 4 deter mines the board temperature required
to maintain the junction temperature below 120°C:
TB = TJ - PTOTAL • ψ JB
(8)
TB = 120°C – 0.46 W • 43°C/W = 100°C
(9)
For comparison, replace the SOIC-8 used in the
previous example w ith the 3x3 mm MLP package w ith
ψ JB = 3.5°C/W. The 3x3 mm MLP package could
operate at a PCB temperature of 118°C, w hile
maintaining the junction temperature below 120°C. This
illustrates that the physically s maller MLP package w ith
ther mal pad offers a more conductive path to remove
the heat from the dr iver. Consider tradeoffs betw een
reducing overall circuit size w ith junction temperature
reduction for increased reliability.
(4)
w here:
= driver junction temperature
TJ
ψ JB = (psi) thermal characterization parameter
relating temperature rise to total pow er
dissipation
TB
= board temperature in location defined in Note
2 under Thermal Resistance table.
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21
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
Thermal Guidelines
VIN
VIN
VOUT
FAN3227
1
8
PWMA
2
7
GND
3
6
PWMB
4
5
PWM
Timing/
Isolation
1
8
2
7
3
6
4
5
Vbias
OUTA
VDD
OUTB
FAN3227
Figure 55. Forw ard Converter
w ith Synchronous Rectification
Figure 56.
Prim ary-Side Dual Driver
in a Push-Pull Converter
VIN
FAN3227
ENB 8
1 ENA
PWM-A
2
A
3 GND
PWM-B
4
7
VDD 6
B
5
Vbias
FAN3227
PWM-C
2
Phase Shift
Controller
PWM-D
ENB 8
1 ENA
A
3 GND
4
7
VDD 6
B
Vbias
5
Figure 57. Phase-Shifted Full-Bridge w ith Tw o Gate Drive Transform ers (Sim plified)
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22
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Typical Application Diagrams
Type
Part
Num ber
(16)
Gate Drive
(Sink/Src)
Input
Threshold
Logic
Package
Single 1 A FAN3111C +1.1 A / -0.9 A
CMOS
Single Channel of Dual-Input/Single-Output
Single 1 A FAN3111E
External (17)
Single Non-Inverting Channel with External Reference SOT23-5, MLP6
Single 2 A FAN3100C +2.5 A / -1.8 A
CMOS
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
Single 2 A FAN3100T
+2.5 A / -1.8 A
TTL
Single Channel of Two-Input/One-Output
SOT23-5, MLP6
Single 2 A FAN3180
+2.4 A / -1.6 A
TTL
Single Non-Inverting Channel + 3.3-V LDO
SOT23-5
Dual 2 A
FAN3216T
+2.4 A / -1.6 A
TTL
Dual Inverting Channels
SOIC8
Dual 2 A
FAN3217T
+2.4 A / -1.6 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 2 A
FAN3226C +2.4 A / -1.6 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3226T
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3227C +2.4 A / -1.6 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3227T
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 2 A
FAN3228C +2.4 A / -1.6 A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8
Dual 2 A
FAN3228T
TTL
Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8
Dual 2 A
FAN3229C +2.4 A / -1.6 A
CMOS
Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8
Dual 2 A
FAN3229T
+2.4 A / -1.6 A
TTL
Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8
Dual 2 A
FAN3268T
+2.4 A / -1.6 A
TTL
20 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 2 A
FAN3278T
+2.4 A / -1.6 A
TTL
30 V Non-Inverting Channel (NMOS) and Inverting
Channel (PMOS) + Dual Enables
SOIC8
Dual 4 A
FAN3213T
+2.5 A / -1.8 A
TTL
Dual Inverting Channels
SOIC8
Dual 4 A
FAN3214T
+2.5 A / -1.8 A
TTL
Dual Non-Inverting Channels
SOIC8
Dual 4 A
FAN3223C +4.3 A / -2.8 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3223T
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3224C +4.3 A / -2.8 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3224T
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual 4 A
FAN3225C +4.3 A / -2.8 A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
Dual 4 A
FAN3225T
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
Single 9 A FAN3121C +9.7 A / -7.1 A
CMOS
Single Inverting Channel + Enable
SOIC8, MLP8
Single 9 A FAN3121T
+9.7 A / -7.1 A
TTL
Single Inverting Channel + Enable
SOIC8, MLP8
Single 9 A FAN3122T
+9.7 A / -7.1 A
CMOS
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Single 9 A FAN3122C +9.7 A / -7.1 A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
Dual 12 A FAN3240
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 0
SOIC8
Dual 12 A FAN3241
+12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 1
SOIC8
+1.1 A / -0.9 A
+2.4 A / -1.6 A
+2.4 A / -1.6 A
+2.4 A / -1.6 A
+4.3 A / -2.8 A
+4.3 A / -2.8 A
+4.3 A / -2.8 A
Notes:
16. Typical currents w ith OUTx at 6 V and V DD=12 V.
17. Thresholds proportional to an externally supplied reference voltage.
www.onsemi.com
23
SOT23-5, MLP6
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Table 1. Related Products
2X
2X
0.8 MAX
RECOMMENDED LAND PATTERN
0.05
0.00
SEATING
PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION VEEC, DATED 11/2001
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. FILENAME: MKT-MLP08Drev2
Figure 58. 3x3 m m , 8-Lead Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms
and conditions, specifically the warranty therein, which covers ON Semiconductor products.
www.onsemi.com
24
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Physical Dimensions
(Continued)
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
1.75 MAX
R0.10
0.10
0.51
0.33
0.50 x 45°
0.25
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
8°
0°
0.90
0.406
0.25
0.19
C
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
Figure 59. 8-Lead, Sm all Outline Integrated Curcuit (SOIC)
Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms
and conditions, specifically the warranty therein, which covers ON Semiconductor products.
www.onsemi.com
25
FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
FAN3226 / FAN3227 / FAN3228 / FAN3229
D l 2 A Hi h S
d L
Sid G t D i
Physical Dimensions
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FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2-A High-Speed, Low-Side Gate Drivers
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D l 2 A Hi h S
d L
Sid G t D i
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