DATA SHEET
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5 A, 2.4 MHz, Digitally
Programmable TinyBuck
Regulator
WLCSP20
CASE 567QK, 567SH, 567SK
FAN53555
ORDERING INFORMATION
Description
See detailed ordering and shipping information on page 2
of this data sheet.
The FAN53555 is a step−down switching voltage
regulator that delivers a digitally programmable output from
an input voltage supply of 2.5 V to 5.5 V. The output voltage
is programmed through an I2C interface capable of
operating up to 3.4 MHz.
Using a proprietary architecture with synchronous
rectification, the FAN53555 is capable of delivering 5 A
continuous at over 80% efficiency, while maintaining over
80% efficiency at load currents as low as 10 mA. Pulse
currents as high as 6.5 A can be supported by the 05 option.
The regulator operates at a nominal fixed frequency of
2.4 MHz, which reduces the value of the external
components to 330 nH for the output induction and as low
as 20 mF for the output capacitor. Additional output
capacitance can be added to improve regulation during load
transients without affecting stability. Inductance up to
1.2 mH may be used with additional output capacitance.
At moderate and light loads, Pulse Frequency Modulation
(PFM) is used to operate in Power−Save Mode with a typical
quiescent current of 60 mA. Even with such a low quiescent
current, the part exhibits excellent transient response during
large load swings. At higher loads, the system automatically
switches to fixed−frequency control, operating at 2.4 MHz.
In Shutdown Mode, the supply current drops below 1 mA,
reducing power consumption. PFM Mode can be disabled if
constant frequency is desired. The FAN53555 is available in
a 20−bump, 1.6 × 2 mm, WLCSP.
• Pulse Current Capability: 6.5 A (05 Option)
• 2.5 V to 5.5 V Input Voltage Range
• Digitally Programmable Output Voltage:
00/01/03/05/08/18 Options: 0.6−1.23 V in 10 mV
Steps
♦ 04/042/09/ Options: 0.603−1.411 V in 12.826 mV
Steps
♦ 23, 79 Option: 0.60−1.3875 V in 12.5 mV Steps
♦ 24 Option: 0.603−1.420 V in 12.967 mV Steps
♦ 13 Option: 0.8−1.43 V in 10 mV Steps
Programmable Slew Rate for Voltage Transitions
I2C−Compatible Interface Up to 3.4 Mbps
PFM Mode for High Efficiency in Light Load
Quiescent Current in PFM Mode: 60 mA (Typical)
Internal Soft−Start
Input Under−Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
20−Bump Wafer−Level Chip Scale Package (WLCSP)
♦
•
•
•
•
•
•
•
•
Applications
• Application, Graphic, and DSP Processors
•
•
•
•
Features
• Fixed−Frequency Operation: 2.4 MHz
• Best−in−Class Load Transient
• Continuous Output Current Capability: 5 A
Arm®, Krait, OMAPt, NovaThort, ARMADA
Hard Disk Drives
Tablets, Netbooks, Ultra−Mobile PCs
Smart Phones
Gaming Devices
PVIN
C IN1
EN
VOUT
SDA
SCL
VSEL
C IN
FAN53555
SW
L1
C OUT
GND
AGND
VDD
Core
Processor
(System Load)
GND
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2010
January, 2022 − Rev. 7
1
Publication Order Number:
FAN53555/D
FAN53555
Table 1. ORDERING INFORMATION
Top Mark
VSEL0
VSEL1
I2C
Slave
Address
FAN53555UC00X
BK
1.05
1.20
C0
FAN53555UC01X
BL
0.90
OFF
VSEL
5A
FAN53555UC03X
BN
0.90
N/A
PGOOD
5A
FAN53555UC04X
BP
1.10
1.20
VSEL
FAN53555UC05X*
BU
0.90
OFF
FAN53555BUC05X (Note 1)
BU
0.90
FAN53555UC08X*
BW
FAN53555BUC08X (Note 1)
BJ
FAN53555BUC09X (Note 1)
Power−Up Defaults
A1 PIN
Function
Max.
RMS
Current
VSEL
5A
Programmable
Output Voltage
EN Pin Low
0.6−1.23 V in
10 mV
Registers
not reset
5A
0.603−1.411 V
in 12.826 mV
Registers
reset
VSEL
5A
OFF
VSEL
5A
0.6−1.23 V in
10 mV
Registers
not reset
1.02
1.15
VSEL
4A
1.02
1.15
VSEL
4A
CP
1.10
1.10
VSEL
3A
FAN53555UC09X*
CP
1.10
1.10
VSEL
3A
FAN53555UC13X
CT
1.15
1.15
VSEL
5A
FAN53555BUC13X (Note 1)
CT
1.15
1.15
VSEL
5A
FAN53555UC18X*
CU
1.02
1.15
VSEL
5A
FAN53555BUC18X (Note 1)
CU
1.02
1.15
VSEL
5A
FAN53555BUC79X
FU
0.85
N/A
PGOOD
5A
FAN53555BUC23X (Note 1)
CW
1.15
1.15
VSEL
5A
0.6−1.3875 V in
12.5 mV
Registers
not reset
FAN53555UC24X
CR
1.225
1.212
VSEL
4A
FAN53555BUC24X (Note 1)
CR
1.225
1.212
VSEL
4A
0.603−1.42 V in
12.967 mV
Registers
reset
FAN53555UC042X (Note 2)
BX
1.10
1.20
VSEL
5A
Part Number
C4
0.603−1.411 V
in 12.826 mV
0.8−1.43 V in
10 mV
0.6−1.23 V in
10 mV
Registers
reset
0.603−1.411 V
in 12.826 mV
1. The FAN53555BUC05X, FAN53555BUC08X, FAN53555BUC09X, FAN53555BUC13X, FAN53555BUC18X, FAN53555BUC23X, and
FAN53555BUC24X, include backside lamination.
2. The 042 option is the same as the 04 option, except the I2C slave addresses.
3. Temperature Range −40 to 85 °C, Package WLCSP−20, Packing Method Tape & Reel
*This device is End of Life. Please contact sales for additional information and assistance with replacement devices.
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2
FAN53555
RECOMMENDED EXTERNAL COMPONENTS
Table 2. RECOMMENDED EXTERNAL COMPONENTS FOR 5 A MAXIMUM LOAD CURRENT
Component
Description
Vendor
L1
330 nH Nominal
See Table 3
Parameter
Typ.
L
0.33
mH
DCR
13
mW
mF
COUT
2 Pieces;
22 mF, 6.3 V, X5R, 0805
GRM21BR60J226M (Murata)
C2012X5R0J226M (TDK)
C
44
CIN
1 Piece;
10 mF, 10 V, X5R, 0805
LMK212BJ106KG−T (Taiyo Yuden)
C2012X5R1A106M (TDK)
C
10
2 Pieces;
10 mF, 6.3 V, X5R, 0805
GRM21BR60J106M (Murata)
C2012X5R0J106M (TDK)
C
20
10 nF, 25 V, X7R, 0402
GRM155R71E103K (Murata)
C1005X7R1E103K (TDK)
C
10
CIN1
Unit
nF
Table 3. RECOMMENDED INDUCTORS FOR HIGH−CURRENT APPLICATIONS
Manufacturer
Part#
L (nH)
DCR (mW)
IMAXDC
(Note 4)
Vishay
IHLP1616ABERR47M01
470
20.0
Mag. Layers (Note 5)
MMD−04ABNR33M−M1−RU
330
Mag. Layers
MMD−04ABNR47M−M1−RU
470
Inter−Technical
SM1608−R33M
Bournes
Component Dimensions
L
W
H
5.0
4.5
4.1
1.2
12.5
7.5
4.5
4.1
1.2
20.0
5.0
4.5
4.1
1.2
330
9.6
9.0
4.5
4.1
2.0
SRP4012−R33M
330
15.0
6.7
4.7
4.2
1.2
Bournes
SRP4012−R47M
470
20.0
5.0
4.7
4.2
1.2
TDK
VLC5020T−R47M
470
15.0
5.4
5.0
5.0
2.0
4. IMAXDC is the lesser current to produce 40°C temperature rise or 30% inductance roll−off.
5. Preferred inductor value is 330 nH and all dynamic characterization was performed with this coil.
FAN53555−24, −08, and −09 REDUCED OUTPUT CURRENT
(4 A Max. RMS. for 08, and 24, 3 A Max. RMS for 09) SMALLER FOOTPRINT APPLICATION
assume that additional bypass capacitance exists across the
battery in fairly close proximity to the regulator(s). The CIN
capacitors specified below are the capacitors that are
required in very close proximity to VIN and PGND (see
layout recommendations in Figure 2 below).
The FAN53555−24, −08, and −09 were developed to
provide power for core processors with high−performance
graphics acceleration in Li−Ion−powered handheld devices.
These applications require a very compact solution. The
smaller input and output capacitors in the table below
Table 4. RECOMMENDED EXTERNAL COMPONENTS FOR LOWER−CURRENT APPLICATIONS WITH
FAN53555−08−09−24
Component
Description
L1
470 or 330 nH, 2016 case size
COUT
−08, ,24 Option
2 Pieces 22 mF, 6.3 V, X5R, 0603
Vendor
Parameter
Typ
Unit
C
44
mF
See Table 5
C1608X5R0J226M (TDK)
−09 Option
1 Piece 22 mF, 6.3 V, X5R, 0603
22
CIN
1 Piece;
10 mF, 10 V, X5R, 0402
GRM155R61A106M (Murata)
C
10
CIN1
10 nF, 25 V, X5R, 0201
TMK063CG100DT−F (Taiyo Yuden)
C
10
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3
nF
FAN53555
Table 5. RECOMMENDED INDUCTORS FOR LOWER−CURRENT APPLICATIONS WITH FAN53555−08−09−24
Manufacturer
Part#
L (nH)
DCR (mW Typ.)
IMAXDC
(Note 6)
Toko
DFE201612R-H−R33N
330
25
Toko
DFE201612C−R47N
470
40
Cyntek
PIFE20161B−R47MS−39
470
SEMCO
CIGT201610HMR47SCE
470
Component Dimensions
L
W
H
3.2
2.0
1.6
1.2
3.2
2.0
1.6
1.2
30
3.1
2.0
1.6
1.2
30
3.1
2.0
1.6
0.9
6. IMAXDC is the lesser current to produce 40°C temperature rise or 30% inductance roll−off.
LAYOUT
Figure 2. Reduced−Footprint Layout
PIN CONFIGURATION
VSEL*
EN
SCL
VOUT
A1
A2
A3
A4
B2
B3
B4
C2
C3
C4
D1
D2
D3
D4
E1
E2
E3
E4
SDA
AGND
B1
GND
C1
VIN
SW
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
A1 = VSEL for 00, 01, 04, 05, 08, 09, 13, 18, 23, 24
A1 = PGOOD for 03,79
Figure 3. Top View
Figure 4. Bottom View
Table 6. PIN DEFINITIONS
Pin #
Name
A1
VSEL
(Except −03
Option)
PGOOD
(03)
Description
Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is HIGH, VOUT is
set by the VSEL1 register.
Power Good. This open−drain pin pulls LOW if an overload condition occurs or soft−start is in progress.
A2
EN
Enable. The device is in Shutdown Mode when this pin is LOW. All register values are kept during shutdown. Options 00, 01, 03, 05, 08 09, 13, 18, and 23 do not reset register values when EN is raised. The 04,
24, 79, and 042 options reset all registers to default values when EN pin is LOW. If pulled up to a low−impedance voltage source greater than 1.8 V, use at least 100 W series resistor.
A3
SCL
I2C Serial Clock
A4
VOUT
B1
SDA
I2C Serial Data
B2, B3,
C1 – C4
GND
Ground. Low−side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path
to these pins.
B4
AGND
Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin.
VOUT. Sense pin for VOUT. Connect to COUT.
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FAN53555
Table 6. PIN DEFINITIONS (continued)
Pin #
Name
Description
D1, D2,
E1, E2
VIN
Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path.
D3, D4,
E3, E4
SW
Switching Node. Connect to the inductor.
Table 7. ABSOLUTE MAXIMUM RATINGS
Symbol
VIN
Parameter
Voltage on SW, VIN Pins
Voltage on EN Pin
Min
Max
Unit
IC Not Switching
−0.3
7.0
V
IC Switching
−0.3
6.5
Tied without Series Resistance
−0.3
2.0
Tied through Series Resistance of
at Least 100 W
−0.3
VIN (Note 7)
IC Not Switching
−0.3
VIN (Note 7)
V
−0.3
3.0
V
100
V/ms
Voltage on All Other Pins
VOUT
Voltage on VOUT Pin
VINOV_SLEW
Maximum Slew Rate of VIN > 6.5 V, PWM Switching
ESD
Electrostatic Discharge Protection Level
Human Body Model per
JESD22−A114
2000
Charged Device Model per
JESD22−C101
1500
V
V
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
TL
Lead Soldering Temperature, 10 Seconds
+260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
7. Lesser of 7 V or VIN + 0.3 V.
Table 8. RECOMMENDED OPERATING CONDITIONS
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions
are specified to ensure optimal performance to the datasheet specifications. onsemi does not recommend exceeding them or designing
to Absolute Maximum Ratings.
Symbol
Parameter
VIN
Supply Voltage Range
IOUT
Output Current
L
CIN
COUT
Min
Max
Unit
2.5
5.5
V
0
5
A
Inductor
Typ
0.33
mH
Input Capacitor
10
mF
Output Capacitor
44
mF
TA
Operating Ambient Temperature
−40
+85
°C
TJ
Operating Junction Temperature
−40
+125
°C
Table 9. THERMAL PROPERTIES
Symbol
θJA
Parameter
Min
Junction−to−Ambient Thermal Resistance (Note 8)
Typ
38
8. See Thermal Considerations in the Application Information section.
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5
Max
Unit
°C/W
FAN53555
Table 10. ELECTRICAL CHARACTERISTICS
Minimum and maximum values are at VIN = 2.5 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. Typical values are at
TA = 25°C, VIN = 5 V, and EN = HIGH.
Parameter
Typ
Max
Unit
ILOAD = 0
60
100
mA
ILOAD = 0, MODE Bit = 1 (Forced PWM)
43
H/W Shutdown Supply Current
EN = GND
0.1
Symbol
Condition
Min
POWER SUPPLIES
IQ
ISD
Quiescent Current
S/W Shutdown Supply Current
EN = VIN, BUCK_ENx = 0
VUVLO
Under−Voltage Lockout Threshold
VIN Rising
VUVHYST
Under−Voltage Lockout Hysteresis
mA
5.0
mA
41
75
mA
2.35
2.45
V
350
mV
EN, VSEL, SDA, SCL
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
VLHYST
IIN
1.1
0.4
Logic Input Hysteresis Voltage
Input Bias Current
V
160
Input Tied to GND or VIN
0.01
V
mV
1.00
mA
1
mA
1.00
mA
PGOOD (03, 79 OPTION)
IOUTL
PGOOD Pull−Down Current
IOUTH
PGOOD HIGH Leakage Current
0.01
VOUT REGULATION
VREG
DVOUT
DILOAD
VOUT DC Accuracy
IOUT(DC) = 0, Forced PWM, VOUT = VSEL0
Default Value
−1.5
1.5
%
08, 24
Options
2.5 V ≤ VIN ≤ 4.5 V, VOUT
from Minimum to Maximum,
IOUT(DC) = 0 to 4 A, Auto
PFM/PWM
−2.0
4.0
%
09 Option
2.5 V ≤ VIN ≤ 4.5 V, VOUT
from Minimum to Maximum,
IOUT(DC) = 0 to 3 A, Auto
PFM/PWM
−2.0
4.0
%
13, 18, 23
Options
2.5 V ≤ VIN ≤ 4.5 V, VOUT
from Minimum to Maximum,
IOUT(DC) = 0 to 5 A, Auto
PFM/PWM
−2.0
4.0
%
All Other
Options
2.5 V ≤ VIN ≤ 5.5 V, VOUT
from Minimum to Maximum,
IOUT(DC) = 0 to 5 A, Auto
PFM/PWM
−3.0
5.0
%
Load Regulation
IOUT(DC) = 1 to 5 A
−0.1
%/A
Line Regulation
2.5 V ≤ VIN ≤ 5.5 V, IOUT(DC) = 1.5 A
0.01
%/V
Transient Response
ILOAD Step 0.1 A to 1.5 A, tr = tf = 100 ns,
VOUT = 1.2 V
±40
mV
DVOUT
DVIN
VTRSP
POWER SWITCH AND PROTECTION
RDS(on)P
P−Channel MOSFET On Resistance
VIN = 5 V
28
mW
RDS(on)N
N−Channel MOSFET On Resistance
VIN = 5 V
17
mW
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FAN53555
Table 10. ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VIN = 2.5 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. Typical values are at
TA = 25°C, VIN = 5 V, and EN = HIGH.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
00, 01, 03, 04, 13, 18, 23, 042, 79 Options
6.3
7.4
8.5
A
05 Option
8.5
10.0
11.5
A
08, 24 Options
5.0
5.9
6.8
A
09 Option
4.0
4.75
5.5
POWER SWITCH AND PROTECTION
ILIMPK
P−MOS Peak Current Limit
TLIMIT
Thermal Shutdown
150
°C
THYST
Thermal Shutdown Hysteresis
17
°C
VSDWN
Input OVP Shutdown
6.15
V
5.50
5.85
V
2.05
2.40
Rising Threshold
Falling Threshold
FREQUENCY CONTROL
fSW
Oscillator Frequency
2.75
MHz
DAC
Resolution
6
Differential Nonlinearity (Note 9)
Bits
0.5
LSB
TIMING
I2CEN
EN = HIGH to I2C Start
100
ms
SOFT−START
tSS
ROFF
Regulator Enable to Regulated VOUT
VOUT Pull−Down Resistance,
Disabled
RLOAD > 5 W; to VOUT = 1.2 V;
00, 01, 03, 04, 042, 05, 09, 13, 23 and 79
Options
300
2.5 V ≤ VIN ≤ 4.5 V; RLOAD = 2 W;
to VOUT = 1.127 V with 1.1 V Pre−Bias
Voltage; 08 and 18 Options
135
EN = 0 or VIN < VUVLO
160
mS
175
mS
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Monotonicity assured by design.
Table 11. I2C TIMING SPECIFICATIONS
Guaranteed by design.
Symbol
fSCL
tBUF
tHD;STA
Parameter
SCL Clock Frequency
Bus−Free Time between STOP and
START Conditions
START or REPEATED START
Hold Time
Condition
Min.
Typ.
Max.
Unit
Standard Mode
100
kHz
Fast Mode
400
Fast Mode Plus
1000
High−Speed Mode, CB ≤100 pF
3400
High−Speed Mode, CB ≤ 400 pF
1700
Standard Mode
4.7
Fast Mode
1.3
Fast Mode Plus
0.5
Standard Mode
4
ms
Fast Mode
600
ns
Fast Mode Plus
260
ns
High−Speed Mode
160
ns
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7
ms
FAN53555
Table 11. I2C TIMING SPECIFICATIONS (continued)
Guaranteed by design.
Symbol
tLOW
tHIGH
tSU;STA
tSU;DAT
tHD;DAT
tRCL
Parameter
SCL LOW Period
SCL HIGH Period
Repeated START Setup Time
Data Setup Time
Data Hold Time
SCL Rise Time
Condition
Max.
Unit
4.7
ms
Fast Mode
1.3
ms
Fast Mode Plus
0.5
ms
High−Speed Mode, CB ≤ 100 pF
160.0
ns
High−Speed Mode, CB ≤ 400 pF
320.0
ns
4
ms
Fast Mode
600
ns
Fast Mode Plus
260
ns
High−Speed Mode, CB ≤ 100 pF
60
ns
High−Speed Mode, CB ≤ 400 pF
120
ns
Standard Mode
4.7
ms
Fast Mode
600.0
ns
Fast Mode Plus
260.0
ns
High−Speed Mode
160.0
ns
Standard Mode
250
ns
Fast Mode
100
Fast Mode Plus
50
High−Speed Mode
10
Standard Mode
Standard Mode
0
3.45
ms
Fast Mode
0
900.00
ns
Fast Mode Plus
0
450.00
ns
High−Speed Mode, CB ≤ 100 pF
0
70.00
ns
High−Speed Mode, CB ≤ 400 pF
0
150.00
ns
ns
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 400 pF
SCL Fall Time
Typ.
Standard Mode
High−Speed Mode, CB ≤ 100 pF
tFCL
Min.
10
80
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
40
High−Speed Mode, CB ≤ 400 pF
20
80
10
80
tRCL1
Rise Time of SCL After a REPEATED
START Condition and After ACK Bit
High−Speed Mode, CB ≤ 100 pF
tRDA
SDA Rise Time
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 400 pF
20
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
8
ns
160
High−Speed Mode, CB ≤ 100 pF
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ns
ns
FAN53555
Table 11. I2C TIMING SPECIFICATIONS (continued)
Guaranteed by design.
Symbol
Parameter
tFDA
Condition
SDA Fall Time
tSU;STO
Stop Condition Setup Time
CB
Min.
Typ.
Max.
Unit
ns
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
Fast Mode Plus
20+0.1CB
120
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
4
ms
Fast Mode
600
ns
Fast Mode Plus
120
ns
High−Speed Mode
160
ns
Capacitive Load for SDA and SCL
400
pF
TIMING DIAGRAMS
ÒÒÒ
ÒÒÒ
ÒÒÒ
ÒÒÒ
ÒÒÒ
ÒÒÒ
ÒÒÒ
ÕÕÕ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÔÔ
ÖÖÖÖ
ÖÖÖÖ
tF
SDA
SCL
tSU;STA
tR
TSU;DAT
tHIGH
tLOW
tHD;STA
tHD;DAT
tBUF
tHD;STO
tHD;STA
REPEATED
START
START
ÓÓÌÌ
ÓÓ
ÌÌ
ÓÓÌÌ
ÓÓ
ÌÌ
ÓÓ
ÌÌ
ÓÓ
ÓÓÌÌ
ÌÌ
ŠŠ
ÑÑ
STOP
Figure 5. I2C Interface Timing for Fast Plus, Fast, and Slow Modes
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÜÜ
ÙÙÙ
ÙÙÙ
tFDA
SDAH
tSU;STA
SCLH
tRDA
tRCL1
REPEATED
START
tFCL
tRCL
tSU;STO
tHIGH
tLOW
tHD;STA
REPEATED
START
ÛÛÛÛŽŽŸŸŸ
ÛÛÛÛŽŽ
ŸŸŸ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
ÚÚ
tSU;DAT
tHD;DAT
note A
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High−Speed Mode
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9
STOP
START
FAN53555
TYPICAL CHARACTERISTICS
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C;
circuit and components according to Figure 1 and Table 1.
92%
92%
2.7 VIN
3.6 VIN
5.0 VIN
90%
90%
88%
EFFICENCY
EFFICENCY
88%
86%
84%
82%
86%
84%
82%
80%
80%
78%
78%
76%
0
1000
2000
3000
LOAD CURRENT (mA)
4000
5000
76%
−40°C
+25°C
+85°C
0
90%
90%
88%
88%
86%
86%
84%
84%
82%
82%
80%
78%
76%
74%
70%
0
1000
4000
76%
−40°C
+25°C
+85°C
5000
70%
0
Figure 9. Efficiency vs. Load Current and
Input Voltage, VOUT = 0.9 V
90%
75%
70%
2000
3000
LOAD CURRENT (mA)
4000
5000
90%
85%
EFFICENCY
EFFICENCY
80%
1000
Figure 10. Efficiency vs. Load Current and
Temperature, VIN = 5 V, VOUT = 1.2 V
2.7 VIN
3.6 VIN
5.0 VIN
85%
5000
78%
72%
2000
3000
LOAD CURRENT (mA)
4000
80%
74%
2.7 VIN
3.6 VIN
5.0 VIN
72%
2000
3000
LOAD CURRENT (mA)
Figure 8. Efficiency vs. Load Current and
Temperature
EFFICENCY
EFFICENCY
Figure 7. Efficiency vs. Load Current and
Input Voltage
1000
80%
75%
70%
3.6VIN, 1.2VOUT, L=MMD−04ABNR33M
65%
65%
60%
60%
3.6VIN, 1.2VOUT, L=VLC5020T−R47M
5.0VIN, 1.2VOUT, L=MMD−04ABNR33M
5.0VIN, 1.2VOUT, L=VLC5020T−R47M
5.0VIN, 0.9VOUT, L=MMD−04ABNR33M
0
1000
2000
3000
LOAD CURRENT (mA)
4000
5000
5.0VIN, 0.9VOUT, L=VLC5020T−R47M
0
1000
2000
3000
4000
5000
6000 7000
LOAD CURRENT (mA)
Figure 11. Efficiency vs. Load Current and
Input Voltage, VOUT = 0.6 V
Figure 12. Efficiency vs. Load Current, VIN =
3.6 V and 5 V, VOUT = 1.2 V and 0.9 V
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10
FAN53555
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
25
20
VOUT SHIFT (mV)
20
2.7 VIN
3.6 VIN
5.0 VIN
16
15
12
10
8
5
4
0
0
1000
2000
3000
LOAD CURRENT (mA)
4000
2.7 VIN
3.6 VIN
5.0 VIN
0
5000
0
1000
1,000
PFM Exit
PFM Enter
800
LOAD CURRENT (mA)
LAOD CURRENT (mA)
5000
1,000
PFM Exit
PFM Enter
600
400
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
5.0
800
600
400
200
5.5
2.5
Figure 15. PFM Entry / Exit Level vs. Input
Voltage, VOUT = 1.2 V
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
5.0
5.5
Figure 16. PFM Entry / Exit Level vs. Input
Voltage, VOUT = 0.9 V
25
3.6VIN, 1.2VOUT, PWM
5.0VIN, 1.2VOUT, Auto
20
5.0VIN, 1.2VOUT, PWM
5.0VIN, 0.9VOUT, Auto
15
10
5
SWITCHING FREQUENCY (kHz)
3,000
3.6VIN, 1.2VOUT, Auto
OUTPUT RIPPLE (mVpp)
4000
Figure 14. Output Regulation vs. Load Current
and Input Voltage, VOUT=0.9 V
Figure 13. Output Regulation vs. Load Current
and Input Voltage, VOUT = 1.2 V
200
2.5
2000
3000
LOAD CURRENT (mA)
2,500
2,000
1,500
1,000
3.6VIN, 1.2VOUT, Auto
500
3.6VIN, 0.9VOUT, Auto
5.0VIN, 1.2VOUT, Auto
5.0VIN, 0.9VOUT, Auto
0
0
1000
2000
3000
4000
5000
0
0
LOAD CURRENT (mA)
1000
2000
3000
LOAD CURRENT (mA)
Figure 17. Output Ripple vs. Load Current,
VIN = 5 V and 3.6 V, VOUT = 1.2 V and 0.9 V,
Auto and FPWM
4000
Figure 18. Frequency vs. Load Current,
VIN = 5 V and 3.6 V, VOUT = 1.2 V and 0.9 V,
Auto PWM
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11
5000
FAN53555
80
60
70
50
INPUT CURRENT (mA)
INPUT SUPPLY CURRENT (mA)
TYPICAL CHARACTERISTICS (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
60
50
40
−40°C
+25°C
+85°C
30
20
2.5
3.0
3.5
4.0
4.5
5.0
40
30
20
−40°C
+25°C
+85°C
10
0
2.5
5.5
3.0
3.5
INPUT SUPPLY VOLTAGE (V)
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
Figure 19. Quiescent Current vs. Input Voltage and
Temperature, Auto PWM
Figure 20. Quiescent Current vs. Input Voltage
and Temperature, FPWM
70
60
EN_BUCK=0, −40C
EN_BUCK=0, +25C
EN_BUCK=0, +85C
EN=0, +25C
60
40
PSSR (dB)
INPUT CURRENT (mA)
50
30
20
50
40
30
10
3.6VIN, 1.2VOUT, 2A Load
3.6VIN, 0.9VOUT, 2A Load
5.0VIN, 0.9VOUT, 18mA Load, PFM
0
2.5
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
5.0
20
5.5
10
100
1,000
10,000
100k
FREQUENCY (Hz)
Figure 21. Shutdown Current vs. Input Voltage
and Temperature
Figure 22. PSRR vs. Frequency
Figure 23. Line Transient, 3−4 VIN, 1.2 VOUT, 10 ms
Edge, 50 W Load
Figure 24. Line Transient, 3−4 VIN, 1.2 VOUT, 10 ms
Edge, 1 A Load
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12
FAN53555
TYPICAL CHARACTERISTICS (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
Figure 25. Load Transient, 5 VIN, 0.9 VOUT, 0.3−3 A,
100 ns Edge
Figure 26. Load Transient, 3.6 VIN, 1.2 VOUT, 0.3−3 A,
100 ns Edge
Figure 27. Load Transient, 3.6 VIN, 1.2 VOUT, 0.3−3 A,
100 ns Edge, COUT = 4x22 mF
Figure 28. Load Transient, 3.6 VIN, 1.2 VOUT, 1.5−6 A,
100 ns Edge, COUT = 4x22 mF
Figure 29. Input Over−Voltage Protection
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13
FAN53555
TYPICAL CHARACTERISTICS (Continued)
Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25°C; circuit and
components according to Figure 1 and Table 1.
Figure 30. Startup / Shutdown, No Load, VOUT = 0.9 V
Figure 31. Startup / Shutdown, 180 mW Load,
VOUT = 0.9 V
Figure 32. Overload Protection and Recovery
Figure 33. Startup into Faulted Load, VOUT = 0.9 V
OPERATION DESCRIPTION
• Reprogram the mode to enable or disable PFM;
• Control voltage transition slew rate; or
• Enable / disable the regulator.
The FAN53555 is a step−down switching voltage
regulator that delivers a programmable output voltage from
an input voltage supply of 2.5 V to 5.5 V. Using a proprietary
architecture with synchronous rectification, the FAN53555
is capable of delivering 5 A at over 80% efficiency. Pulse
currents as high as 6.5 A can be supported by the 05 option.
The regulator operates at a nominal frequency of 2.4 MHz
at full load, which reduces the value of the external
components to 330 nH for the output inductor and 22 mF for
the output capacitor. High efficiency is maintained at light
load with single−pulse PFM.
The FAN53555 integrates an I2C−compatible interface,
allowing transfers up to 3.4 Mbps. This communication
interface can be used to:
• Dynamically re−program the output voltage in 10 mV,
12.826 mV increments (option 04, 09, and 042),
12.5 mV increments (option 23), or 12.967 mV
increments (option 24);
Control Scheme
The FAN53555 uses a proprietary non−linear,
fixed−frequency PWM modulator to deliver a fast load
transient response, while maintaining a constant switching
frequency over a wide range of operating conditions. The
regulator performance is independent of the output
capacitor ESR, allowing for the use of ceramic output
capacitors. Although this type of operation normally results
in a switching frequency that varies with input voltage and
load current, an internal frequency loop holds the switching
frequency constant over a large range of input voltages and
load currents.
For very light loads, the FAN53555 operates in
Discontinuous Current Diode (DCM) single−pulse PFM,
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14
FAN53555
In the 01 and 05 options, BUCK_EN0 and BUCK_EN1
are initialized to 10. Using these options, VSEL must be
LOW after a POR if the IC is powering the processor used
to communicate through I2C. The 03 option has the VSEL
input to the modulator logic internally tied LOW.
which produces low output ripple compared with other PFM
architectures. Transition between PWM and PFM is
relatively seamless, providing a smooth transition between
DCM and CCM Modes.
PFM can be disabled by programming the MODE bit
HIGH in the VSEL registers.
Table 12. HARDWARE AND SOFTWARE ENABLE
Enable and Soft−Start
When the EN pin is LOW; the IC is shut down, all internal
circuits are off, and the part draws very little current. In this
state, I2C cannot be written to or read from. For all options
except the 04, 24, and 042 options, all register values are
kept while EN pin is LOW. For the 04, 24 042 and 79
options; registers are reset to default values when EN pin is
LOW. For all options, registers are reset to default values
during a Power On Reset (POR).
When the OUTPUT_DISCHARGE bit in the CONTROL
register is enabled (logic HIGH) and the EN pin is LOW or
the BUCK_ENx bit is LOW, a load is connected from
VOUT to GND to discharge the output capacitors.
Raising EN while the BUCK_ENx bit is HIGH activates
the part and begins the soft−start cycle. During soft−start, the
modulator’s internal reference is ramped slowly to minimize
surge currents on the input and prevent overshoot of the
output voltage. Synchronous rectification is inhibited
during soft−start, allowing the IC to start into a pre−charged
capacitive load.
If large output capacitance values are used, the regulator
may fail to start. Maximum COUT capacitance for
successfully starting with a heavy constant−current load is
approximately:
C OUTMAX + ǒI LIMPK * I LOADǓ @
320m
V OUT
Pins
BITS
EN
VSEL
BUCK_EN0
BUCK_EN1
Output
0
X
X
X
OFF
1
0
0
X
OFF
1
0
1
X
ON
1
1
X
0
OFF
1
1
X
1
ON
VSEL Pin and I2C Programming Output Voltage
The output voltage is set by the NSELx control bits in
VSEL0 and VSEL1 registers. The output voltage for options
00, 01, 03, 05, 08, 18 and 79 is given as:
V OUT + 0.60 V ) NSELx @ 10 mV
(eq. 2)
For example, when NSEL = 011111 (31 decimal), then
VOUT = 0.60 + 0.310 = 0.91 V.
For the 04, 042, and 09 options; the output voltage is given
as:
V OUT + 0.603 ) NSELx @ 12.826 mV
(eq. 3)
For the 13 option, the output voltage is given as:
V OUT + 0.80 ) NSELx @ 10 mV
(eq. 1)
(eq. 4)
For the 23 option, the output voltage is given as:
V OUT + 0.60 V ) NSELx @ 12.5 mV
where COUTMAX is expressed in μF and ILOAD is the load
current during soft−start, expressed in A.
If the regulator is at its current limit for 16 consecutive
current limit cycles, the regulator shuts down and enters
3−state before reattempting soft−start 1700 ms later. This
limits the duty cycle of full output current during soft−start
to prevent excessive heating.
The IC allows for software enable of the regulator, when
EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and
BUCK_EN1 are both initialized HIGH in the 00, 04, 08, 09,
23, 24, 42 and 79 options. These options start after a POR
regardless of the state of the VSEL pin.
(eq. 5)
For the 24 option, the output voltage is given as:
V OUT + 0.603 V ) NSELx
12.967 mV (eq. 6)
Output voltage can also be controlled by toggling the
VSEL pin LOW or HIGH. VSEL LOW corresponds to
VSEL0 and VSEL HIGH corresponds to VSEL1. Upon
POR, VSEL0 and VSEL1 are reset to their default voltages,
shown in Table 9.
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15
FAN53555
Transition Slew Rate Limiting
currents from causing damage. Sixteen consecutive current
limit cycles in current limit cause the regulator to shut down
and stay off for about 1700 μs before attempting a restart.
When transitioning from a low to high voltage, the IC can
be programmed for one of eight possible slew rates using the
SLEW bits in the CONTROL register.
Thermal Shutdown
When the die temperature increases, due to a high load
condition and/or high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 17°C
hysteresis.
Table 13. TRANSITION SLEW RATE
Decimal
Bin
Slew Rate
0
000
64.00
mV / ms
1
001
32.00
mV / ms
2
010
16.00
mV / ms
3
011
8.00
mV / ms
4
100
4.00
mV / ms
5
101
2.00
mV / ms
6
110
1.00
mV / ms
7
111
0.50
mV / ms
Monitor Register (Reg05)
The Monitor register indicates of the regulation state of
the IC. If the IC is enabled and is regulating, its value is
(1000 0000).
I2C Interface
The FAN53555’s serial interface is compatible with
Standard, Fast, Fast Plus, and HS Mode I2C−Bus
specifications. The FAN53555’s SCL line is an input and its
SDA line is a bi−directional open−drain output; it can only
pull down the bus when active. The SDA line only pulls
LOW during data reads and when signaling ACK. All data
is shifted in MSB (bit 7) first.
Transitions from high to low voltage rely on the output
load to discharge VOUT to the new set point. Once the
high−to−low transition begins, the IC stops switching until
VOUT has reached the new set point.
For options 04, 042, 09, 23, and 24 where the Dynamic
Voltage Scaling (DVS) step is not 10 mV; the actual slew
rate is the corresponding number shown in Table 6 scaled by
the ratio of the DVS step to 10 mV. For example, the slew
rate of option 13 for Bin=011 is 8.00 mV / ms x 12.5 mV /
10 mV = 10.00 mV / ms.
I2C Slave Address
In hex notation, the slave address assumes a 0 LS Bit. The
hex slave address is C0 for all options except −42, which has
a hex slave address of C4.
Under−Voltage Lockout
Table 14. I2C SLAVE ADDRESS
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises
HIGH enough to properly operate. This ensures proper
operation of the regulator during startup or shutdown.
Bits
Input Over−Voltage Protection (OVP)
Option
Hex
7
6
5
4
3
2
1
0
00 to 24,
79
C0
1
1
0
0
0
0
0
R/ W
42
C4
1
1
0
0
0
1
0
R/ W
When VIN exceeds VSDWN (about 6.2 V) the IC stops
switching to protect the circuitry from internal spikes above
6.5 V. An internal filter prevents the circuit from shutting
down due to noise spikes.
Other slave addresses can be assigned. Contact a onsemi
representative.
Power Good (03 & 79 Option)
Bus Timing
As shown in Figure 34, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
The PGOOD pin is an open−drain output indicating that
the regulator is enabled when its state is HIGH. PGOOD
pulls LOW under the following conditions:
• Regulator is disabled (EN pin LOW, disabled by I2C,
fault time−out, UVLO, OVP, over−temperature);
• Regulator is performing a soft−start.
Data change allowed
PGOOD remains HIGH during I2C initiated VOUT
transitions.
SDA
tH
Current Limiting
SCL
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
tSU
Figure 34. Data Transfer Timing
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16
FAN53555
High−Speed (HS) Mode
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 35.
tHD;STA
SDA
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical, except the bus
speed for HS mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a START condition. The master code is sent in Fast or
Fast−Plus Mode (less than 1 MHz clock); slaves do not ACK
this transmission.
The master generates a REPEATED START condition ()
that causes all slaves on the bus to switch to HS Mode. The
master then sends I2C packets, as described above, using the
HS Mode clock rate and timing.
The bus remains in HS Mode until a STOP bit (Figure 36)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 37).
Slave Address
MS Bit
SCL
Figure 35. START Bit
A transaction ends with a STOP condition, which is
defined as SDA transitioning from 0 to 1 with SCL HIGH,
as shown in Figure 36.
Slave Releases
Master Drives
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
packet, defined as Master Drives Bus and Slave Drives Buss.
All addresses and data are MSB first.
tHD;STO
ACK(0) or
NACK(1)
SDA
SCL
Table 15. I2C BIT DEFINITIONS FOR FIGURE 38 AND
FIGURE 39
Figure 36. STOP Bit
Symbol
During a read from the FAN53555, the master issues a
REPEATED START after sending the register address, and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 37.
Slave Releases
tSU;STA
SLADDR
MS Bit
SCL
Figure 37. REPEATED START Timing
7 bits
S
R
REPEATED START, see Figure 37
P
STOP, see Figure 36
S
START, see Figure 35
A
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
R
Repeated START, see Figure 37.
P
STOP, see Figure 36.
tHD;STA
ACK(0) or
NACK(1)
SDA
Slave Address
0
Definition
0
8 bits
0
8 bits
0
A
Reg Addr
A
Data
A
P
Figure 38. Write Transaction
7 bits
S
Slave Address
0
0
8 bits
0
A
Reg Addr
A
7 bits
R
Slave Address
Figure 39. Read Transaction
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17
1
0
8 bits
1
A
Data
A
P
FAN53555
REGISTER DESCRIPTION
Table 16. REGISTER MAP
POR Default
Hex
Address
Name
00
VSEL0
01
02
03
VSEL1
CONTROL
ID1
04
ID2
05
MONITOR
Option
VOUT
Binary
Hex
00
1.050
10101101
AD
08, 18
1.020
10101010
AA
01, 03, 05
0.900
10011110
9E
04
1.100
10100111
A7
24
1.225
10110000
B0
13
1.150
10100011
A3
23
1.150
10101100
AC
09
1.100
10100111
A7
79
0.85
10011001
99
00
1.200
11111100
FC
01, 05
1.000
01101000
68
04
1.200
11101111
EF
24
1.212
10101111
AF
08, 18
1.150
10110111
B7
13
1.150
10100011
A3
23
1.150
10101100
AC
09
1.100
11100111
E7
00, 01, 03, 04,
05, 24
10000000
80
08, 09, 18
00000000
00
13, 23
10110000
B0
00, 13, 23, 24
10000000
80
01
10000001
81
79
10000010
82
03
10000011
83
04
10000100
84
05
10000101
85
08, 18
10001000
88
09
10001100
8C
Read−only register identifies die revision
All
0000XXXX
0X
Indicates device status
All
X0000000
X0
Function
Controls VOUT settings when VSEL pin = 0
Controls VOUT settings when VSEL pin = 1
Determines whether VOUT output discharge is enabled and also the slew rate of positive transitions
Read−only register identifies vendor and chip type
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18
FAN53555
Table 17. BIT DEFINITIONS
The following table defines the operation of each register bit. Bold indicates power−on default values.
Bit
VSEL0
Name
R/W
Value
Description
Register Address: 00
7
BUCK_EN0
1
Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is
HIGH, BUCK_EN bit takes precedent.
6
MODE0
0
Allow Auto−PFM Mode during light load.
1
Forced PWM Mode.
5:0
NSEL0
00 Option
101101
Sets VOUT value from 0.6 to 1.23 V in 10 mV steps (see Eq. (2)).
08, 18 Options
101010
01, 03, 05 Options
011110
79 Option 011001
04 Option
100111
Sets VOUT value from 0.603 to 1.411 V in 12.826 mV steps (see Eq. (3)).
09 Option
100111
VSEL1
7
R/W
13 Option
100011
Sets VOUT value from 0.8 to 1.43 V in 10 mV steps (see Eq. (4)).
23 Option
101100
Sets VOUT value from 0.6 to 1.3875 V in 12.5 mV steps (see Eq. (5)).
24 Option
110000
Sets VOUT value from 0.603 to 1.42 V in 12.967 mV steps (see Eq. (6)).
Register Address: 01
BUCK_EN1
00, 04, 08, 09,13,
18, 23, 24 Options
1
Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is
HIGH, BUCK_EN bit takes precedent.
01, 05 Options
0
6
MODE1
08, 13, 18, 23, 24
Options
0
Allow AUTO−PFM Mode during light load.
00, 01, 04, 05, 09
Options
1
Forced PWM Mode.
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19
FAN53555
Table 17. BIT DEFINITIONS (continued)
The following table defines the operation of each register bit. Bold indicates power−on default values.
Bit
Name
VSEL1
R/W
5:0
Value
Description
Register Address: 01
NSEL1
00 Option
111100
Sets VOUT value from 0.6 to 1.23 V in 10 mV steps (see Eq. (2)).
01, 05 Options
101000
08, 18 Options
110111
04 Option
101111
Sets VOUT value from 0.603 to 1.411 V in 12.826 mV steps (see Eq. (3)).
09 Option
100111
CONTROL
7
R/W
OUTPUT_DISCHARGE
6:4
SLEW
13 Option
100011
Sets VOUT value from 0.8 to 1.43 V in 10 mV steps (see Eq. (4)).
23 Option
010100
Sets VOUT value from 0.6 to 1.3875 V in 12.5 mV steps (see Eq. (5)).
24 Option
101111
Sets VOUT value from 0.603 to 1.42 V in 12.967 mV steps (see Eq. (6)).
Register Address: 02
08, 09, 18, 79
Options
0
When the regulator is disabled, VOUT is not discharged.
00, 01, 03, 04,
05,13, 23, 24
Options
1
When the regulator is disabled, VOUT discharges through an internal pull−down.
000 –111
011
Sets the slew rate for positive voltage transitions (see Table 6).
Default value for 13 and 23 options
3
Reserved
0
Always reads back 0
2
04, 09, 24, 79 Options
RESET
0
Setting to 1 resets all registers to default values.
All other options
Reserved
0
Always reads back 0
Reserved
00
Always reads back 00
1:0
ID1
R
Register Address: 03
7:5
VENDOR
100
4
Reserved
0
Signifies onsemi as the IC vendor
Always reads back 0
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FAN53555
Table 17. BIT DEFINITIONS (continued)
The following table defines the operation of each register bit. Bold indicates power−on default values.
Bit
ID1
Name
R
3:0
ID2
Value
Register Address: 03
DIE_ID
R
Description
0000
IC Type = 00 Option (FAN53555UC00X / FAN53555BUC24X)
0001
IC Type = 01 Option (FAN53555UC01X)
0010
IC Type = 79 Option (FAN53555BUC79X)
0011
IC Type = 03 Option (FAN53555UC03X)
0100
IC Type = 04 Option (FAN53555UC04X)
0100
IC Type = 042 Option (FAN53555UC042X)
0101
IC Type = 05 Option (FAN53555UC05X / FAN53555BUC05X)
1000
IC Type = 08, 18 Options (FAN53555UC08X / FAN53555BUC08X,
FAN53555UC18X / FAN53555BUC18X)
1100
IC Type = 09 Option (FAN53555UC09X / FAN53555BUC09X)
0000
IC Type = 13 Option (FAN53555UC13X / FAN53555BUC13X)
0000
IC Type = 23 Option (FAN53555BUC23X)
Register Address: 04
7:4
Reserved
0000
3:0
DIE_REV
00 Option
0011
Always reads back 0000
IC mask revision
01 Option
0011
03 Option
0011
04 Option
1111
24−Option
0100
042 Option
1111
05 Option
0011
08, 18 Options
0001
BUC08, BUC18
Options
1111
09 Option
1111
13 Option
1111
23 Option
1100
79 Option 1000
MONITOR
R
Register Address: 05
7
PGOOD
0
6:0
Not used
000 0000
1: buck is enabled and soft−start is completed
Always reads back 000 0000
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FAN53555
APPLICATION INFORMATION
Selecting the Inductor
Output Capacitor and VOUT Ripple
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects the average current
limit, the output voltage ripple, and the efficiency.
The ripple current (DI) of the regulator is:
DI +
V OUT
V IN
@
ǒ
Ǔ
V IN * V OUT
L @ f sw
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in−circuit capacitance than the
0805 package, which can degrade transient response and
output ripple.
Increasing COUT has negligible effect on loop stability
and can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, DVOUT,
is calculated by:
(eq. 7)
The maximum average load current, IMAX(LOAD), is
related to the peak current limit, ILIM(PK), by the ripple
current such that:
DI
I MAX(LOAD) + I LIM(PK) *
2
ƪ
DV OUT + DI L
(eq. 8)
ǸI
OUT(DC)
2 ) DI
2
12
(eq. 9)
The increased RMS current produces higher losses
through the RDS(ON) of the IC MOSFETs as well as the
inductor ESR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current.
DVOUT (Eq.(11))
Transient Response
Increase
Decrease
Degraded
)
ƫ
1
8 @ f SW @ C OUT
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the
square−wave component of output ripple that results from
the division ratio COUT ESL and the output inductor (LOUT).
The square−wave component due to the ESL can be
estimated as:
DVOUT(SQ) [ V IN @
Table 18. EFFECTS OF INDUCTOR VALUE
(FROM 330 nH RECOMMENDED) ON REGULATOR
PERFORMANCE
IMAX(LOAD)
2 @ D @ ( 1 * D)
2
where COUT is the effective output capacitance.
The capacitance of COUT decreases at higher output
voltages, which results in higher DVOUT. Equation (10) is
only valid for Continuous Current Mode (CCM) operation,
which occurs when the regulator is in PWM Mode.
For large COUT values, the regulator may fail to start under
a load. If an inductor value greater than 1.0 mH is used, at
least 30 mF of COUT should be used to ensure stability.
The lowest DVOUT is obtained when the IC is in PWM
Mode and, therefore, operating at 2.4 MHz. In PFM Mode,
fSW is reduced, causing DVOUT to increase.
The FAN53555 is optimized for operation with
L = 330 nH, but is stable with inductances up to 1.0 μH
(nominal). The inductor should be rated to maintain at least
80% of its value at ILIM(PK). Failure to do so lowers the
amount of DC current the IC can deliver.
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but since DI increases, the
RMS current increases, as do core and skin−effect losses.
I RMS +
(eq. 10)
f SW @ C OUT @ ESR
ESL COUT
L1
(eq. 11)
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired COUT value. For
example, to obtain COUT = 20 mF, a single 22 mF 0805
would produce twice the square wave ripple as two x 10 mF
0805.
To minimize ESL, try to use capacitors with the lowest
ratio of length to width. 0805s have lower ESL than 1206s.
If low output ripple is a chief concern, some vendors
produce 0508 or 0612 capacitors with ultra−low ESL.
Placing additional small−value capacitors near the load also
reduces the high−frequency ripple components.
Inductor Current Rating
The current limit circuit can allow substantial peak
currents to flow through L1 under worst−case conditions. If
it is possible for the load to draw such currents, the inductor
should be capable of sustaining the current or failing in a safe
manner.
For space−constrained applications, a lower current rating
for L1 can be used. The FAN53555 may still protect these
inductors in the event of a short circuit, but may not be able
to protect the inductor from failure if the load is able to draw
higher currents than the DC rating of the inductor.
Input Capacitor
The ceramic input capacitors should be placed as close as
possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or
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22
FAN53555
tantalum) should be placed between CIN and the power
source lead to reduce under−damped ringing that can occur
between the inductance of the power source leads and CIN.
The effective CIN capacitance value decreases as VIN
increases due to DC bias effects. This has no significant
impact on regulator performance.
2. Calculate total power dissipation using:
P T + V OUT
ǒ1h * 1Ǔ
I LOAD
(eq. 12)
where h is efficiency from Figure 7 through Figure
12.
3. Estimate inductor copper losses using:
Thermal Considerations
P L + I LOAD
Heat is removed from the IC through the solder bumps to
the PCB copper. The junction−to−ambient thermal
resistance (θJA) is largely a function of the PCB layout (size,
copper weight, and trace width) and the temperature rise
from junction to ambient (ΔT).
For the FAN53555UC, θJA is 38°C/W when mounted on
its four−layer evaluation board in still air with two−ounce
outer layer copper weight and one−ounce inner layers.
Halving the copper thickness results in an increased θJA of
48°C/W.
For long−term reliable operation, the IC’s junction
temperature (TJ) should be maintained below 125°C.
To calculate maximum operating temperature (
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