USB-Compliant Single-Cell
Li-Ion Switching Charger
with USB-OTG Boost for
200 mA to 1.45 A Systems
FAN54005
Description
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The FAN54005 is a highly integrated switch−mode
charger, configurable for 200 mA to 1.45 A systems using
a single external resistor.
The charging parameters and operating modes are program−
mable through an I2C Interface that operates up to 3.4 Mbps.
The charger and boost regulator circuits switch at 3 MHz
to minimize the size of external passive components.
The FAN54005 provides battery charging in three phases:
conditioning, constant current and constant voltage.
To ensure USB compliance and minimize charging time, the
input current limit can be changed through the I2C interface
by the host processor. Charge termination is determined by
a programmable minimum current level. A safety timer with
reset control provides a safety backup for the I2C host.
Charge status is reported to the host through the I2C port.
The integrated circuit (IC) automatically restarts the charge
cycle when the battery falls below an internal threshold. If
the input source is removed, the IC enters a high−impedance
mode, preventing leakage from the battery to the input.
Charge current is reduced when the die temperature reaches
120°C, protecting the device and PCB from damage.
The FAN54005 can operate as a boost regulator on
command from the system. The boost regulator includes a
soft−start that limits inrush current from the battery and uses
the same external components used for charging the battery.
1
WLCSP
20 BALL
CASE 567SL
• Charge Parameters Programmable through High−Speed
•
•
•
•
•
Features
• Fully Integrated, High−Efficiency Charger for
•
•
•
•
•
•
•
•
•
Single−Cell Li−Ion and Li−Polymer Battery Packs
Charge Voltage Accuracy: ±0.5% at 25°C
Charge Voltage Accuracy: ±1% from 0 to 125°C
Supports 200 mA to 1.45 A Systems
95% Efficiency for 200 mA−Hour Batteries
94% Efficiency for 500 mA−Hour Batteries
90% Efficiency for 1.0 A−Hour Batteries
±5% Input Current Regulation Accuracy
±5% Charge Current Regulation Accuracy
20 V Absolute Maximum Input Voltage
6 V Maximum Input Operating Voltage
I2C Interface (3.4 Mb/s) with Fast Mode Plus
Compatibility
♦ Input Current
♦ Fast−Charge / Termination Current
♦ Charger Voltage
♦ Termination Enable
3 MHz Synchronous Buck PWM Controller with Wide
Duty Cycle Range
Small Footprint 1 mH External Inductor
Safety Timer with Reset Control
1.8 V Regulated Output from VBUS for Auxiliary Circuits
Dynamic Input Voltage Control Automatically Reduces
Charging Current with Weak Input Sources
Low Reverse Leakage to Prevent Battery Drain to VBUS
5 V, 500 mA Boost Mode for USB OTG for 3.0 V to
4.5 V Battery Input
Available in a 1.96 x 1.87 mm, 20−bump, 0.4 mm Pitch
WLCSP Package
Applications
•
•
•
•
•
Wireless Speakers, Headphones
Cell Phones, Gaming Devices
Toys, Drones, Digital Cameras
IoT Devices
E−Cigs, Vapes
ORDERING INFORMATION
Part Number
Temperature Range
Package
PN Bits: IC_INFO[4:2]
Packing†
FAN54005UCX
−40°C to +85°C
20−Bump, Wafer−Level Chip−Scale Package
(WLCSP), 0.4 mm Pitch, 1.96 x 1.87 mm
101
Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
November, 2019 − Rev. 4
1
Publication Order Number:
FAN54005/D
FAN54005
L1
SW
VBUS
1mH
CBUS
COUT
1mF
0.1mF
PMID
CMID
CSIN
4.7mF
SDA
FAN54005
RSNS
SCL
VBAT
DISABLE
CBAT
VREG
OTG/USB#
+ Battery
SYSTEM
LOAD
C REG 10 mF
STAT
1mF
Figure 1. Typical Application
Block Diagram
VREG
1.8V / PMID REG
C REG
PMID
1mF
PMID
Q1
Q3
CHARGE
PUMP
C BUS
1mF
VBUS
OVP
Q1A
Q1B
ON
OFF
< VBAT
OFF
ON
C MID
Q1A
VBUS
PMID
> VBAT
4.7mF
Q1B
I_IN
CONTROL
L1
SW
PWM
MODULATOR
Q2
1mH
PGND
DAC
SDA
CSIN
VREF
SCL
DISABLE
RSNS
STAT
30 mA
CSYS_DISTRIBUTED
+
C BAT
PMID
I2C
INTERFACE
C OUT
0.1mF
Battery
10 mF
OSC
SYSTEM
LOAD
LOGIC
AND
CONTROL
OTG
47mF
Figure 2. IC and System Block Diagram
Table 1. RECOMMENDED EXTERNAL COMPONENTS
Component
Description
Vendor
Parameter
Typ
Unit
L1
1 mH ±20%, 4.0 A, 33 mW, 2016
Semco CIGT201610EH1R0M
L
1.0
mH
CBAT
10 mF, 20%, 6.3 V, X5R, 0603
Murata: GRM188R60J106M
TDK: C1608X5R0J106M
C
10
mF
CMID
4.7 mF, 10%, 10 V, X5R, 0603
Murata: GRM188R61A475K
TDK: C1608X5R1A475K
C (Note 1)
4.7
mF
CBUS
1.0 mF, 10%, 25 V, X5R, 0603
Murata: GRM188R61E105K
TDK: C1608X5R1E105M
C
1.0
mF
CREG
1.0 mF, 10%, 10 V, X5R, 0402
Murata: GRM155R61A105K
TDK: C1005X5R1A105K
C
1.0
mF
COUT
0.1 mF, 10%, 16 V, X7R, 0402
Murata: GRM155R71C104K
TDK: C1005X7R1C104K
C
0.1
mF
CSYS_DISTRIBUTED (Note 2)
n/a
n/a
C
47
mF
1. A 10 V rating is sufficient for CMID because PMID is protected from over−voltage surges on VBUS by Q3 (Figure 2).
2. A minimum 47 mF of distributed capacitance on SYS is required for proper operation of the FAN54005.
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2
FAN54005
Pin Configuration
A1
A2
A3
A4
A4
A3
A2
A1
B1
B2
B3
B4
B4
B3
B2
B1
C1
C2
C3
C4
C4
C3
C2
C1
D1
D2
D3
D4
D4
D3
D2
D1
E1
E2
E3
E4
E4
E3
E2
E1
Top View
Bottom View
Figure 3. WLCSP−20 Pin Assignments
Table 2. PIN DEFINITIONS
Pin #
Name
Description
A1, A2
VBUS
A3
NC
No Connect. No external connection is made between this pin and the IC’s internal circuitry.
A4
SCL
I2C Interface Serial Clock. This pin should not be left floating.
B1−B3
PMID
Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and
high−voltage input switch. Bypass with a minimum of 4.7 mF, 6.3 V capacitor to PGND.
B4
SDA
I2C Interface Serial Data. This pin should not be left floating.
C1−C3
SW
Switching Node. Connect to output inductor.
C4
STAT
Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charging.
D1−D3
PGND
Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom
of CMID should be as short as possible.
D4
OTG
On−The−Go. On VBUS Power−On Reset (POR), this pin sets the input current limit for t15MIN charging. Also,
the OTG pin enables the boost regulator in conjunction with OTG_EN and OTG_PL bits (See Table 21)
E1
CSIN
Current−Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to
sense current into the battery. Bypass this pin close to RSNS with a 0.1 mF capacitor to PGND.
E2
DISABLE
E3
VREG
Regulator Output. Connect to a 1 mF capacitor to PGND. This pin provides regulated 1.8 V and can supply
up to 2 mA of DC load current.
E4
VBAT
Battery Voltage. Connect to the positive (+) terminal of the battery pack and close to RSNS.
Charger Input Voltage and USB−OTG output voltage. Bypass with a 1 mF capacitor to PGND.
Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the I2C registers. When this pin is HIGH, the 15−minute timer is reset. This pin does not affect the 32−second timer.
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3
FAN54005
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
VBUS
VBUS Voltage
VSTAT
STAT Voltage
VI
PMID Voltage
Parameter
Min
Max
Unit
Continuous
−0.7
20.0
V
Pulsed, 100 ms Maximum Non−Repetitive
−1.0
16.0
V
7.0
V
−0.3
SW, CSIN, VBAT, DISABLE Voltage
VO
Voltage on Other Pins
−0.3 (Note 3)
7.0
−0.3
6.5 (Note 4)
V
dVBUS / dt
Maximum VBUS Slope above 5.5 V when Boost or Charger are Active
4
V/ms
−dVBUS / dt
Negative VBUS Slew Rate during VBUS Short Circuit,
CMID ≤ 4.7 mF (See VBUS Short While Charging)
TA ≤ 60°C
4
V/ms
TA ≥ 60°C
2
Electrostatic Discharge Protection Level
Human Body Model
per JESD22−A114
2000
Charged Device Model
per JESD22−C101
1000
ESD
V
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. SW only: Switching transients of −0.7 V, minimum, with duration VIN(MIN)1, PWM Switching
10
mA
VBUS > VIN(MIN)1; PWM Enabled,
Not Switching (Battery OVP Condition);
I_IN Setting = 100 mA
2.5
mA
0°C < TJ < 85°C, HZ_MODE = 1, 32S Mode
63
90
mA
0.2
5.0
mA
mA
ILKG
VBAT to VBUS Leakage Current
0°C < TJ < 85°C, HZ_MODE = 1,
VBAT = 4.2 V, VBUS = 0 V
IBAT
Battery Discharge Current in High−
Impedance Mode
0°C < TJ < 85°C, HZ_MODE = 1,
VBAT = 4.2 V
10
DISABLE = 1, 0°C < TJ < 85°C,
VBAT = 4.2 V
10
CHARGER VOLTAGE REGULATION
VOREG
Charge Voltage Range
V
3.5
4.4
−0.5%
+0.5%
TJ = 0 to 125°C
−1%
+1%
Output Charge Current Range
VSHORT < VBAT < VOREG,
68 < RSNS < 180 mW
200
1450
mA
Charge Current Accuracy Across
RSNS
20 mV ≤ [VCSIN – VBAT ] ≤ 40 mV
92
97
102
%
[VCSIN – VBAT ] > 40 mV
94
97
100
%
Charge Voltage Accuracy
TA = 25°C
CHARGING CURRENT REGULATION
IOCHARGE
WEAK BATTERY DETECTION
VLOWV
Weak Battery Threshold Range
3.4
3.7
V
Weak Battery Threshold Accuracy
−5
+5
%
Weak Battery Deglitch Time
Rising Voltage
30
ms
LOGIC LEVELS: DISABLE, SDA, SCL, OTG
VIH
High−Level Input Voltage
VIL
Low−Level Input Voltage
IIN
Input Bias Current
1.05
Input Tied to GND or VBUS
V
0.01
0.4
V
1.00
mA
CHARGE TERMINATION DETECTION
ITERM
Termination Current Range
VBAT > VOREG – VRCH,
68 < RSNS < 180 mW
20
400
mA
Termination Current Accuracy
[VCSIN – VBAT ] from 3 mV to 20 mV
−25
+25
%
[VCSIN – VBAT ] from 20 mV to 40 mV
−5
+5
Termination Current Deglitch Time
30
ms
1.8 V LINEAR REGULATOR
VREG
1.8 V Regulator Output
IREG from 0 to 2 mA
1.7
1.8
1.9
V
INPUT POWER SOURCE DETECTION
VIN(MIN)1
VBUS Input Voltage Rising
To Initiate and Pass VBUS Validation
4.29
4.42
V
VIN(MIN)2
Minimum VBUS During Charge
During Charging
3.71
3.94
V
tVBUS_VALID VBUS Validation Time
30
ms
DYNAMIC INPUT VOLTAGE CONTROL (VBUS)
VSP
DIVC Accuracy
−3
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5
+3
%
FAN54005
Table 6. ELECTRICAL SPECIFICATIONS
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IINLIM Set to 100 mA
88
93
98
mA
IINLIM Set to 500 mA
450
475
500
Recharge Threshold
Below VOREG
100
120
150
Deglitch Time
VBAT Falling Below VRCH Threshold
INPUT CURRENT LIMIT
IINLIM
Input Current Limit Threshold
BATTERY RECHARGE THRESHOLD
VRCH
130
mV
ms
STAT OUTPUT
VSTAT(OL)
STAT Output Low
ISTAT = 10 mA
ISTAT(OH)
STAT High Leakage Current
VSTAT = 5 V
0.4
V
1
mA
BATTERY DETECTION
IDETECT
Battery Detection Current before
Charge Done (Sink Current) (Note 5)
tDETECT
Battery Detection Time
Begins after Termination Detected and
VBAT ≤ VOREG –VRCH
−0.80
mA
262
ms
SLEEP COMPARATOR
VSLP
Sleep−Mode Entry Threshold,
VBUS – VBAT
2.3 V ≤ VBAT ≤ VOREG, VBUS Falling
0
0.04
0.10
tSLP_EXIT
Deglitch Time for VBUS Rising
Above VBAT by VSLP
Rising Voltage
30
IINLIM = 500 mA
180
250
Q1 On Resistance (PMID to SW)
130
225
Q2 On Resistance (SW to GND)
150
225
V
ms
POWER SWITCHES (See Figure 2)
RDS(ON)
Q3 On Resistance (VBUS to PMID)
mW
CHARGER PWM MODULATOR
fSW
Oscillator Frequency
DMAX
Maximum Duty Cycle
DMIN
Minimum Duty Cycle
ISYNC
Synchronous to Non−Synchronous
Current Cut−Off Threshold (Note 6)
2.7
Low−Side MOSFET (Q2) Cycle−by−Cycle
Current Limit
3.0
3.3
MHz
100
%
0
%
140
mA
BOOST MODE OPERATION (OPA_MODE = 1, HZ_MODE = 0)
VBOOST
Boost Output Voltage at VBUS
IBAT(BOOST) Boost Mode Quiescent Current
ILIMPK(BST)
Q2 Peak Current Limit
UVLOBST
Minimum Battery Voltage for Boost
Operation
V
2.5 V < VBAT < 4.5 V, ILOAD from 0 to 200 mA
4.80
5.07
5.17
3.0 V < VBAT < 4.5 V, ILOAD from 0 to 500 mA
4.77
5.07
5.17
140
300
mA
1700
1960
mA
PFM Mode, VBAT = 3.6 V, IOUT = 0
1440
V
While Boost Active
2.30
To Start Boost Regulator
2.50
Normal Operation
1500
kW
Charger Validation
100
W
2.70
VBUS LOAD RESISTANCE
RVBUS
VBUS to PGND Resistance
PROTECTION AND TIMERS
VBUSOVP
VBUS Over−Voltage Shutdown
VBUS Rising
Hysteresis
VBUS Falling
6.09
6.29
100
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6
6.49
V
mV
FAN54005
Table 6. ELECTRICAL SPECIFICATIONS
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PROTECTION AND TIMERS
ILIMPK(CHG) Q1 Cycle−by−Cycle Peak Current
Limit
VSHORT
Charge Mode
2.3
Battery Short−Circuit Threshold
VBAT Rising
Hysteresis
VBAT Falling
Linear Charging Current
VBAT < VSHORT
Thermal Shutdown Threshold
(Note 7)
TJ Rising
145
Hysteresis (Note 7)
TJ Falling
10
TCF
Thermal Regulation Threshold
(Note 7)
Charge Current Reduction Begins
120
tINT
Detection Interval
t32S
32−Second Timer (Note 8)
ISHORT
TSHUTDWN
t15MIN
DtLF
1.95
2.00
A
2.05
100
20
30
V
mV
40
mA
°C
°C
2.1
s
s
Charger Enabled
20.5
25.2
28.0
Charger Disabled
18.0
25.2
34.0
15−Minute Timer
15−Minute Mode
12.0
13.5
15.0
min
Low−Frequency Timer Accuracy
Charger Inactive
−25
25
%
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Negative current is current flowing from the battery to GND (discharging the battery).
6. Q2 always turns on for 60 ns, then turns off if current is below ISYNC.
7. Guaranteed by design; not tested in production.
8. This tolerance (%) applies to all timers on the IC, including soft−start and deglitching timers.
Table 7. I2C TIMING SPECIFICATIONS Guaranteed by design, VBAT ≥ 2.5 V if valid VBUS not present.
Symbol
fSCL
Parameter
SCL Clock Frequency
Conditions
Min
Typ
Max
Unit
Standard Mode
100
kHz
Fast Mode
400
High−Speed Mode, CB ≤ 100 pF
3400
High−Speed Mode, CB ≤ 400 pF
tBUF
tHD;STA
tLOW
tHIGH
tSU;STA
1700
Bus−Free Time between STOP and
START Conditions
Standard Mode
4.7
Fast Mode
1.3
START or Repeated START Hold
Time
Standard Mode
SCL LOW Period
SCL HIGH Period
Repeated START Setup Time
ms
4
ms
Fast Mode
600
ns
High−Speed Mode
160
ns
Standard Mode
4.7
ms
Fast Mode
1.3
ms
High−Speed Mode, CB ≤ 100 pF
160
ns
High−Speed Mode, CB ≤ 400 pF
320
ns
4
ms
Fast Mode
600
ns
High−Speed Mode, CB ≤ 100 pF
60
ns
High−Speed Mode, CB ≤ 400 pF
120
ns
Standard Mode
4.7
ms
Fast Mode
600
ns
High−Speed Mode
160
ns
Standard Mode
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FAN54005
Table 7. I2C TIMING SPECIFICATIONS Guaranteed by design, VBAT ≥ 2.5 V if valid VBUS not present.
Symbol
tSU;DAT
tHD;DAT
tRCL
Parameter
Data Setup Time
Data Hold Time
SCL Rise Time
Conditions
250
Fast Mode
100
High−Speed Mode
10
tRDA
tRCL1
tFDA
tSU;STO
CB
SDA Rise Time
Rise Time of SCL after a Repeated
START Condition and after ACK Bit
SDA Fall Time
Stop Condition Setup Time
Max
Unit
ns
Standard Mode
0
3.45
ms
Fast Mode
0
900
ns
High−Speed Mode, CB ≤ 100 pF
0
70
ns
High−Speed Mode, CB ≤ 400 pF
0
150
ns
ns
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
High−Speed Mode, CB ≤ 400 pF
SCL Fall Time
Typ
Standard Mode
High−Speed Mode, CB ≤ 100 pF
tFCL
Min
10
80
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
High−Speed Mode, CB ≤ 100 pF
10
40
High−Speed Mode, CB ≤ 400 pF
20
80
Standard Mode
20+0.1CB
1000
Fast Mode
20+0.1CB
300
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
20+0.1CB
300
Fast Mode
20+0.1CB
300
ns
ns
ns
High−Speed Mode, CB ≤ 100 pF
10
80
High−Speed Mode, CB ≤ 400 pF
20
160
Standard Mode
4
ms
Fast Mode
600
ns
High−Speed Mode
160
ns
Capacitive Load for SDA, SCL
400
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8
pF
FAN54005
ÕÕÕ
ÕÕÕ
ÕÕÕ
ÕÕÕ
ÕÕÕ
ÕÕÕ
ÕÕÕ
ŠŠŠ
ŠŠŠ
Timing Diagrams
ÖÖ
ÖÖ
ÖÖ
ÖÖ
ÖÖ
ÖÖ
ÖÖ
ÒÒÒÒ
ÒÒÒÒ
tF
SDA
SCL
tSU;STA
tR
TSU;DAT
tHIGH
tLOW
tHD;STA
tHD;DAT
tBUF
tHD;STO
tHD;STA
REPEATED
START
START
STOP
Figure 4. I2C Interface Timing for Fast and Slow Modes
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ÙÙ
ŸŸŸ
ŸŸŸ
tFDA
SDAH
tSU;STA
SCLH
tRDA
REPEATED
START
tFCL
tRCL
tSU;STO
tHIGH
tLOW
tHD;STA
REPEATED
START
ÜÜÜܦ¦ŽŽŽ
ÜÜÜܦ¦
ÛÛŽŽŽ
ÛÛ
ÛÛ
ÛÛ
ÛÛ
tSU;DAT
tRCL1
ÔÔÔ
ÔÔÔÑÑ
ÑÑ
ÔÔÔÑÑ
ÔÔÔÑÑ
ÔÔÔÑÑ
ÔÔÔ
ÑÑ
ÔÔÔÑÑ
ÚÚÚ
ÓÓ
ÚÚÚÓÓ
tHD;DAT
note A
= MCS Current Source Pull−up
= RP Resistor Pull−up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 5. I2C Interface Timing for High−Speed Mode
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STOP
START
FAN54005
Charge Mode Typical Characteristics
180
900
160
800
Battery Charge Current (mA)
Battery Charge Current (mA)
Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.
140
120
100
5.5 VBUS
80
700
600
500
5.5 VBUS
400
5.0 VBUS
5.0 VBUS
4.7 VBUS
60
2.5
4.7 VBUS
3.0
3.5
4.0
300
4.5
2.5
3.0
Battery Voltage, VBAT (V)
3.5
4.0
4.5
Battery Voltage, VBAT (V)
Figure 6. Battery Charge Current vs. VBUS with
IINLIM=100 mA, VOREG=4.35V
Figure 7. Battery Charge Current vs. VBUS with
IINLIM=500 mA, VOREG=4.35V
97%
94%
4.3 VBAT, 5.0 VBUS
3.8 VBAT, 5.0 VBUS
4.3 VBAT, 5.5 VBUS
94%
92%
91%
Efficiency
Efficiency
3.8 VBAT, 5.5 VBUS
88%
85%
90%
88%
4.7 VBUS
86%
5.0 VBUS
82%
100
300
500
700
900
1100
1300
1500
5.5 VBUS
84%
2.5
Battery Charge Current (mA)
3.0
3.5
4.0
4.5
Battery Voltage, VBAT (V)
Figure 8. Charger Efficiency, No
IINLIM,IOCHARGE=1450 mA
Figure 9. Charger Efficiency vs. VBUS,
IINLIM=500 mA, VOREG=4.35
Figure 10. Auto−Charge Startup at VBUS Plug−in,
OTG=0, VBAT=3.4 V
Figure 11. Auto−Charge Startup at VBUS Plug−in,
OTG=1, VBAT=3.4 V
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FAN54005
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.
Figure 12. Auto−Charge Startup with 300 mA
Limited Charger / Adaptor, OTG=1, VBAT=3.4 V
Figure 13. Charger Startup with HZ_MODE Bit
Reset, IINLIM=500 mA, IOCHARGE=1050 mA,
VOREG=4.2 V, VBAT=3.6 V
Figure 14. Battery Removal / Insertion During
Charging, VBAT=3.9 V, IOCHARGE=1050 mA, No
IINLIM, TE=0
Figure 15. Battery Removal / Insertion During
Charging, VBAT=3.9 V, IOCHARGE=1050 mA, No
IINLIM, TE=1
200
1.82
−30C
+25C
1.81
+85C
150
1.80
V REG (V)
High−Z Mode Input Current (mA)
250
100
50
1.79
−30C, 5.0 VBUS
1.78
+25C, 5.0 VBUS
+85C, 5.0 VBUS
0
1.77
4.0
4.5
5.0
5.5
0
6.0
1
2
3
4
1.8V Regulator Load Current (mA)
Input Voltage, V BUS (V)
Figure 16. VBUS Current in High−Impedance Mode
with Battery Open
Figure 17. VREG 1.8 V Output Regulation
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11
5
FAN54005
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C.
Sleep Mode Battery Current (mA)
10
8
6
4
−30C
2
+25C
+85C
0
2.5
3.0
3.5
4.0
4.5
Battery Voltage, VBAT (V)
Figure 18. No Battery, TE=0, VBUS Power Up
Sleep Mode Battery Current (mA)
10
Figure 19. Sleep Mode Battery Discharge Current,
SDA=SCL=0 V, VBUS Open
VBUS open,
SDA=SCL=0V
VBUS open,
SDA=SCL=1.8V
8
VBUS=5.0V,
SDA=SCL=0V,
DIS or HZ=1
6
4
2
0
2.5
3.0
3.5
4.0
4.5
Battery Voltage, VBAT (V)
Figure 20. Battery Discharge Current vs. Mode
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12
FAN54005
Boost Mode Typical Characteristics
100
100
95
95
Efficiency (%)
Efficiency (%)
Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VBAT = 3.6 V, and TA = 25°C.
90
85
80
90
85
−30C, 3.6VBAT
80
3.0 VBAT
+25C, 3.6VBAT
3.6 VBAT
4.2 VBAT
75
0
100
200
300
400
+85C, 3.6VBAT
75
500
0
100
VBUS Load Current (mA)
Figure 21. Efficiency vs. VBAT
5.15
5.10
5.05
5.00
4.90
4.90
4.85
300
400
−30C, 3.6VBAT
500
+85C, 3.6VBAT
5.00
4.95
4.85
0
VBUS Load Current (mA)
300
+25C
Quiescent Current (mA)
250
+85C
200
150
100
50
3.5
200
300
400
500
Figure 24. Output Regulation Over−Temperature
−30C
3.0
100
VBUS Load Current (mA)
Figure 23. Output Regulation vs. VBAT
2.5
500
5.05
4.95
200
400
+25C, 3.6VBAT
5.10
4.2 VBAT
VBUS (V)
VBUS (V)
5.15
3.6 VBAT
100
300
Figure 22. Efficiency Over−Temperature
3.0 VBAT
0
200
VBUS Load Current (mA)
4.0
4.5
Battery Voltage, V BAT (V)
Figure 25. Quiescent Current
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13
FAN54005
Boost Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VBAT = 3.6 V, and TA = 25°C.
Figure 26. Boost PWM Waveform
50
50
40
3.0 VBAT
−30C, 3.6VBAT
3.6 VBAT
+25C, 3.6VBAT
40
4.2 VBAT
VBUS Ripple (mVpp)
VBUS Ripple (mVpp)
Figure 27. Boost PFM Waveform
30
20
+85C, 3.6VBAT
30
20
10
10
0
0
0
100
200
300
400
500
0
100
200
300
400
VBUS Load Current (mA)
VBUS Load Current (mA)
Figure 28. Output Ripple vs. VBAT
Figure 29. Output Ripple vs. Temperature
Figure 30. Startup, 3.6 VBAT, 44 W Load, Additional
10 mF, X5R Across VBUS
Figure 31. VBUS Fault Response, 3.6 VBAT
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500
FAN54005
Boost Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, RSNS = 68 mW, VBAT = 3.6 V, and TA = 25°C.
Figure 32. Load Transient, 5−155−5 mA, tR=tF=100 ns
Figure 33. Load Transient, 5−255−5 mA, tR=tF=100 ns
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15
FAN54005
Circuit Description / Overview
Battery Charging Curve
When charging batteries with a current−limited input source,
such as USB, a switching charger’s high efficiency over a
wide range of output voltages minimizes charging time.
The FAN54005 combines a highly integrated
synchronous buck regulator for charging with a
synchronous boost regulator, which can supply 5 V to USB
On−The−Go (OTG) peripherals. The FAN54005 employs
synchronous rectification for both the charger and boost
regulators to maintain high efficiency over a wide range of
battery voltages and charge states.
The FAN54005 has three operating modes:
1. Charge Mode: Charges a single−cell Li−ion or
Li−polymer battery.
2. Boost Mode: Provides 5 V power to USB−OTG
with an integrated synchronous rectification boost
regulator using the battery as input.
3. High−Impedance Mode: Both the boost and
charging circuits are OFF in this mode. Current
flow from VBUS to the battery or from the battery
to VBUS is blocked in this mode. This mode
consumes very little current from VBUS or the
battery.
If the battery voltage is below VSHORT, a linear current
source pre−charges the battery until VBAT reaches VSHORT.
The PWM charging circuit is then started and the battery is
charged with a constant current if sufficient input power is
available. The current slew rate is limited to prevent
overshoot.
During the current regulation phase of charging, IINLIM or
the programmed charging current limits the amount of
current available to charge the battery and power the system.
The effect of IINLIM on IOCHARGE can be seen in Figure 35.
VOREG
V
OREG
I CHARGE
I TERM
VSHORT
VSHORT
I SHORT
ISHORT
Charge Mode and Registers
Note: Default settings are denoted by bold typeface.
PRE−
CHARGE
CONSTANT CURRENT
(CC)
CONSTANT
VOLTAGE (CV)
Figure 34. Charge Curve, IOCHARGE Not Limited by
IINLIM
Charge Mode
In Charge Mode, FAN54005 employs four regulation loops:
1. Input Current: Limits the amount of current drawn
from VBUS. This current is sensed internally and
can be programmed through the I2C interface.
2. Charging Current: Limits the maximum charging
current, which is sensed using an external RSNS.
Choose RSNS to provide the desired IOCHARGE and
ITERM currents for your system, relative to the
VRSNS levels determined by the IOCHARGE and
ITERM register settings, as shown in Table 4 and
Table 5, respectively.
3. Charge Voltage: The regulator is restricted from
exceeding this voltage. As the internal battery
voltage rises, the battery’s internal impedance and
RSNS work in conjunction with the charge voltage
regulation to decrease the amount of current
flowing to the battery. Battery charging is
completed when the voltage across RSNS drops
below the threshold determined by ITERM.
4. Temperature: If the IC’s junction temperature
reaches 120°C, charge current is reduced until the
IC’s temperature stabilizes at 120°C.
5. Dynamic Input Voltage Control (DIVC) limits the
amount of drop on VBUS to a programmable
voltage (VSP) to accommodate incompatible
adapters that limit current to a lower current than
might be available from a “normal” USB adapter.
VOREG
ITERM
VSHORT
ISHORT
PRE−
CHARGE
CURRENT REGULATION
VOLTAGE
REGULATION
Figure 35. Charge Curve, IINLIM Limits IOCHARGE
Assuming that VOREG is programmed to the cell’s fully
charged “float” voltage, the current that the battery accepts
with the PWM regulator limiting its output (sensed at
VBAT) to VOREG declines, and the charger enters the
voltage regulation phase of charging. When the current
declines to the programmed ITERM value, the charge cycle
is complete. Charge current termination can be disabled by
resetting the TE bit (REG 01[3]).
The charger output or “float” voltage can be programmed
by the OREG bits from 3.5 V to 4.44 V in 20 mV increments
as shown in Table 8.
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16
FAN54005
A new charge cycle begins when one of the following
occurs:
• The battery voltage falls below VOREG – VRCH
• VBUS Power on Reset (POR)
• CE or HZ_MODE is reset through I2C write to
CONTROL1 (REG 01) register.
Table 8. OREG BITS (REG 02[7:2]) vs. CHARGER
VOUT (VOREG) FLOAT VOLTAGE
Decimal
Hex
VOREG
Decimal
Hex
VOREG
0
00
3.50
32
20
4.14
1
01
3.52
33
21
4.16
2
02
3.54
34
22
4.18
3
03
3.56
35
23
4.20
4
04
3.58
36
24
4.22
5
05
3.60
37
25
4.24
6
06
3.62
38
26
4.26
7
07
3.64
39
27
4.28
8
08
3.66
40
28
4.30
OREG
9
09
3.68
41
29
4.32
10
0A
3.70
42
2A
4.34
11
0B
3.72
43
2B
4.36
12
0C
3.74
44
2C
4.38
13
0D
3.76
45
2D
4.40
14
0E
3.78
46
2E
4.42
15
0F
3.80
47
2F
4.44
16
10
3.82
48
30
4.44
17
11
3.84
49
31
4.44
18
12
3.86
50
32
4.44
19
13
3.88
51
33
4.44
20
14
3.90
52
34
4.44
21
15
3.92
53
35
4.44
22
16
3.94
54
36
Charge Current Limit (IOCHARGE)
Charge current limit is established by regulating the
voltage across RSNS (VRSNS) to the value controlled by the
IOCHARGE bits. Select RSNS in the range of 68 mW < RSNS
< 180 mW.
Charge current is further limited by the IO_LEVEL (Reg
05[5]) bit by default (IO_LEVEL=1). When IOLEVEL=1,
the voltage across RSNS is limited to 34.0 mV. When
IO_LEVEL=0 charge current is limited by the IOCHARGE
bits.
Table 10. IOCHARGE CURRENT AS FUNCTION OF
IOCHARGE (REG 04 [6:4]) BITS AND RSNS VALUE
IOCHARGE Range (mA)
HEX
VRSNS (mV)
180 mW
68 mW
0
00
37.4
208
550
1
01
44.2
246
650
2
02
51.0
283
750
3
03
57.8
321
850
4
04
71.4
397
1050
5
05
78.2
434
1150
4.44
6
06
91.8
510
1350
7
07
98.6
548
1450
23
17
3.96
55
37
4.44
24
18
3.98
56
38
4.44
25
19
4.00
57
39
4.44
26
1A
4.02
58
3A
4.44
27
1B
4.04
59
3B
4.44
28
1C
4.06
60
3C
4.44
29
1D
4.08
61
3D
4.44
30
1E
4.10
62
3E
4.44
31
1F
4.12
63
3F
4.44
Decimal
IOCHARGE
Termination Current Limit
Current charge termination is enabled when TE (REG
01[3])=1.
Table 11. ITERM CURRENT AS FUNCTION OF ITERM
BITS (REG 04[2:0]) AND RSNS RESISTOR VALUES
ITERM Range (mA)
Decimal
HEX
VRSNS (mV)
180 mW
68 mW
49
ITERM
The following charging parameters can be programmed by
the host through I2C:
0
00
3.3
18
1
01
6.6
37
97
Table 9. PROGRAMMABLE CHARGING PARAMETERS
2
02
9.9
55
146
Parameter
Name
Register
3
03
13.2
73
194
VOREG
REG 02[7:2]
4
04
16.5
92
243
IOCHARGE
REG 04[6:4]
5
05
19.8
110
291
IINLIM
REG 01[7:6]
6
06
23.1
128
340
Charge Termination Limit
ITERM
REG 04[2:0]
7
07
26.4
147
388
Weak Battery Voltage
VLOWV
REG 01[5:4]
Output Voltage Regulation
Battery Charging Current Limit
Input Current Limit
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17
FAN54005
When the charge current falls below ITERM, PWM
charging stops and the STAT bits change to READY (00) for
about 500 ms while the IC determines whether the battery
and charging source are still connected. STAT then changes
to CHARGE DONE (10), provided the battery and charger
are still connected.
LOW, and charging resumes using the default values with
the t15MIN timer running.
Normal charging is controlled by the host with the t32S
timer running to ensure that the host is alive. Charging with
the t15MIN timer running is used for charging that is
unattended by the host. If the t15MIN timer expires; the IC
turns off the charger, sets the CE bit, and indicates a timer
fault (110) on the FAULT bits (REG 00[2:0]). This sequence
prevents overcharge if the host fails to reset the t32S timer.
PWM Controller in Charge Mode
The IC uses a current−mode PWM controller to regulate
the output voltage and battery charge currents. The
synchronous rectifier (Q2) has a current limit that switches
off the FET when the current is more negative than ISYNC.
USB−Friendly Boot Sequence
At VBUS POR, the IC operates in accordance with its I2C
register settings. If no registers have been written (including
Safety, and the TMR_RST bit), typically due to an absence
of host communication, the chargers input current limit is
controlled by the OTG pin (100 mA if OTG is LOW and
500 mA if OTG is HIGH).
Once the host processor begins writing to the IC, charging
parameters are set by the host, which must continually reset
the t32S timer to continue charging using the programmed
charging parameters.
Charger Operation
VBUS Plug In
When the IC detects that VBUS has risen above VIN(MIN)1
(4.4 V), the IC applies a 100 W load from VBUS to GND. To
clear the VBUS Power−On−Reset (POR) and begin
charging, VBUS must remain above VIN(MIN)1 and below
VBUSOVP for tVBUS_VALID (30 ms) before the IC initiates
charging.
The VBUS validation sequence always occurs before
charging is initiated or re−initiated (for example, after a
VBUS OVP fault or a VRCH recharge initiation).
TVBUS_VALID ensures that unfiltered 50 / 60 Hz chargers
and other non−compliant chargers are rejected.
Input Current Limiting
To minimize charging time without overloading VBUS
current limitations, the IC’s input current limit can be
programmed by the IINLIM bits (REG 01[7:6]).
Table 12. INPUT CURRENT LIMIT
Safety Timer
Section references Figure 39.
At the beginning of charging, the IC starts a 15−minute
timer (t15MIN). When this times out, charging is terminated.
Writing to any register through I2C stops and resets the
t15MIN timer, which in turn starts a 32−second timer (t32S).
Setting the TMR_RST bit (REG 00[7]) resets the t32S timer.
If the t32S timer times out; charging is terminated, all
registers (except Safety) are set to their default values, the
FAULT bits are set to 110, STAT is pulsed HIGH and returns
IINLIM REG 01[7:6]
Input Current Limit
00
100 mA
01
500 mA
10
800 mA
11
No limit
The OTG pin establishes the input current limit when t15MIN
is running.
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18
FAN54005
Flow Charts
VBUS POR
YES
VBAT > V LOWV
HZ State
HZ, CE or
DISABLE Pin
set?
YES
Charge
Configuration
State
NO
NO
NO
T15Min Timer?
NO
HZ, CE or
DISABLE Pin
set?
YES
NO
T32Sec
Armed?
YES
YES
HZ, CE or
DISABLE Pin
set?
YES
NO
HZ State
T32Sec
Armed?
YES
NO
Reset all registers
Start T15MIN
Figure 36. Charger VBUS POR
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19
Charge State
FAN54005
Flow Charts (Continued)
CHARGE STATE
Disable Charging
NO
Indicate
VBUS Fault
VBAT < VSHORT
YES
Enable ISHORT ,
Reset Safety reg
VBUS OK?
NO
Indicate Charging
NO
VBUS OK?
YES
YES
PWM Charging
T15MIN
Timeout?
Indicate Charging
NO
Disable Charging
Indicate
VBUS Fault
YES
T15MIN
Timeout?
Indicate timer fault
YES
Set CE
Charge
Configuration
State
NO
NO
HIGHZ mode
NO
IOUT < ITERM
Termination enabled
VBAT > VOREG –VRCH
V BAT < VOREG –VRCH
Indicate Charge
Complete
Reset Safety reg
Delay tINT
NO
YES
Stop Charging
Battery Removed
VBAT < VOREG –VRCH
Enable IDET for TDETECT
Figure 37. Charge Mode
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20
YES
YES
Reset charge
parameters
FAN54005
Flow Charts (Continued)
Charge
Configuration
State
T32Sec
ARMED AND
CE = 0?
CE#
YES
Charge State
NO
Has T15Min
CE = 0
and CE#
NO
START T15Min
YES
VBAT < VOREG
for 262ms?
NO
YES
Figure 38. Charge Configuration
Charge Start
Start T15MIN
Reset Registers
YES
T32SEC
NO
Start T32SEC
Stop T15MIN
T15MIN
Active?
Expired?
YES
NO
I2C Write
YES
received?
NO
Timer Fault :
Set CE
CE
T15MIN
Expired?
NO
Continue
Charging
YES
Figure 39. Timer Flow Chart
Dynamic Input Voltage Control
If VBUS collapses to VSP when the current is ramping up, the
FAN54005 charges with an input current that keeps
VBUS=VSP. When the VSP control loop is limiting the charge
current, the SP bit (REG 05[4]) is set.
The FAN54005 has functionality that limits input current
in case a current−limited incompatible adapter is supplying
VBUS. These slowly increase the charging current until
either:
• IINLIM or IOCHARGE is reached
or
• VBUS=VSP.
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21
FAN54005
Table 13. VSP AS FUNCTION OF VSP BITS (REG 05[2:0])
Decimal
HEX
Table 15. VSAFE (VOREG Max. Limit) AS FUNCTION
OF VSAFE BITS (REG 06[3:0])
VSP
HEX
Max. OREG
(REG 02[7:2])
VOREG
Max. (V)
0
00
100011
4.20
1
01
100100
4.22
2
02
100101
4.24
3
03
100110
4.26
4
04
100111
4.28
5
05
101000
4.30
6
06
101001
4.32
Safety Settings
7
07
101010
4.34
FAN54005 contain a SAFETY register (REG 06) that
prevents the values in OREG (REG 02[7:2]) and
IOCHARGE (REG 04[6:4]) from exceeding the values of
the VSAFE and ISAFE values. Refer to Table 14 and
Table 15 for details.
After VBAT exceeds VSHORT, the SAFETY register is
loaded with its default value and may be written only before
any other register is written. The entire desired Safety
register value should be written twice to ensure the register
bits are set. After writing to any other register, the SAFETY
register is locked until VBAT falls below VSHORT.
The ISAFE (REG 06[6:4]) and VSAFE (REG 06[3:0])
registers establish the maximum values of VRSNS and
VOREG used by the control logic. If the host attempts to write
a value higher than VSAFE or ISAFE to OREG or
IOCHARGE, respectively; the VSAFE, ISAFE value
appears as the OREG, IOCHARGE register value,
respectively.
8
08
101011
4.36
9
09
101100
4.38
10
0A
101101
4.40
VSP
0
00
4.213
1
01
4.293
2
02
4.373
3
03
4.453
4
04
4.533
5
05
4.613
6
06
4.693
7
07
4.773
Decimal
VSAFE
11
0B
101110
4.42
12
0C
101111
4.44
13
0D
110000
4.44
14
0E
110001
4.44
15
0F
110010
4.44
Thermal Regulation and Protection
When the IC’s junction temperature reaches TCF (about
120°C), the charger reduces its output current to
37.4 mV/RSNS to prevent overheating. If the temperature
increases beyond TSHUTDOWN; charging is suspended, the
FAULT bits are set to 101, and STAT is pulsed HIGH. In
Suspend Mode, all timers stop and the state of the IC’s logic
is preserved. Charging resumes at programmed current after
the die cools to about 120°C.
Additional qJA data points, measured using the
FAN54005 evaluation board, are given in Table 16
(measured with TA=25°C). Note that as power dissipation
increases, the effective qJA decreases due to the larger
difference between the die temperature and ambient.
Table 14. ISAFE (IOCHARGE Limit) AS FUNCTION OF
ISAFE BITS (REG 06[6:4])
ISAFE Range (mA)
HEX
VRSNS (mV)
180 mW
68 mW
0
00
37.4
208
550
1
01
44.2
246
650
2
02
51.0
283
750
Dissipation (W)
qJA
3
03
57.8
321
850
0.504
54°C/W
4
04
71.4
397
1050
0.844
50°C/W
5
05
78.2
434
1150
1.506
46°C/W
6
06
91.8
510
1350
7
07
98.6
548
1450
Decimal
ISAFE
Table 16. EVALUATION BOARD MEASURED qJA
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22
FAN54005
Charge Mode Input Supply Protection
If VBAT is below VOREG – VRCH, the battery is absent and
the IC:
1. Sets the registers to their default values.
2. Sets the FAULT bits to 111.
3. Resumes charging with default values after tINT.
Sleep Mode
When VBUS falls below VBAT + VSLP, and VBUS is above
VIN(MIN)1, the IC enters Sleep Mode to prevent the battery
from draining into VBUS. During Sleep Mode, reverse
current is disabled by body switching Q1.
Battery Short−Circuit Protection
If the battery voltage is below the short−circuit threshold
(VSHORT); a linear current source, ISHORT, supplies VBAT
until VBAT > VSHORT.
Input Supply Low−Voltage Detection
The IC continuously monitors VBUS during charging. If
VBUS falls below VIN(MIN)2, the IC:
1. Terminates charging
2. Pulses the STAT pin, sets the STAT bits to 11, and
sets the FAULT bits to 011.
If VBUS recovers above the VIN(MIN)1 rising threshold
after time tINT (about two seconds), the charging process is
repeated. This function prevents the USB power bus from
collapsing or oscillating when the IC is connected to a
suspended USB port or a low−current−capable OTG device.
System Operation with No Battery
The FAN54005 continues charging after VBUS POR with
the default parameters, regulating the VBAT line to 3.54 V
until the host processor issues commands or the t15MIN timer
expires. In this way, the FAN54005 can start the system
without a battery.
The FAN54005 soft−start function may interfere with the
system supply when the battery is absent. The soft−start
activates whenever VOREG, IINLIM, or IOCHARGE are set
from a lower to higher value. During soft−start, the IIN limit
drops to 100 mA for about 1 ms unless IINLIM is set to 11
(no limit). This could cause the system processor to fail to
start. To avoid this behavior, use the following sequence.
1. Set the OTG pin HIGH. When VBUS is plugged
in, IINLIM is set to 500 mA until the system
processor powers up and can set parameters
through I2C.
2. Program the Safety Register.
3. Set IINLIM to 11 (no limit).
4. Set OREG to the desired value (typically 4.18).
5. Reset the IO_LEVEL bit, then set IOCHARGE.
6. Set IINLIM to 500 mA if a USB source is
connected.
During the initial system startup, while the charger IC is
being programmed, the system current is limited to 500 mA
for 1 ms during steps 4 and 5. This is the value of the
soft−start IOCHARGE current used when IINLIM is set to No
Limit.
If the system is powered up without a battery present, the
CV bit should be set. When a battery is inserted, the CV bit
is cleared.
Input Over−Voltage Detection
When VBUS exceeds VBUSOVP, the IC:
1. Turns off Q3
2. Suspends charging
3. Sets the FAULT bits to 001, sets the STAT bits to
11, and pulses the STAT pin.
When VBUS falls about 100 mV below VBUSOVP, the fault
is cleared and charging resumes after VBUS is revalidated.
VBUS Short While Charging
If VBUS is shorted with a very low impedance while the
IC is charging with IINLIMIT =100 mA, the IC may not meet
datasheet specifications until power is removed. To trigger
this condition, VBUS must be driven from 5 V to GND with
a high slew rate. Achieving this slew rate requires a 0 W
short from GND to the USB cable that is less than 10 cm
from the connector.
Charge Mode Battery Detection & Protection
VBAT Over−Voltage Protection
The OREG voltage regulation loop prevents VBAT from
overshooting the OREG voltage by more than 50 mV when
the battery is removed. When the PWM charger runs with no
battery, the TE bit is not set, and a battery is inserted that is
charged to a voltage higher than VOREG; PWM pulses stop.
If no further pulses occur for 30 ms, the IC sets the FAULT
bits to 100, sets the STAT bits to 11, and pulses the STAT pin.
Charger Status / Fault Status
The STAT pin indicates the operating condition of the IC
and provides a fault indicator for interrupt driven systems.
Table 17. STAT PIN FUNCTION
Battery Detection during Charging
The IC can detect the presence, absence, or removal of a
battery if the termination bit (TE) is set. During normal
charging, once VBAT is close to VOREG and the termination
charge current is detected, the IC terminates charging and
sets the STAT bits to 10. It then turns on a discharge current,
IDETECT, for tDETECT. If VBAT is still above VOREG – VRCH,
the battery is present and the IC sets the FAULT bits to 000.
EN_STAT
Charge State
STAT Pin
0
X
OPEN
X
Normal Conditions
OPEN
1
Charging
LOW
X
Fault (Charging or Boost)
128 ms Pulse, then
OPEN
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23
FAN54005
Boost Mode
The FAULT bits (REG 00[2:0]) indicate the type of fault
in Charge Mode. See Table 18 for details.
Boost Mode can be enabled if the IC is in 32−Second
Mode with the OTG pin and OPA_MODE bits as indicated
in Table 21. The OTG pin ACTIVE state is 1 if OTG_PL=1
and 0 when OTG_PL=0.
If boost is active using the OTG pin, Boost Mode is
initiated even if the HZ_MODE=1. The HZ_MODE bit
overrides the OPA_MODE bit.
Table 18. FAULT STATUS BITS DURING CHARGE MODE
Fault Bit
B2
B1
B0
0
0
0
Normal (No Fault)
0
0
1
VBUS OVP
0
1
0
Sleep Mode
0
1
1
Poor Input Source
1
0
0
Battery OVP
1
0
1
Thermal Shutdown
1
1
0
Timer Fault
1
1
1
No Battery
Fault Description
Table 21. ENABLING BOOST
OTG_EN
OTG Pin
1
ACTIVE
X
X
Enabled
X
X
0
1
Enabled
X
ACTIVE
X
0
Disabled
0
X
1
X
Disabled
1
ACTIVE
1
1
Disabled
0
ACTIVE
0
0
Disabled
Charge Mode Control Bits
either HZ_MODE or CE through I2C disables the
Setting
charger and puts the IC into High−Impedance Mode. The
t32S timer will continue to run. If it is allowed to expire, all
registers (except SAFETY) reset, which enables t15MIN
charging. When the t15MIN expires, the IC sets the CE bit and
the IC enters High−Impedance Mode. If CE was set by
t15MIN overflow, a new charge cycle can only be initiated
through I2C or VBUS POR.
Setting the RESET bit clears all registers (except Safety).
DISABLE Pin
CE
Boost PWM Control
The IC uses a minimum on−time and computed minimum
off−time to regulate VBUS. The regulator achieves
excellent transient response by employing current−mode
modulation. This technique causes the regulator to exhibit a
load line. During PWM Mode, the output voltage drops
slightly as the input current rises. With a constant VBAT, this
appears as a constant output resistance.
The “droop” caused by the output resistance when a load
is applied allows the regulator to respond smoothly to load
transients with no undershoot from the load line. This can be
seen in Figure 32 and Figure 40.
HZ_MODE
ENABLE
0
0
0
DISABLE
X
1
X
DISABLE
X
X
1
DISABLE
1
X
X
Raising the DISABLE pin does stop the t32S from
advancing. If the DISABLE pin is raised during t15MIN
charging, the t15MIN timer is reset.
350
325
Output Resistance (mΩ)
Operational Mode Control
OPA_MODE (REG 01[0]) and the HZ_MODE (REG
01[1]) bits in conjunction with the FAULT state define the
operational mode of the charger.
Table 20. OPERATION MODE CONTROL
HZ_MODE
OPA_MODE
FAULT
0
0
0
Charge
0
X
1
Charge Configure
0
1
0
Boost
1
X
X
High Impedance
BOOST
To remain in Boost Mode, the TMR_RST must be set by
the host before the t32S timer times out. If t32S times out in
Boost Mode; the IC resets all registers, pulses the STAT pin,
sets the FAULT bits to 110, and resets the BOOST bit. VBUS
POR or reading REG00 clears the fault condition.
Table 19. DISABLE PIN AND CE BIT FUNCTIONALITY
Charging
HZ_MODE OPA_MODE
Operation Mode
300
275
250
225
200
2.0
2.5
3.0
3.5
4.0
4.5
Figure 40. Output Resistance (ROUT)
The IC resets the OPA_MODE bit whenever the boost is
deactivated, whether due to a fault or being disabled by
setting the HZ_MODE bit.
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24
5.0
FAN54005
VBUS as a function of ILOAD can be computed when the
regulator is in PWM Mode (continuous conduction) as:
V BUS + 5.07 * R OUT @ I LOAD
To ensure VBUS does not pump significantly above the
regulation point, the boost switch remains off as long as the
actual output voltage is greater than the regulation point.
(eq. 1)
Boost Faults
At VBAT=3.3 V, and ILOAD=200 mA, VBUS would drop to:
V BUS + 5.07 * 0.26 @ 0.2 + 5.018 V
If a BOOST fault occurs:
1. The STAT pin pulses.
2. OPA_MODE bit is reset.
3. The power stage is in High−Impedance Mode.
4. The FAULT bits (REG 00[2:0]) are set per
Table 23
(eq. 2)
At VBAT=2.7 V, and ILOAD=200 mA, VBUS would drop to:
V BUS + 5.07 * 0.327 @ 0.2 + 5.005 V
(eq. 3)
PFM Mode
If VBUS > VBOOST (nominally 5.07 V) when the
minimum off−time has ended, the regulator enters PFM
Mode. Boost pulses are inhibited until VBUS < VBOOST. The
minimum on−time is increased to enable the output to pump
up sufficiently with each PFM boost pulse. Therefore the
regulator behaves like a constant on−time regulator, with the
bottom of its output voltage ripple at 5.07 V in PFM Mode.
Restart After Boost Faults
If boost was enabled with the OPA_MODE bit and
OTG_EN=0, Boost Mode can only be enabled through
subsequent I2C commands since OPA_MODE is reset on
boost faults. If OTG_EN=1 and the OTG pin is still
ACTIVE (see Table 21), the boost restarts after a 5.2 ms
delay, as shown in Figure 41. If the fault condition persists,
restart is attempted every 5 ms until the fault clears or an I2C
command disables the boost.
Table 22. BOOST PWM OPERATING STATES
Mode
Description
Invoked When
LIN
Linear Startup
VBAT > VBUS
SS
Boost Soft−Start
VBUS < VBOOST
BST
Boost Operating Mode
VBAT > UVLOBST and
SS Completed
Table 23. FAULT BITS DURING BOOST MODE
Fault Bit
B2
B1
B0
0
0
0
Normal (no fault)
0
0
1
VBUS > VBUSOVP
When the boost regulator is shut down, current flow is
prevented from VBAT to VBUS, as well as reverse flow
from VBUS to VBAT.
0
1
0
VBUS fails to achieve the voltage required to
advance to the next state during soft−start or
sustained (>50 ms) current limit during the BST
state.
LIN State
0
1
1
VBAT < UVLOBST
When the boost is enabled, if VBAT > UVLOBST, the
regulator first attempts to bring PMID within 400 mV of
VBAT using an internal 450 mA current source from VBAT
(LIN State). If PMID has not achieved VBAT – 400 mV after
560 ms, a FAULT state is initiated.
1
0
0
N/A: This code does not appear.
1
0
1
Thermal shutdown
1
1
0
Timer fault; all registers reset.
1
1
1
N/A: This code does not appear.
Startup
SS State
Fault Description
VBUS 0
When PMID > VBAT – 400 mV, the boost regulator begins
switching with a reduced peak current limit of about 50% of
its normal current limit. The output slews up until VBUS is
within 5% of its setpoint; at which time, the regulation loop
is closed and the current limit is set to 100%.
If the output fails to achieve 95% of its setpoint (VBST)
within 128 ms, the current limit is increased to 100%. If the
output fails to achieve 95% of its setpoint after this second
384 ms period, a fault state is initiated.
BATTERY
CURRENT
560
450mA
0
5200
64
BOOST
ENABLED
Figure 41. Boost Response Attempting to Start into
VBUS Short Circuit (times in ms)
VREG Pin
The 1.8 V regulated output on this pin can be disabled
through I2C by setting the DIS_VREG bit (REG 05[6]).
VREG can supply up to 2 mA. This circuit, which is
powered from PMID, is enabled only when PMID > VBAT
and does not drain current from the battery. During boost,
VREG is off. It is also off when the HZ_MODE bit (REG
01[1])=1.
BST State
This is the normal operating mode of the regulator. The
regulator uses a scheme of calculated tOFF, modulated tON
with a minimum tON. The calculated tOFF is proportional to
VIN / VOUT, which keeps the regulator’s switching
frequency reasonably constant in CCM.
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25
FAN54005
Monitor Register (Reg 10h)
A transaction ends with a STOP condition, which is
defined as SDA transitioning from 0 to 1 with SCL HIGH,
as shown in Figure 44.
Additional status monitoring bits enable the host
processor to have more visibility into the status of the IC.
The monitor bits are real−time status indicators and are not
internally debounced or otherwise time qualified.
The state of the MONITOR register bits listed in
High−Impedance Mode is only valid when VBUS is valid.
Slave Releases
SCL
The FAN54005’s serial interface is compatible with
Standard, Fast, Fast Plus, and High−Speed Mode I2C−Bus
specifications. The SCL line is an input and the SDA line is
a bi−directional open−drain output; it can only pull down the
bus when active. The SDA line only pulls LOW during data
reads and signaling ACK. All data is shifted in MSB (bit 7)
first.
Figure 44. Stop Bit
During a read from the FAN54005 (Figure 47), the master
issues a Repeated Start after sending the register address and
before resending the slave address. The Repeated Start is a
1−to−0 transition on SDA while SCL is HIGH, as shown in
Figure 45.
Slave Address
High−Speed (HS) Mode
Table 24. I2C SLAVE ADDRESS BYTE
Part Type
7
6
5
4
3
2
1
0
FAN54005
1
1
0
1
0
1
0
R/W
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when
the bus master sends the HS master code 00001XXX after
a start condition. The master code is sent in Fast or Fast Plus
Mode (less than 1 MHz clock); slaves do not ACK this
transmission.
The master then generates a repeated start condition
(Figure 45) that causes all slaves on the bus to switch to HS
Mode. The master then sends I2C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a stop bit (Figure 44)
is sent by the master. While in HS Mode, packets are
separated by repeated start conditions (Figure 45).
In hex notation, the slave address assumes a 0 LSB. The
hex slave address for the FAN54005 is D4H and is D6H for
all other parts in the family.
Bus Timing
As shown in Figure 42, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
Data change allowed
Slave Releases
SDA
SDA
TH
TSU
SCL
tHD;STA
SLADDR
MS Bit
Figure 45. Repeated Start Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 43.
THD;STA
tSU;STA
ACK(0) or
NACK(1)
SCL
Figure 42. Data Transfer Timing
SDA
tHD;STO
ACK(0) or
NACK(1)
SDA
I2C Interface
Master Drives
Read and Write Transactions
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
defined as
Master Drives Bus
Slave Address
MS Bit
and
Slave Drives Bus
SCL
All addresses and data are MSB first.
Figure 43. Start Bit
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26
FAN54005
Table 25. BIT DEFINITIONS FOR FIGURE 46 AND FIGURE 47
Symbol
Definition
S
START, see Figure 43
A
ACK. The slave drives SDA to 0 to acknowledge the preceding packet.
A
NACK. The slave sends a 1 to NACK the preceding packet.
R
Repeated START, see Figure 45
P
STOP, see Figure 44
7 bits
S
Slave Address
0
0
8 bits
0
8 bits
0
A
Reg Addr
A
Data
A
P
Figure 46. Write Transaction
7 bits
S
Slave Address
0
0
8 bits
0
A
Reg Addr
A
7 bits
R
Slave Address
1
0
8 bits
1
A
Data
A
P
Figure 47. Read Transaction
Register Descriptions
The nine FAN54005 user−accessible registers are defined in Table 26.
Table 26. I2C REGISTER ADDRESS
Register
Address Bits
Name
REG#
7
6
5
4
3
2
1
0
CONTROL0
00
0
0
0
0
0
0
0
0
CONTROL1
01
0
0
0
0
0
0
0
1
OREG
02
0
0
0
0
0
0
1
0
IC_INFO
03
0
0
0
0
0
0
1
1
IBAT
04
0
0
0
0
0
1
0
0
SP_CHARGER
05
0
0
0
0
0
1
0
1
SAFETY
06
0
0
0
0
0
1
1
0
MONITOR
10h
0
0
0
1
0
0
0
0
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27
FAN54005
Table 27. REGISTER BIT DEFINITIONS
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
Bit
Name
Value
Type
CONTROL0
7
TMR_RST OTG
6
EN_STAT
1
0
STAT
00
Writing a 1 resets the t32S timer; writing a 0 has no effect
R
Returns the OTG pin level (1=HIGH)
R/W
BOOST
R
Charge in progress
10
Charge done
0
Fault
R
FAULT
R
IINLIM
01
R/W
5:4
VLOWV
00
R/W
TE
10
3.6 V
11
3.7 V
R/W
CE
0
0
R/W
OPA_MODE
0
Charger enabled.
Charger disabled. The T32S timer is not suspended
R/W
1
0
Disable charge current termination
Enable charge current termination
1
HZ_MODE
Weak battery voltage threshold
3.4 V
3.5 V
0
Default Value=0111 0000 (70h)
Input current limit, see Table 12
01
1
1
Fault status bits: for Charge Mode, see Table 18
Register Address: 01
7:6
2
IC is not in Boost Mode
IC is in Boost Mode
CONTROL1
3
Ready
01
1
2:0
Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate
faults
Enables STAT pin LOW when IC is charging
11
3
Default Value=X1XX 0XXX
W
1
5:4
Description
Register Address: 00
Not High−Impedance Mode
See Table 21
High−Impedance Mode
R/W
1
Charge Mode
Boost Mode
OREG
Register Address: 02
Default Value=0000 1010 (0Ah)
7:2
OREG
000010
R/W
Charger output “float” voltage; programmable from 3.5 to 4.44 V in 20 mV increments;
defaults to 000010 (3.54 V). See Table 8
1
OTG_PL
0
R/W
OTG pin active LOW
0
OTG_EN
1
0
OTG pin active HIGH
R/W
1
Disables OTG pin
Enables OTG pin
IC_INFO
Register Address: 03
Default Value=100101XX (9Xh)
7:5
Vendor Code
100
R
Identifies ON Semiconductor as the IC supplier
4:2
PN
101
R
Part number bits, see the Ordering Information on page 1
1:0
REV
XX
R
IBAT
IC Revision bits
Register Address: 04
Default Value=1000 1001 (89h)
7
RESET
1
W
Writing a 1 resets charge parameters, except the Safety register (REG 06), to their defaults: writing a 0 has no effect; read returns 1
6:4
IOCHARGE
000
R/W
Programs the maximum charge current when IO_LEVEL (REG 05[5]) = 0. See Table 10
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28
FAN54005
Table 27. REGISTER BIT DEFINITIONS
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
Bit
Name
Value
Type
3
Reserved
1
R
2:0
ITERM
001
R/W
SP_CHARGER
Reserved
0
R
6
DIS_VREG
0
R/W
1
IO_LEVEL
SP
0
R/W
0
EN_LEVEL
0
R
VSP
100
Unused
1.8 V regulator is ON
Output current is controlled by the IOCHARGE bits
DIVC is not active (VBUS is able to stay above VSP)
DIVC has been detected and VBUS is being regulated to VSP
R
1
2:0
Default Value=001X X100
Output current control is limited to 34 mV across RSNS
1
3
Sets the current used for charging termination. See Table 11
1.8 V regulator is OFF
1
4
Unused
Register Address: 05
7
5
Description
DISABLE pin is LOW
DISABLE pin is HIGH
R/W
SAFETY
DIVC input regulation voltage. See Table 13
Register Address: 06
Default Value=0100 0000 (40h)
7
Reserved
0
R
6:4
ISAFE
100
R/W
Sets the maximum IOCHARGE value used by the control circuit. See Table 14
3:0
VSAFE
0000
R/W
Sets the maximum VOREG used by the control circuit. See Table 15
MONITOR
Bit disabled and always returns 0 when read back
Register Address: 10h (16)
7
ITERM_CMP
R
ITERM comparator output, 1 when VRSENSE > See Table 11
6
VBAT_CMP
R
Output of VBAT comparator
1 during charging indicates VBAT > VSHORT
1 during HZ_MODE indicates VBAT > VLOWV
1 during Boost Mode indicated VBAT > UVLOBST
5
LINCHG
R
30 mA linear charger ON
4
T_120
R
Thermal regulation comparator; when=1 and T_145=0, the charge current is limited to
22.1 mV across RSENSE
3
ICHG
R
0 indicates the IOCHARGE loop is controlling the battery charge current
2
IBUS
R
0 indicates the IBUS (input current) loop is controlling the battery charge current
1
VBUS_VALID
R
1 indicates VBUS has passed validation and is capable of charging
0
CV
R
1 indicates the constant−voltage loop (OREG) had been active at least once since the
last VBUS plug in
0 indicates the constant−voltage loop (OREG) had never been reached since the last
VBUS plug in or the part is in the Charge Done state with TE=1
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29
FAN54005
PCB Layout Recommendations
Bypass capacitors should be placed as close to the IC as
possible. In particular, the total loop length for CMID should
be minimized to reduce overshoot and ringing on the SW,
PMID, and VBUS pins. All power and ground pins must be
routed to their bypass capacitors, using top copper whenever
possible. Copper area connecting to the IC should be
maximized to improve thermal performance if possible.
Figure 48. PCB Layout Recommendations
The table below pertains to the MOD information on the following page.
PRODUCT−SPECIFIC DIMENSIONS
Product
D
E
X
Y
FAN54005UCX
1.960 ±0.030 mm
1.870 ±0.030 mm
0.335 mm
0.180 mm
ON Semiconductor is licensed by the Philips Corporation to use the I2C bus protocol.
www.onsemi.com
30
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP20 1.96x1.87x0.586
CASE 567SL
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON16608G
WLCSP20 1.96x1.87x0.586
DATE 30 NOV 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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