FAN6292CMX

FAN6292CMX Secondary Side Synchronous Rectifier Controller for Flyback Converters www.onsemi.com Descriptions The FAN6292CMX is a secondary−side synchronous rectifier (SR) controller for an isolated flyback converter operating in Discontinuous Conduction Mode (DCM). The adaptive dead time control algorithm minimizes the body diode conduction of SR MOSFET while guaranteeing stable and robust SR operation against noise and disturbance caused by the circuit parasitic. When pair with FAN1080, PSR controller, FAN6292CMX can execute functions that are more valuable. Dynamic Response Enhancement (DRE) awakes primary controller quickly during load transient thus improves voltage dip. FAN6292C are also source only USB Type−C controllers which are optimized for mobile chargers and power adapters. It supports standard 3 A VBUS current level is compatible as a load switch, and helps to reduce BOM cost. SOIC8 CASE 751EB MARKING DIAGRAM ON ZXYTT 6292C MC Features • Support Discontinuous Conduction Modes (DCM) and Boundary • • • • • • • • Conduction Mode (BCM) Adaptive Turn−Off Dead Time Tuning for General SR MOSFET Application Turn−On Trigger Blanking Time (Minimum Gate OFF Time) for Improved Noise Immunity Dynamic Response Enhancement (DRE) Function to Improve System Dynamic Response Type−C Control for Standard 3 A VBUS Current Level N−Channel MOSFET Control as a Load Switch for USB Type−C Minimum Turn−On Delay (20 ns) Supporting General Output Voltage (VIN) Range : 3.25 V ∼ 20 V for LDO Input Fewest External Component Allowed Applications • Travel Adapter for Smart Phones, Feature Phones and Tablet PCs • AC−DC Adapters for Portable Devices that Require CV/CC Control • IoT Power Applications © Semiconductor Components Industries, LLC, 2018 February, 2019 − Rev. 1 1 Z X Y TT 6292C M C = Assembly Plant Code = Year Code = Week Code = Die Run Code = FAN6292C = SOP = Manufacture Code PIN CONNECTIONS DRAIN 1 8 GND LGATE 2 7 GATE VIN 3 6 VDD CC1 4 5 CC2 ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Publication Order Number: FAN6292CMX/D FAN6292CMX PACKAGE MARKING AND ORDERING INFORMATION Part Number Operating Temperature Package Packing Method FAN6292CMX −40 to 85_C 8−Lead, SOIC (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Load Switch L PI FUSE B CSNU RSNU + CE1 Vac CE2 VBUS USB Type−C NP NS RCL CCL CO2 CO1 RSTART − DSNU NTC RSER VBUS L GND DVDD RVDD CC1 MOSFET DRAIN GATE GND VIN CVDD RCDC RG VBUS FAN108 CC2 CC1 VDD LGATE NA AUX Gate RVS1 VDD VS RVS2 CS GND TX1+ RX1+ TX1− RX1− VBUS VBUS CC1 SBU2 D+ D− D− D+ SBU1 FAN6292C DG GND CC2 VBUS VBUS RX2− TX2− RX2+ TX2+ GND GND CDD RCSS GND RCS CC1 CC2 CVS CCC1 CCC2 Figure 1. FAN6292C Typical Application Schematic CC2 CC1 LGATE Type−C Detection LGATE Control OVP Detection Turn−on Trigger Blanking SR_COND(n−1) + VTH−ARM − LDO + − VIN−ON/VIN−OFF tS < tSLO−DIS Slope Detection DRAIN − VTH−ON IDRE VDD VIN + SR_COND(n) GATE D SET Q Turn−on CLR Q Turn−off VIN VTH−OFF + R SNS1 − R SNS2 − + Turn−off Trigger Blanking V DREI tS < tDRE−EN SR_COND(n−1) Minimum Turn On Time GND Figure 2. FAN6292C Function Block Diagram www.onsemi.com 2 VBUS CC2 VBUS FAN6292CMX Table 1. PIN FUNCTION DESCRIPTION Pin # Name 1 DRAIN Synchronous rectifier drain sense input. Description 2 LGATE Load switch controlling. 3 VIN Input voltage pin. This pin is connected to the output of the adaptor to monitor its output voltage and supply internal bias. IC operating current, and MOSFET gate drive current are supplied through this pin. 4 CC1 Configuration Channel 1. This pin is used to detect connections of Type−C cables and connectors. It is tied to the USB−C CC1. 5 CC2 Configuration Channel 2. This pin is used to detect connections of Type−C cables and connectors. It is tied to the USB−C CC2. 6 VDD Internal regulator 5 V output and gate drive power supply rail. Bypass with 1uF capacitor to GND. 7 GATE Gate driver output. 8 GND Ground. Table 2. ABSOLUTE MAXIMUM RATINGS Symbol VIN Parameter Power Supply Pin Voltage Value Unit −0.3 to 20 V −1 to 65 V VDRAIN Drain Sense Pin Voltage VLGATE LGATE PIN Voltage −0.3 to 20 V Internal Regulator Pin Voltage −0.3 to 6.5 V VGATE VDD Gate Pin Voltage −0.3 to 6.5 V VCC1 CC1 Pin Input Voltage −0.3 to 6.0 V VCC2 CC2 Pin Input Voltage −0.3 to 6.0 V 0.651 W PD Power Dissipation (TA = 25°C) TJ Operation Junction Temperature −40 to 125 °C Storage Temperature Range TSTG TL ESD −60 to 150 °C Lead Temperature (Soldering) 10 Seconds 260 °C Electrostatic Discharge Capability − Charged Device Model (CDM) 0.5 kV Electrostatic Discharge Capability − Human Body Model (HBM) 2 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. All voltage values, except differential voltages, are given with respect to the GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. Meets JEDEC standards JS−001−2012 and JESD 22−C101. Table 3. THERMAL CHARACTERISTICS Symbol Parameter Min Unit θJA Junction−to−Ambient Thermal Impedance 150.9 °C/W θJT Junction−to−Top Thermal Impedance 13.4 °C/W 4. TA = 25°C unless otherwise specified. Table 4. RECOMMENDED OPERATING RANGES Symbol VDRAIN VIN Min Max Unit Drain Pin Voltage Parameter −1 60 V VIN Pin Voltage 3.5 20 V VLGATE LGATE Pin Voltage 0 19.5 V VGATE GATE Pin Voltage 0 5.5 V www.onsemi.com 3 FAN6292CMX Table 4. RECOMMENDED OPERATING RANGES (continued) Symbol VDD VCC1/VCC2 Parameter VDD Pin Voltage Min Max Unit 3.1 5.5 V 0 5.8 V CC1/CC2 Pin Voltage Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 5. ELECTRICAL CHARACTERISTICS VIN = 5.5 V and TA = −40°C to 125°C unless otherwise noted. Parameter Symbol Test Conditions Min Typ Max Unit VDD SECTION VIN−ON Turn−On Threshold VIN rising 3.06 3.15 3.25 V VIN−OFF Turn−Off Threshold VIN falling 2.78 2.9 3.05 V Operating Current fSW = 100 kHz, CGATE = 3.3 nF, VIN = 5 V 2.5 3.2 mA 5.25 5.5 V 0.3 V IIN−OP POWER SUPPLY SECTION VDD Internal LDO Output Voltage VIN = 20 V 5.0 VDO Dropout Voltage of LDO IOUT = 10 mA, VIN = 3.3 V DRAIN VOLTAGE SENSING SECTION Comparator Input Offset Voltage (Note 5) Internal Design Suggestion VTH−ON Turn−On Threshold Voltage RDRAIN = 0 W (includes comparator input offset voltage) tSLO−DIS Slope Detection Disable Criteria (Note 7) tSLO−HYS Slope Detection Disable Criteria Hysteresis (Note 5) tON−DLY Turn On Delay (Note 5) VTH−OFF Turn−Off Threshold Tuning Range tOFF−DLY Comparator Delay for VTH−OFF (Note 5) With 0 mV overdrive From VTH−OFF to Gate voltage equal 1V VTH−ARM Gate Re−arming Threshold VIN = 5 V (typically 0.7 VDD) VOSI −1 0 1 mV −250 −200 −150 mV 53 58 63 ms With 50 mV overdrive From VTH−ON to Gate voltage over 1 V 8 ms 20 ns −5 5 20 mV ns 3.3 3.5 3.7 V tARM Gate Re−arming Time for Slope Detection (Note 5) 70 85 100 ns VTH−HGH Slope Detection High Threshold (Note 5) 0.4 0.5 0.6 V MINIMUM ON−TIME AND MINIMUM OFF−TIME SECTION tON−MIN tON−MIN−L NON−MIN−ST Minimum On−Time tS < (tSLO−DIS − tSLO−HYS) 2.16 2.4 2.64 ms Minimum On−Time at Light Load tS ≥ tSLO−DIS 1.50 1.65 1.80 ms Minimum tON Cycles during Start−up 3 Cycles tOFF−MIN−L Minimum Off−Time (Note 6) tS < (tSLO−DIS − tSLO−HYS) 1.53 1.70 1.87 ms tOFF−MIN−H Minimum On−Time at Light Load (Note 6) tS ≥ tSLO−DIS 3.6 4 4.4 ms From GATE OFF to VDRAIN rising above 0.5 V 170 200 230 ns DEAD TIME CONTROL SECTION tDEAD Dead Time Self−Tuning Target (Note 5) www.onsemi.com 4 FAN6292CMX Table 5. ELECTRICAL CHARACTERISTICS (continued) VIN = 5.5 V and TA = −40°C to 125°C unless otherwise noted. Parameter Symbol Test Conditions Min Typ Max Unit 6.8 7.5 8.2 V TYPE−C SECTION VLGATE−ON Drain Pin Threshold Voltage for LGATE Turn On IP−CC1 Source Current on CC1 Pin VIN = 5 V, VCC1 = 0 V 304 330 356 mA IP−CC2 Source Current on CC2 Pin VIN = 5 V, VCC2 = 0 V 304 330 356 mA ZOPEN−CC1 Input Impedance on CC1 Pin ZOPEN−CC2 Input Impedance on CC2 Pin 126 kW 126 kW VRA−CC1 Ra Impedance Detection Threshold on CC1 Pin VIN = 5 V, VCC2 = 0 V, decreasing VCC1 0.75 0.80 0.85 V VRA−CC2 Ra Impedance Detection Threshold on CC2 Pin VIN = 5 V, VCC1 = 0 V, decreasing VCC2 0.75 0.80 0.85 V VRD−CC1 Rd Impedance Detection Threshold on CC1 Pin VIN = 5 V, VCC2 = 0 V, increasing VCC1 2.45 2.60 2.75 V VRD−CC2 Rd Impedance Detection Threshold on CC2 Pin VIN = 5 V, VCC1 = 0 V, increasing VCC2 2.45 2.60 2.75 V UFP Detachment Debounce Time VIN = 5 V, VCC2 = 0 V, decreasing VCC1 10 15 20 ms UFP Attachment Debounce Time VIN = 5 V, VCC2 = 0 V, increasing VCC1 100 150 200 ms LGATE High Voltage for Load Switch Control VIN = 5 V 11 V tCC−Detach− Debounce tCC−Attach− Debounce VINGATE 8 DRE SECTION VDRE VIN Pin DRE Function Trigger Level (Note 6) VIN = 5.5 V → 4.5 V 4.68 4.78 4.85 V tDREI DRE Current Sinking Period (Note 5) VIN = 5.5 V → 4.5 V 1.2 1.5 1.8 ms tDRE−EN DRE Enable Period VIN = 5.5 V → 4.5 V 64 72 80 ms tRE−ARM DRE Re−arm Period VIN = 5.5 V → 4.5 V IDRE DRE Sinking Current Maximum IDRE cycle are 14 every gate switching cycles 4 ms 50 mA OUTPUT DRIVER SECTION VOL Gate Low Voltage VIN = 6 V VOH 0.25 V Gate High Voltage VIN = 6 V tR Gate Rise Time VIN = 6 V, CL = 3300 pF, GATE = 1 V → 4 V 4.9 90 ns V tF Gate Fall Time VIN = 6 V, CL = 3300 pF, GATE = 4 V → 1 V 30 ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Guaranteed by Design. 6. Specification operation temperature range −5°C to 85°C. 7. Specification operation temperature range −5°C to 50°C. www.onsemi.com 5 FAN6292CMX 1,030 1,030 1,020 1,020 VIN−OFF, Normalized VIN−ON, Normalized TYPICAL PERFORMANCE CHARACTERISTICS 1,010 1,000 0,990 0,980 0 25 50 75 85 1,000 0,990 0,980 0,970 −40 −30 −15 100 125 0 50 75 85 100 125 Temperature (5C) Figure 3. Turn−On Threshold Voltage (VIN−ON) vs. Temperature Figure 4. Turn−Off Threshold Voltage (VIN−OFF) vs. Temperature 1,030 1,060 1,020 1,040 1,010 1,000 0,990 0,980 0,970 −40 −30 −15 0 25 50 75 85 1,020 1,000 0,980 0,960 0,940 −40 −30 −15 100 125 0 Temperature (5C) Figure 5. Operating Supply Current (IIN−OP) vs. Temperature 1,060 1,009 1,040 1,006 1,020 1,000 0,980 0,960 0,940 −40 −30 −15 25 50 75 Temperature (5C) 85 100 125 Figure 6. Minimum On Time (tON−MIN) vs. Temperature VTH−ARM, Normalized tOFF−MIN, Normalized 25 Temperature (5C) tON−MIN, Normalized IIN−OP, Normalized 0,970 −40 −30 −15 1,010 1,003 1,000 0,997 0,994 0,991 0 25 50 75 Temperature (5C) 85 100 −40 −30 −15 125 Figure 7. Minimum Gate Turn Off Time (tOFF−MIN) vs. Temperature 0 25 50 75 Temperature (5C) 85 100 125 Figure 8. Gate Turn On Threshold Voltage(VTH−ARM) vs. Temperature www.onsemi.com 6 FAN6292CMX 1,018 1,060 1,012 1,040 IDRE, Normalized VDRE, Normalized TYPICAL PARFORMANCE CHARACTERISTICS (continued) 1,006 1,000 0,994 0,988 1,020 1,000 0,980 0,960 0,982 −40 −30 −15 0 25 50 75 Temperature (5C) 85 100 0,940 −40 −30 −15 125 1,120 1,090 1,080 1,060 tARM, Normalized tDRE−EN, Normalized 25 50 75 Temperature (5C) 85 100 125 Figure 10. Drain Pin Sinking Current for DRE Triggered (IDRE) vs. Temperature Figure 9. VIN Pin DRE Function Trigger Level (VDRE) vs. Temperature 1,040 1,000 0,960 0,920 1,030 1,000 0,970 0,940 0,880 −40 −30 −15 0 25 50 75 Temperature (5C) 85 100 0,910 −40 −30 −15 125 Figure 11. DRE Function Enable Period (tDRE−EN) vs. Temperature 0 25 50 75 Temperature (5C) 85 100 125 Figure 12. Gate Re−Arming Time for Slope Detection (tARM) vs. Temperature 1,120 tCC−Detach−Debounce, Normalized 1,06 tCC−Attach−Debounce, Normalized 0 1,04 1,02 1,00 0,98 0,96 0,84 −40 −30 −15 0 25 50 75 Temperature (5C) 85 100 125 1,080 1,040 1,000 0,960 0,920 0,880 −40 −30 −15 Figure 13. UFP Attachment Debounce Time (tCC−Attach−Debounce) vs. Temperature 0 25 50 75 Temperature (5C) 85 100 125 Figure 14. UFP Detachment Debounce Time (tCC−Detach−Debounce) vs. Temperature www.onsemi.com 7 FAN6292CMX 1,04 1,018 1,02 1,012 IP−CC1/CC2, Normalized VNGATE, Normalized TYPICAL PERFORMANCE CHARACTERISTICS (continued) 1,00 0,98 0,96 0,94 0,92 −40 −30 −15 0 25 50 75 Temperature (5C) 85 100 1,006 1,000 0,994 0,988 0,982 −40 −30 −15 125 Figure 15. LGATE High Level Voltage (VNGATE) vs. Temperature 0 25 50 75 Temperature (5C) 85 100 125 Figure 16. Source Current on CC1/CC2 Pin (IP−CC1/CC2) vs. Temperature FUNCTIONAL DESCRIPTION Overview SR Turn−On Algorithm For an ideal circuit operation, the SR control algorithm of FAN6292C is very straightforward. FAN6292C controls the SR MOSFET based on the instantaneous Drain−to−Source voltage as illustrated in Figure 17. When the body diode starts conducting, the drain−to−source voltage drops below the turn−on threshold (VTH−ON) which triggers the turn−on of the gate. Then the product of RDS_ON and instantaneous SR current determines the Drain−to−Source voltage. When the drain−to−source voltage reaches the turn−off threshold (VTH−OFF) as SR MOSFET current decreases to near zero, FAN6292C turns off the gate. If the turn off threshold (VTH−OFF) is very close to zero, the turn off dead time can be minimized. As the diagram shown in Figure 18, the turn−on of SR GATE is triggered by the three input signals of AND gate. The first input signal is TURN_ON_ALLOW signal, which is given after tOFF−MIN from the falling edge of VGS.SR signal. The second input is the TURN_ON_TRG signal, which is enabled after DRAIN pin voltage drops below VTH_ON. The third signal is tARM which allows turn−on trigger only when SR drain voltage drops fast with a large slope, preventing SR from triggering by the drain resonance voltage in DCM operation. SR Turn−Off Algorithm As diagram shown in Figure 19, the turn−off of SR GATE is triggered by turn off signal, which is enabled when VDS.SR >VTH_OFF. V DS.SR V TH−OFF V TH−ON tON.DLY V GS.SR tDEAD ISD.SR Figure 17. SR MOSFET Operation Waveforms (Ideal Case) www.onsemi.com 8 FAN6292CMX V TH−ARM GND V TH−OFF V DS.SR V TH−ON t ARM t ARM ARM ARM ARM t OFF−MIN TURN_ON_ALLOW TURN_ON_ALLOW TURN_ON_TRG TURN_ON_TRG V GS.SR GS.SR I DS.SR I DS.SR Figure 18. SR Turn−On Algorithm GND VTH_OFF V TH_ON V DS.SR V DS.SR V DS.SR Turn off Turn off Turn off Turn off SR_COND V GS.SR V GS.SR ISD.SR ISD.SR Figure 19. SR Turn−Off Algorithm VDRAIN Slope Detection FAN6292C checks SR drain voltage falling slope to distiguish primary FET off instant from the resonant curve. Continuously sees the time gap between SR drain voltage touches VTH−ARM and VTH−ON, this is compared with the internal fixed time of tARM, gate is only turn on when the time gap is less than tARM described at Figure 20. VTH−ARM tSLOPE VTH−ON Gate time Figure 20. Slope Detection Timing Chart www.onsemi.com 9 FAN6292CMX Gate Turn−On Slope detection is good for identification SR on instance from the resonance, however, system configuration may give huge impact on the SR drain voltage so slope detection is not always good way for gate ON identification especially at light load. Due to this at light load, slope detection is enabled or disabled depend on period of Gate switching cycles (tS) as below: • tS < (tSLO−DIS − tSLO−HYS): continually enable slope detection when tS is decreasing • tS ≥ tSLO−DIS: basically slope detection is disabled and only enabled after gate rising edge until end of tDRE−EN when tS increasing FAN6292C turns on SR FET according to the voltage across SR drain and primary switching period of tS. Depending on the tS, gate turn on criteria is different and it is as below: • tS < tSLO−DIS: SR FET ON when both (a) and (b) meet: (a) VDRAIN falling time from VTH−ARM to VTH−ON is less than tARM (b) VDRAIN ≤ VTH−ON • tS < (tSLO−DIS − tSLO−HYS):SR FET ON when meet: VDRAIN ≤ VTH−ON Gate Turn−On Blanking Time FAN6292C supports Primary Side Regulation (PSR) operation with Discontinuous Conduction Mode (DCM) and Boundary Conduction Mode (BCM) and the typical operating of Quasi−Resonant valley switching to make the best balance between efficiency and Electro Magnetic Interference (EMI). Together with slope detection, FAN6292C has a GATE turn on blanking time to avoid SR FET mis−triggered turn on at the first Quasi−Resonant cycle. Blanking time lengths depend on last Gate−to−Gate pulse period. The resonance period is decided by the parasitic capacitance summed at primary side and magnetizing inductance and normally is fixed once system configured but this changes as load changes, typically getting longer as load decreases. This is caused by the parasitic capacitances varies depending on voltage and stored energy at the transformer. To corresponds this change, FAN6292C adjust minimum OFF time (tOFF−MIN) depend on loading condition. Similar as slope detection, when tS is shorter than tSLO−DIS, tOFF−MIN becomes tOFF−MIN−H and when tS is longer than tSLO−DIS with a hysteresis then tOFF−MIN becomes tOFF−MIN−L. Slope detection disabled enabled tSLO−DIS−tSLO−HYS tS tSLO−DIS Figure 21. Slope Detect Enable/Disable Depend on tS Slope detection enabled disabled 1 1 tSLO−DIS tSLO−DIS−tSLO−HYS fSW Figure 22. Slope Detect Enable/Disable Depend on fSW Drain tS w t tS < t SLO−DIS SLO−DIS Gate Slope detection disabled enabled Gate Blanking tOFF−MIN−H tOFF−MIN−L tDRE−EN Figure 23. SR Conduction Timing Chart www.onsemi.com 10 FAN6292CMX Gate Turn−Off (Dead Time Self Tuning) VBUS V DL SR controller should turn on SR FET until the secondary discharging current become zero to avoid body diode conduction. Because the conduction loss of body diode is much higher than FET conduction loss. Therefore, the OFF dead time between SR off and magnetizing current become zero is recommended to minimized. But too small OFF dead time may raise the risk of SR FET and primary FET turn on simultaneously and too longer OFF dead time deteriorates the primary auxiliary winding voltage and gives impact on the PSR detection function. So proper value of OFF dead time is needed. It is possible that offset voltages are induced by the stray inductance by the bonding wires inside MOSFET package and PCB layout. Therefore, it is very difficult to maintain the same OFF dead time against all the circuit tolerances and variation of operating condition. In order to control MOSFET turn off when the secondary magnetizing current is near zero, FAN6292C build−in OFF dead time self−tuning, which has adaptively changing internal turn off thresholds. The off threshold, VTH−OFF, is modulated between 32 steps through internal up/down counter. FAN6292C measures OFF dead time from gate falling edge to drain voltage reaches VTH−HGH and compares with internal timing threshold tDEAD. When tDEAD_OFF > tDEAD then internal counter increases one−step and gate turned off a little delayed at next switching cycle. NP NS CO V Drain C GD C GS VGS PWM GATE RCS DRAIN GATE VIN FAN6292C Figure 24. Gate Coupling Signal Via Practice Capacitance VBUS NS GND RDrain GATE DRAIN Gate Pull Down Enhancement S1 SR Controller VIN Start−Up Operation FAN6292C supplies internal circuit power through VIN pin, there is integrate Low Drop Out (LDO) regulator to regulate internal voltage not exceed 5.5 V. In typical application, FAN6292C VIN pin is connect to VBUS of USB port so VIN gradually increases, FAN6292C start operation when VIN touches VIN−ON and stop operation when VIN drop to VIN−OFF. Accordingly, even before FAN6292C start to working, primary side is normally working and it gives impact on the secondary side. When primary FET turns on, the voltage cross over the primary winding becomes AC input voltage and it gives secondary winding voltage based on primary and secondary turn ratio. Once SR FET drain voltage is generated by the primary switching, the voltage will be divided by the capacitance of SR FET and some amount of voltage can be shown at the SR FET gate as in the Figure 24 and below equation. V GS_SR + C GD C GD ) C GS V Drain VIN−ON /V IN−OFF Figure 25. Gate Clamping Function Block Before FAN6292C Start−Up Operation Dynamic Response Enhancement (DRE) In PSR system control, the output voltage is regulated through detecting proportional voltage of auxiliary winding (VS) which is reflected from secondary winding. However VS signal can only generate and detects when primary side PWM switched. To get better standby power performance, the switching frequency is decreased to quite low frequency, the output voltage cannot be maintain as load suddenly increases from extremely light load to heavy load. In order to enhance load transient response time when primary switching frequency is much slower, FAN6292C build−in Dynamic Response Enhancement (DRE) function that continues monitor VIN pin voltage. FAN6292C generate a sinking current pulse from Drain of MOSFET to GND when VIN pin voltage is lower than threshold VDRE. The DRE sinking current which period is tDERI and current level is IDRE at Drain pin. The IDRE current flowing loop is depicted in the Figure 26 as a blue line and this informs the primary controller that output voltage drops lower than VDRE at any loading condition. (eq. 1) If the divided gate voltage is higher than SR FET urn−on threshold (VGS_TH) then SR FET can be turned on and this may make primary FET turn on and SR FET turn on simultaneously. In order to avoid mis−turn on SR FET, even before VIN voltage reaches VIN−ON, FAN6292C pulls down the gate voltage to GND by using drain voltage. www.onsemi.com 11 FAN6292CMX Type−C Control Function Description In order to give enough detection time window of primary controller FAN6292C enables DRE when primary switching frequency is low enough, FAN6292C starts counting from SR gate rising edge and DRE is enabled when the counted time is longer than tDRE−EN. DRE function generates sinking current (IDRE) for tDREI every 4us (tRE−ARM) until get drain rising edge signal when the primary PWM MOSFET gate turns on. Figure 27 shows DRE function timing chart. FAN6292C implements Type−C block to enable and disable an external load switch. Internally adapted charge pump lets FAN6292C control N−channel MOSFET as a load switch. It helps whole system be more cost competitive compared to P−channel MOSFET as a load switch. FAN6292C supports output current up to 3 A. In order to meet Type−C specification, 330 mA is applied on CC1 pin and CC2 pin. When Rd (5.1 kW) is attached on either CC1 or CC2, Load switch is turned−on after 150 ms denounce time. As soon as load switch is enabled, BC1.2 counter is enabled. To acknowledge detachment, it needs 15 ms denounce time. When load switch is turned−off. VBUS NP NS Co 1 PCB Layout Guidance Figure 28 shows the connection path of each loop at secondary side. The PCB layout was recommended as below: • Path1 is connected between Drain of MOSFET and FAN6292C DRAIN pin, trace length is needed as short as possible. RDRAIN could helpful on the drain pin ESD capability but should be less than 30 W to make sure DRE function. • GND path needs separate as three paths: Path2, Path3 and Path 4. FAN6292C detects Drain to source voltage of SR MOSFET via DRAIN pin and GND pin. Therefore FAN6292C GND pin needs connect to GND of CO1 directly then goes to Source of SR MOSFET. The path2 connection should be IC GND → CO1 → Source pin of SR MOSFET. Path 3 is connected to GND of CO1, CO2, and USB port after Path 2. Path 4 is connected IC GND and all component are needed connect to GND. • Path 6 is connected secondary winding and SR MOSFET, It’s trace length needs as short as possible to avoids switching noise coupling. I DRAIN SR Gate DRAIN I DRE VIN t DRE S1 VDRE Pulse V DREI t S > t DRE−EN Figure 26. DRE Internal Function Block VDRAIN VIN VDRE VDL Load Switch VBUS NP CSNU I DRAIN Path 5 RCL CCL NS CO1 CO2 I DRE GND … RSER Path 6 QSR Path 2 Path 3 Path 4 Path 1 Max DRE generating cycles are 14 cycles each PWM switching cycles PWM Gate CCC1 RDRAIN CC1 Figure 27. DRE Function Active Sequence RCS DRAIN VIN GND CC1 CVDD CCC2 FAN6292C GATE LGATE VDD CC2 CC2 Figure 28. PCB Layout Guideline www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC8 CASE 751EB ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13735G SOIC8 DATE 24 AUG 2017 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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