FDMF3030

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMF3030 — Extra-Small, High-Performance, High-Frequency, DrMOS Module Benefits Description  Ultra-Compact 6x6mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions    Fully Optimized for System Efficiency The DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET-plusdriver, power-stage solution for high-current, highfrequency, synchronous buck, DC-DC applications. The FDMF3030 integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact, 6x6mm package. Clean-Switching Waveforms with Minimal Ringing High-Current Handling Features      Over 93% Peak-Efficiency  Thermal Warning Flag for Over-Temperature Condition   Driver Output Disable Function (DISB# Pin)  Fairchild PowerTrench® Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing  Fairchild SyncFET™ Technology (Integrated Schottky Diode) in Low-Side MOSFET        High-Current Handling: 50A High-Performance PQFN Copper-Clip Package 3-State 5V PWM Input Driver Automatic Diode Emulation (Skip Mode) Enabled through ZCD_EN# Input Internal Pull-Up and Pull-Down for ZCD_EN# and DISB# Inputs, Respectively With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). The FDMF3030 uses ® Fairchild's high-performance PowerTrench MOSFET technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. A driver IC with reduced dead times and propagation delays further enhances performance. A thermal warning function indicates a potential over-temperature situation. The FDMF3030 also incorporates a ZeroCross Detect (ZCD_EN# pin) for improved light-load efficiency and provides a 3-state 5V PWM input for compatibility with a wide range of PWM controllers. Applications Notebook Computers Integrated Bootstrap Schottky Diode    Adaptive Gate-Drive Timing for Shoot-Through Protection  Desktop Computers, V-Core and Non-V-Core DC-DC Converters Under-Voltage Lockout (UVLO)   High-Current DC-DC Point-of-Load Converters  Small Form-Factor Voltage Regulator Modules Optimized for Switching Frequencies up to 1MHz Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliance High-Performance Gaming Motherboards Compact Blade Servers & Workstations, V-Core and Non-V-Core DC-DC Converters Networking and Telecom Microprocessor Voltage Regulators ® Based on the Intel 4.0 DrMOS Standard Ordering Information Part Number Current Rating Package Top Mark FDMF3030 50A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF3030 © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module September 2012 VIN 3V ~ 24V V5V CVIN CVDRV VCIN VDRV DISB# VIN RBOOT DISB# BOOT PWM Input PWM OFF CBOOT FDMF3030 PHASE ZCD_EN# ON VOUT VSWH LOUT Open-Drain Output THWN# COUT CGND PGND Figure 1. Typical Application Circuit DrMOS Block Diagram VDRV VIN BOOT UVLO VCIN Q1 HS Power MOSFET DBoot DISB# GH Level-Shift GH Logic  10µA 20k PHASE VCIN Dead-Time RUP_PWM Input 3-State Logic PWM Control VSWH VDRV RDN_PWM GL GL Logic THWN# VCIN Q2 LS Power MOSFET Temp. Sense 10µA CGND Figure 2. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 PGND ZCD_EN# DrMOS Block Diagram www.fairchildsemi.com 2 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Application Circuit Figure 3. Bottom View Figure 4. Top View Pin Definitions Pin # Name Description 1 ZCD_EN# When ZCD_EN#=HIGH, the low-side driver is the inverse of the PWM input. When ZCD_EN#=LOW, diode emulation is enabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor. 2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND. 3 VDRV Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH 7 PHASE 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 - 35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET. 36 GL 38 THWN# Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. 39 DISB# Output disable. When LOW, this pin disables power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller. For manufacturing test only. This pin must float; it must not be connected to any pin. Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. For manufacturing test only. This pin must float; it must not be connected to any pin. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 3 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Pin Configuration Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCIN Supply Voltage Referenced to CGND -0.3 7.0 V VDRV Drive Voltage Referenced to CGND -0.3 7.0 V VDISB# Output Disable Referenced to CGND -0.3 7.0 V VPWM PWM Signal Input Referenced to CGND -0.3 7.0 V Referenced to CGND -0.3 7.0 V Low Gate Manufacturing Test Pin Referenced to CGND -0.3 7.0 V Thermal Warning Flag Referenced to CGND -0.3 7.0 V Power Input Referenced to PGND, CGND -0.3 30.0 V Referenced to VSWH, PHASE -0.3 7.0 V VZCD_EN# ZCD Enable Signal Input VGL VTHWN# VIN VBOOT Bootstrap Supply VGH High Gate Manufacturing Test Pin VPHS PHASE VSWH Switch Node Input VBOOT Bootstrap Supply ITHWN# THWN# Sink Current IO(AV) Output Current(1) θJPCB 30.0 V -0.3 7.0 V Referenced to CGND -0.3 30.0 V Referenced to CGND -0.3 30.0 V Referenced to PGND, CGND (DC Only) -0.3 30.0 V Referenced to PGND, VIH_DISB). Table 1. When exiting a valid three-state condition, the FDMF3030 follows the PWM input command. If the PWM input goes from three-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 29. The FDMF3030 design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). UVLO and Disable Logic UVLO DISB# 0 Exiting Three-State Condition Driver State X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (see Table 2) 1 Open Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced, low-RDS(ON), N-channel MOSFET. The bias for GL is internally connected between the VDRV and CGND pins. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW. Note: 3. DISB# internal pull-down current source is 10µA. Thermal Warning Flag (THWN#) The FDMF3030 provides a thermal warning flag (THWN#) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State High-Side Driver The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, tD_HOLD-OFF. 135°C Reset 150°C Temperature Activation Temperature Normal Operation Thermal Warning LOW TJ_driver IC Figure 28. THWN Operation © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 12 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Functional Description The driver IC advanced design ensures minimum MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 29 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes V IH_PWM To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH-to-PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (tPD_PLGHL). Once the voltage across GH-to-PHASE falls below 1.7V, Q2 begins to turn on after adaptive delay tD_DEADOFF. V IH_PWM V IH_PWM V IL V IH_PWM V TRI_HI V TRI_HI V TRI_LO V IL_PWM PWM tR_GH PWM less than t D_HOLD‐OFF GH to VSWH tF_GH 90% tD_HOLD‐OFF 10% V IN CCM DCM DCM V OUT 1.7V VSWH GL 90% 1.7V tPD_PHGLL tD_DEADON 90% 10% 10% tPD_PLGHL tR_GL    tF_GL tD_DEADOFF Enter     3‐State tPD_TSGHH tD_HOLD‐OFF Enter  3 ‐State Exit  3‐State tPD_TSGHH Exit 3‐   State less than t D_HOLD‐OFF tD_HOLD‐OFF tPD_TSGLH Enter    3 ‐State Exit    3‐State Notes:  tPD_xxx = propagation delay from external signal (PWM, ZCD_EN#, etc.) to IC generated signal.   Example (tPD_PHGLL – PWM going HIGH to LS Vgs (GL) going LOW)  tD_xxx = delay from IC generated signal to IC generated signal.  Example (tD_DEADON – LS Vgs (GL) LOW to HS Vgs (GH) HIGH)                                Exiting 3‐state  PWM             tPD_TSGHH = PWM 3‐state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS  tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS    tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS              tPD_TSGLH = PWM 3‐state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS  tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (ZCD_EN# held LOW)    ZCD_EN#                              Dead Times            tD_DEADON = LS VGS fall to HS VGS rise, LS‐comp trip value (~1.7V GL) to 10% HS VGS  tPD_ZLGLL = ZCD_EN# fall to LS VGS fall, VIL_ZCD_EN to 90% LS VGS  tPD_ZHGLH = ZCD_EN# rise to LS VGS rise, VIH_ZCD_EN to 10% LS VGS            tD_DEADOFF = VSWH fall to LS VGS rise, SW‐comp trip value (~1.7V VSWH) to 10% LS VGS  Figure 29. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 PWM and 3-StateTiming Diagram www.fairchildsemi.com 13 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module HIGH, Q2 begins to turn off after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below 1.7V, Q1 begins to turn on after adaptive delay tD_DEADON. Adaptive Gate Drive Circuit The Zero Cross Detection Mode allows for higher converter efficiency when operating in light-load conditions. When ZCD_EN# is pulled LOW; the low-side MOSFET gate signal pulls LOW when internal circuitry detects positive LS MOSFET drain current, preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – known as “Diode Emulation” Mode. When the ZCD_EN# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode, which allows for gating of the low-side MOSFET. Table 2. ZCD_EN# Logic DISB# PWM ZCD_EN# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 (IL 0)(4) 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. GL = 0, when IL < 0 (Inductor current is negative and flowing in to the DrMOS VSWH node). GL = 1 when IL > 0 (Inductor current is positive and flowing out of the DrMOS VSWH node). ZCD_EN# V IH_ZCD_EN V IL_ZCD_EN V IL_ZCD_EN V IH_PWM VIH_PWM VIL_PWM PWM 90% 1.7V GH to VSWH 1 0% DCM DCM (IL = 0)  IL > 0 VOUT VSWH GL 90% 90% 1.7V tPD_PHGLL tD_DEADON 10% tPD_PLGHL tD_DEADOFF 10% Delay from  ZCD_EN#  going high to LS V GS high  Figure 30. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 tPD_ZHGLH I L