FDMF6820C

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Other names and brands may be claimed as the property of others. Benefits     Description Ultra-Compact 6x6 mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions Fully Optimized System Efficiency Clean Sw itching Waveforms w ith Minimal Ringing High-Current Handling Features                  Over 93% Peak-Efficiency High-Current Handling: 50 A High-Performance PQFN Copper-Clip Package 3-State 3.3 V PWM Input Driver Skip-Mode SMOD# (Low -Side Gate Turn Off) Input Thermal Warning Flag for Over-Temperature Condition Driver Output Disable Function (DISB# Pin) Internal Pull-Up and Pull-Dow n for SMOD# and DISB# Inputs, Respectively ® ON Semiconductor Pow erTrench Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing ON Semiconductor SyncFET™ (Integrated Schottky Diode) Technology in Low -Side MOSFET The XS™ Dr MOS family is ON Semiconductor ’s nextgeneration, fully optimized, ultra-compact, integrated MOSFET plus driver pow er stage solution for highcurrent, high-frequency, synchronous buc k DC- DC applications. The FDMF6820C integrates a driver IC, tw o pow er MOSFETs, and a bootstrap Schottky diode into a ther mally enhanced, ultra-compact 6x6 mm package. With an integrated approach, the complete sw itching pow er stage is optimized w ith regard to dr iver and MOSFET dynamic performance, system inductance, and pow er MOSFET RDS(ON) . XS™ Dr MOS uses ON ® Semiconductor's high-perfor mance Pow erTrench MOSFET technology, w hich dramatically reduces sw itch ringing, eliminating the need for snubber circuit in most buck converter applications. A driver IC w ith reduced dead times and propagation delays further enhances the performance. A thermal warning function w arns of a potential over-temperature situation. The FDMF6820C also incorporates a Skip Mode ( SMOD#) for improved light- load efficiency. The FDMF6820C also provides a 3-state 3.3 V PWM input for compatibility w ith a w ide range of PWM controllers. Applications   Integrated Bootstrap Schottky Diode Adaptive Gate Drive Timing for Shoot-Through Protection  Low -Profile SMD Package    ON Semiconductor Green Packaging and RoHS Compliance  Under-Voltage Lockout (UVLO) Optimized for Sw itching Frequencies up to 1MHz High-Performance Gaming Motherboards Compact Blade Servers, V-Core and Non-V-Core DC-DC Converters Desktop Computers, V-Core and Non-V-Core DC-DC Converters Workstations High-Current DC-DC Point-of-Load Converters Netw orking and Telecom Microprocessor Voltage Regulators Small Form-Factor Voltage Regulator Modules ® Based on the Intel 4.0 DrMOS Standard Ordering Information Part Number Current Rating FDMF6820C 50 A © 2011 Semiconductor Components Industries, LLC. October-2017, Rev.2 Package Top Mark 40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package FDMF6820C Publication Order Number: FDMF6820C/D FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module V5V VIN 3V ~ 16V RVCIN C VCIN C VDRV VDRV DISB# VCIN C VIN VIN RBOOT DISB# BOOT PWM Input PWM C BOOT FDMF6820C OFF PHASE SMOD# ON OpenDrain Output VSWH THWN# VOUT L OUT CGND Figure 1. COUT PGND Typical Application Circuit DrMOS Block Diagram VDRV VCIN VIN BOOT UVLO Q1 HS Power MOSFET DBoot DISB# GH Logic GH Lev el-Shift 10µA 30kΩ PHASE VCIN Dead-Time R UP_PWM Input 3-State Logic PWM Control VSWH VDRV R DN_PWM GL Logic THWN# VCIN GL 30kΩ Temp. Sense Q2 LS Power MOSFET 10µA CGND PGND SMOD# Figure 2. DrMOS Block Diagram www.onsemi.com 2 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Application Circuit 11 40 12 39 13 38 37 CGND VSWH VSWH 36 GL PGND PGND 35 VSWH PGND PGND 34 VSWH PGND PGND 33 VSWH PGND PGND 32 VSWH PGND PGND 31 NC VIN VIN PGND 14 PHASE PGND VIN 15 GH PGND THWN# VIN 16 CGND PGND VIN 17 BOOT PGND DISB# VIN 18 VDRV PGND VIN VSWH Bottom View CGND 41 VIN 42 VSWH 43 21 22 23 24 25 26 Figure 4. 27 28 29 30 VSWH PGND PWM VIN 19 VCIN 1 VSWH PGND 2 20 SMOD# SMOD# 3 PGND VSWH VCIN 4 PGND VSWH VDRV 21 5 PGND 22 BOOT 23 6 PGND 24 CGND Figure 3. 25 7 PGND 26 GH 27 8 PGND 28 9 VIN PGND 29 10 VIN PGND 30 PHASE VSWH 43 NC VIN 42 VIN 31 CGND 41 VIN 10 20 32 VSWH 9 19 33 VSWH 8 18 34 VSWH 7 17 35 VSWH 6 16 36 VSWH 5 15 37 GL 4 14 38 CGND 3 13 39 THWN# 2 12 40 DISB# 1 11 PWM Top View Pin Definitions Pin # 1 Name Description When SMOD#=HIGH, the low -side driver is the inverse of the PWM input. When SMOD# SMOD#=LOW, the low -side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add a noise filter capacitor. 2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND. 3 VDRV Pow er for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 7 GH For manufacturing test only. This pin must float; it must not be connected to any pin. PHASE Sw itch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Pow er input. Output stage supply voltage. 15, 29 35, 43 VSWH Sw itch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Pow er ground. Output stage ground. Source pin of the low -side MOSFET. 36 GL 38 THWN# Thermal w arning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. 39 DISB# Output disable. When LOW, this pin disables the pow er MOSFET sw itching (GH and GL are held LOW). This pin has a 10 µA internal pull-dow n current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 3.3 V PWM signal from the controller. For manufacturing test only. This pin must float; it must not be connected to any pin. www.onsemi.com 3 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Pin Configuration Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol V CIN Parameter Supply Voltage Referenced to CGND Min. Max. Unit -0.3 6.0 V V DRV Drive Voltage Referenced to CGND -0.3 6.0 V V DISB# Output Disable Referenced to CGND -0.3 6.0 V V PWM PWM Signal Input Referenced to CGND -0.3 6.0 V V SMOD# V GL V THWN# V IN V BOOT Skip Mode Input Referenced to CGND -0.3 6.0 V Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V Thermal Warning Flag Referenced to CGND -0.3 6.0 V Pow er Input Referenced to PGND, CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to CGND -0.3 25.0 V Referenced to PGND, CGND (DC Only) -0.3 25.0 V Referenced to PGND, V IH_DISB). Table 1. UVLO and Disable Logic UVLO DISB# Driver State 0 X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (see Table 2) 1 Open Disabled (GH, GL=0) Thermal Warning Flag (THWN#) The FDMF6820C provides a ther mal w arning flag (THWN#) to w arn of over-temperature conditions. The ther mal w arning flag uses an open-drain output that pulls to CGND w hen the activation temperature (150°C) is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, w hich can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State Nor mal Operation Ther mal Warning LOW TJ_driver Figure 26. The FDMF6820C incorporates a three-state 3.3 V PWM input gate drive design. The three-state gate dr ive has both logic HIGH level and LOW level, along w ith a three-state shutdow n window . When the PWM input signal enters and remains w ithin the three-state w indow for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This enables the gate drive to shut dow n both high-side and low-side MOSFETs to support features such as phase shedding, w hich is common on multi-phase voltage regulators. Exiting Three-State Condition When exiting a valid three-state condition, the FDMF6820C follow s the PWM input command. If the PWM input goes from three-state to LOW, the low -side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 27. The FDMF6820C design allows for short propagation delays w hen exiting the three-state w indow (see Electrical Characteristics). Low-Side Driver Note: 3. DISB# internal pull-dow n current source is 10 µA. 135°C Reset 150°C Activation Temperature Temperature Three-State PWM Input The low -side driver (GL) is designed to drive a groundreferenced, low-RDS(ON) , N-channel MOSFET. The bias for GL is internally connected betw een the VDRV and CGND pins. When the dr iver is enabled, the driver's output is 180° out of phase w ith the PWM input. When the driver is disabled (DISB#=0 V), GL is held LOW. High-Side Driver The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, V SWH is held at PGND, allow ing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, V SWH rises to V IN, forcing the BOOT pin to V IN + V BOOT, which provides suffic ient V GS enhancement for Q1. To complete the sw itching cycle, Q1 is turned off by pulling GH to V SWH. CBOOT is then recharged to V DRV w hen V SWH falls to PGND. GH output is in-phase w ith the PWM input. The high-side gate is held LOW w hen the driver is disabled or the PWM signal is held w ithin the three-state w indow for longer than the three-state hold-off time, tD_HOLD-OFF. IC THWN Operation www.onsemi.com 12 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Functional Description The driver IC advanced design ensures minimum MOSFET dead-time, w hile eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 27 provides the relevant timing w aveforms. To prevent overlap dur ing the LOW-to-HIGH sw itching transition (Q2 off to Q1 on), the adaptive c ircuitry monitors the voltage at the GL pin. When the PWM signal goes V IH_PWM tD_HOLD-OFF V IH_PWM HIGH, Q2 begins to turn off after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below 1.0 V, Q1 begins to turn on after adaptive delay tD_DEADON. To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive c ircuitry monitors the voltage at the GH-to- PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (tPD_PLGHL). Once the voltage across GH-to- PHASE falls below 2.2 V, Q2 begins to turn on after adaptive delay tD_DEADOFF. V TRI_HI VIH_PWM V IH_PWM V TRI_HI VTRI_LO V IL_PWM V IL_PWM tR_GH PWM t F_GH 90% GH to VSWH 10% V IN CCM DCM DCM VOUT 2.2V VSWH tR_GL GL tF_GL 90% 90% 1.0V tPD_PHGLL t D_DEADON 10% 10% tPD_PLGHL t PD_TSGHH t D_DEADOFF Enter 3- state Exit 3- state t D_HOLD-OFF Enter 3-state t PD_TSGHH Exit 3- state t D_HOLD-OFF t PD_TSGLH Enter 3 -state Exit 3-state Notes: tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS V GS (GL) going LOW) tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS V GS (GL) LOW to HS VGS (GH) HIGH) PWM tPD_PHGLL = PWM rise to LS VGS fall, V IH_PWM to 90% LS V GS tPD_PLGHL = PWM fall to HS VGS fall, V IL_PWM to 90% HS VGS tPD_PHGHH = PWM rise to HS VGS rise, V IH_PWM to 10% HS VGS (SMOD# held LOW) Exiting 3-state tPD_TSGHH = PWM 3-state to HIGH to HS V GS rise, VIH_PWM to 10% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, V IL_PWM to 10% LS V GS SMOD# tPD_SLGLL = SMOD# fall to LS V GS fall, VIL_SMOD to 90% LS V GS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS Dead Times tD_DEADON = LS V GS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 27. PWM and 3-StateTim ing Diagram www.onsemi.com 13 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Adaptive Gate Drive Circuit The Skip Mode function allow s for higher converter efficiency w hen operated in light-load conditions. When SMOD# is pulled LOW, the low -side MOSFET gate signal is disabled (held LOW), preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – know n as “Diode Emulation” Mode. Table 2. SMOD# Logic DISB# PWM SMOD# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side FET V GS response time to control diode emulation on a cycle-by-cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IH_PWM V IL_PWM PWM 90% GH to VSWH 10% 1 0% CCM 2.2V DCM CCM V OUT VSWH GL 90% 1.0V t PD_PHGLL t D_DEADON 1 0% 10% tPD_PLGHL tPD_SLGLL tD_DEADOFF tPD_PHGHH Delay from SMOD# going LOW to LS VGS LOW HS turn - on with SMOD# LOW Figure 28. SMOD# Tim ing Diagram www.onsemi.com 14 tPD_SHGLH Delay from SMOD# going HIGH to LS V GS HIGH FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module When the SMOD# pin is pulled HIGH, the synchronous buck converter w orks in Synchronous Mode. This mode allows for gating on the Low Side MOSFET. When the SMOD# pin is pulled LOW, the low -side MOSFET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD# w hen the controller detects light-load condition from output current sens ing. Nor mally this pin is active LOW. See Figure 28 for timing delays. Skip Mode (SMOD#) VCIN Filter Supply Capacitor Selection The V DRV pin provides pow er to the gate drive of the high-side and low -side pow er MOSFET. In most cases, it can be connected directly to V CIN, the pin that provides pow er to the logic section of the driver. For additional noise immunity, an RC filter can be inserted betw een the VDRV and V CIN pins. Recommended values w ould be 10 Ω and 1 µF. For the supply inputs (V CIN), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1 µF X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane w ith vias. Bootstrap Circuit Power Loss and Efficiency The bootstrap circuit uses a charge storage capacitor (CBOOT), as show n in Figure 30. A bootstrap capacitance of 100 nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific applications to improve sw itching noise immunity. The boot resistor may be required w hen operating above 15 V IN and is effective at controlling the high-side MOSFET turn-on s lew rate and V SHW overshoot. RBOOT values from 0.5 to 3.0 Ω are typically effective in reducing VSWH overshoot. V5V A Refer to Figure 30 for pow er loss testing method. Pow er loss calculations are: (1) PSW=V SW x IOUT (W) (2) POUT=V OUT x IOUT (W) (3) PLOSS_MODULE=PIN - PSW (W) (4) PLOSS_BOARD=PIN - POUT (W) (5) EFFMODULE=100 x PSW/PIN (%) (6) EFFBOARD=100 x POUT/PIN (%) (7) A VDRV VCIN VIN I IN C VCIN C VDRV C VIN VIN DISB# PWM Input PIN=(V IN x IIN) + (V 5V x I5V) (W) R VCIN I5V DISB# Measurement and Calculation RBOOT BOOT PWM FDMF6820C CBOOT OFF IOUT VSWH SMOD# ON A OpenDrain Output A V VSW PGND Block Diagram With V CIN Filter A R VCIN I5V VDRV DISB# PWM Input PWM VCIN VIN I IN CVCIN C VDRV DISB# C VIN VIN RBOOT BOOT FDMF6820C OFF CBOOT IOUT VSWH ON OpenDrain Output V OUT VOUT COUT CGND Figure 29. V5V L OUT PHASE THWN# SMOD# A L OUT PHASE COUT THWN# CGND Figure 30. PGND V VSW Pow er Loss Measurem ent www.onsemi.com 15 VOUT FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Application Information Figure 31 and Figure 32 provide an example of a proper layout for the FDMF6820C and critical components. All of the high-current paths, such as V IN, VSWH, VOUT, and GND copper, should be short and w ide for low inductance and resistance. This aids in achieving a more stable and evenly distributed current flow , along w ith enhanced heat radiation and system performance. Recommendations for PCB Designers 1. Input ceramic bypass capacitors must be placed close to the V IN and PGND pins. This helps reduce the high-current pow er loop inductance and the input current ripple induced by the pow er MOSFET sw itching operation. 2. The V SWH copper trace serves tw o purposes. In addition to being the high-frequency current path from the Dr MOS package to the output inductor, it serves as a heat sink for the low -side MOSFET in the Dr MOS package. The trace should be short and w ide enough to present a low -impedance path for the high-frequency, high-current flow betw een the Dr MOS and inductor. The short and w ide trace minimizes electrical losses as w ell as the Dr MOS temperature rise. Note that the V SWH node is a highvoltage and high-frequency sw itching node w ith high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the low er MOSFET, balance using the largest area possible to improve Dr MOS cooling w hile maintaining acceptable noise emission. 3. An output inductor should be located close to the FDMF6820C to minimize the pow er loss due to the V SWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. ® 4. Pow erTrench MOSFETs are used in the output stage and are effective at minimizing ringing due to fast sw itching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The selected resistor and capacitor need to be the proper size for pow er dissipation. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the V CIN-to- CGND, VDRV-to-CGND, and BOOT-to- PHA SE pin pairs to ensure clean and stable pow er. Routing w idth and length should be considered as w ell. 6. Inc lude a trace from the PHASE pin to the VSWH pin to improve noise margin. Keep this trace as short as possible. noise issues due to ground bounce or high positive and negative V SWH ringing. Inserting a boot resistance low ers the Dr MOS efficiency. Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5 Ω to 3.0 Ω are typically effective in reducing V SWH overshoot. 8. The V IN and PGND pins handle large current transients w ith frequency components greater than 100 MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of ther mal relief traces in series w ith these pins is discouraged s ince this adds inductance to the pow er path. This added inductance in series w ith either the V IN or PGND pin degrades system noise immunity by increasing pos itive and negative V SWH ringing. 9. GND pad and PGND pins should be connected to the GND copper plane w ith multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level betw een CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs. 10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode. 11. The SMOD# and DISB# pins have w eak internal pull-up and pull-dow n current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary. 12. Use multiple vias on the V IN and VOUT copper areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. Do not put many vias on the VSWH copper to avoid extra parasitic inductance and noise on the sw itching w aveform. As long as efficiency and ther mal perfor mance are acceptable, place only one VSWH copper on the top layer and use no vias on the VSWH copper to minimize sw itch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Cr itical highfrequency components, such as RBOOT, CBOOT, RC snubber, and bypass capacitors; should be located as close to the respective Dr MOS module pins as possible on the top layer of the PCB. If this is not feasible, they can be connected from the backside through a netw ork of low -inductance vias. 7. The layout should include the option to insert a small-value series boot resistor betw een the boot capacitor and BOOT pin. The boot-loop size, including RBOOT and CBOOT, should be as s mall as possible. The boot resistor may be required w hen operating above 15 V IN and is effective at controlling the high-side MOSFET turn-on slew rate and V SHW overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have www.onsemi.com 16 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines Figure 32. PCB Layout Exam ple (Top View ) PCB Layout Exam ple (Bottom View ) www.onsemi.com 17 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Figure 31. B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 0.40 2.50 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.40±0.10 (2.20) 0.10 C A B 0.05 C 0.30 30 0.20 (40X) 31 20 0.50 2.40±0.10 (0.70) 1.50±0.10 11 10 0.40 2.00±0.10 (0.20) 40 0.50 (40X) 0.30 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) 1.10 0.90 0.10 C 0.30 0.20 PIN #1 INDICATOR 0.20 MAY APPEAR AS OPTIONAL 1 BOTTOM VIEW 0.08 C 2.10 LAND PATTERN RECOMMENDATION 0.05 0.00 DETAIL 'A' C A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV3 SEATING PLANE SCALE: 2:1 Figure 33. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 m m Package Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. www.onsemi.com 18 FDMF6820C — Extra-Small, High-Performance, High-Frequency DrMOS Module Physical Dimensions PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. 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