Motion SPM) 5 Series
FSB50550BL, FSB50550BSL
General Description
The FSB50550BL/FSB50550BSL is an advanced Motion SPM 5
module providing a fully−featured, high−performance inverter output
stage for AC Induction, BLDC and PMSM motors. These modules
integrate optimized gate drive of the built−in MOSFETs (FRFET®
technology) to minimize EMI and losses, while also
providing multiple on−module protection features including
under−voltage lockouts and thermal monitoring. The built−in
high−speed HVIC requires only a single supply voltage and translates
the incoming logic−level gate inputs to the high−voltage, high−current
drive signals required to properly drive the module’s internal
MOSFETs. Separate open−source MOSFET terminals are available
for each phase to support the widest variety of control algorithms.
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SPM5E−023/23LD
CASE MODEJ
Features
• UL Certified No. E209204 (UL1557)
• Optimized for over 10 kHz Switching Frequency
• 500 V FRFET MOSFET 3−Phase Inverter with Gate Drivers and
Protection
• Built−In Bootstrap Diodes Simplify PCB Layout
• Separate Open−Source Pins from Low−Side MOSFETs for
Three−Phase Current−Sensing
• Active−HIGH Interface, Works with 3.3/5 V Logic,
•
•
•
•
•
•
Schmitt−Trigger Input
Optimized for Low Electromagnetic Interference
HVIC Temperature−Sensing Built−In for Temperature Monitoring
HVIC for Gate Driving and Under−Voltage Protection
Isolation Rating: 1500 Vrms/min.
Moisture Sensitive Level (MSL) 3 for SMD PKG
This Device is Pb−Free and is RoHS Compliant
SPM5H−023/23LD
CASE MODEM
MARKING DIAGRAM
ON
Applications
FSB50550XX
ZKKXYY
• 3−Phase Inverter Driver for Small Power AC Motor Drives
Related Source
•
5 Series Version 2 User’s Guide
• AN−9082 − Motion SPM® 5 Series Thermal Performance by Contact
AN−9080 − Motion SPM®
Pressure
FSB50550XX
XX
Z
KK
XYY
= Specific Device Code
= BL for FSB50550BL
= BSL for FSB50550BSL
= Assembly Code
= Lot Run Traceability Code
= Date Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
November, 2019 − Rev. 0
1
Publication Order Number:
FSB50550BL/D
FSB50550BL, FSB50550BSL
ORDERING INFORMATION
Device
Device Marking
Packing Type†
Package
Reel Size
Quantity
FSB50550BL
FSB50550BL
SPM5E−023
Rail
NA
15
FSB50550BSL
FSB50550BSL
SPM5H−023
Tape & Reel
330 mm
450
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Rating
Unit
500
V
INVERTER PART (Each MOSFET Unless Otherwise Specified)
VDSS
Drain−Source Voltage of Each MOSFET
*ID 25
Each MOSFET Drain Current, Continuous
TC = 25°C
3.0
A
*ID 80
Each MOSFET Drain Current, Continuous
TC = 80°C
1.9
A
*IDP
Each MOSFET Drain Current, Peak
TC = 25°C, PW < 100 ms
7.0
A
Each FRFET Drain Current, Rms
TC = 80°C, FPWM < 20 kHz
1.3
Arms
*IDRMS
CONTROL PART (Each HVIC Unless Otherwise Specified)
VDD
Control Supply Voltage
Applied between VDD and COM
20
V
VBS
High−Side Bias Voltage
Applied between VB and VS
20
V
VIN
Input Signal Voltage
Applied between VIN and COM
−0.3~VDD + 0.3
V
500
V
BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified)
VRRMB
Maximum Repetitive Reverse Voltage
* IFB
Forward Current
TC = 25°C
0.5
A
* IFPB
Forward Current (Peak)
TC = 25°C, Under 1 ms Pulse Width
2.0
A
Inverter MOSFET Part (Per Module)
2.2
°C/W
Operating Junction Temperature
−40~150
°C
TSTG
Storage Temperature
−40~125
°C
VISO
Isolation Voltage
1500
Vrms
THERMAL RESISTANCE
Rth(j−c)Q
Junction to Case Thermal Resistance
(Note 1)
TOTAL SYSTEM
TJ
60 Hz, Sinusoidal, 1 minute,
Connect Pins to Heat Sink Plate
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
NOTES:
1. For the measurement point of case temperature TC, Please refer to Figure 4.
2. Marking “*” is calculation value or design factor.
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2
FSB50550BL, FSB50550BSL
PIN DESCRIPTIONS
Pin No.
Pin Name
Pin Description
1
COM
IC Common Supply Ground
2
VB(U)
Bias Voltage for U−Phase High−Side MOSFET Driving
3
VDD(U)
Bias Voltage for U−Phase IC and Low−Side MOSFET Driving
4
IN(UH)
Signal Input for U−Phase High−Side
5
IN(UL)
Signal Input for U−Phase Low−Side
6
N.C
No Connection
7
VB(V)
Bias Voltage for V−Phase High Side MOSFET Driving
8
VDD(V)
Bias Voltage for V−Phase IC and Low Side MOSFET Driving
9
IN(VH)
Signal Input for V−Phase High−Side
10
IN(VL)
Signal Input for V−Phase Low−Side
11
VTS
12
VB(W)
13
VDD(W)
Bias Voltage for W−Phase IC and Low−Side MOSFET Driving
14
IN(WH)
Signal Input for W−Phase High−Side
15
IN(WL)
Signal Input for W−Phase Low−Side
16
N.C
17
P
18
U, VS(U)
19
NU
Negative DC−Link Input for U−Phase
20
NV
Negative DC−Link Input for V−Phase
21
V, VS(V)
22
NW
23
W, VS(W)
Output for HVIC Temperature Sensing
Bias Voltage for W−Phase High−Side MOSFET Driving
No Connection
Positive DC−Link Input
Output for U−Phase & Bias Voltage Ground for High−Side MOSFET Driving
Output for V−Phase & Bias Voltage Ground for High−Side MOSFET Driving
Negative DC−Link Input for W−Phase
Output for W Phase & Bias Voltage Ground for High−Side MOSFET Driving
(1) COM
(17) P
(2) VB(U)
(3) VDD(U)
VDD
(4) IN (UH)
HIN
(5) IN (UL)
LIN
VS
COM
LO
(18) U, VS(U)
(6) N.C
(19) NU
(7) VB(V)
(8) VDD(V)
VDD
(9) IN (VH)
HIN
(10) IN(VL)
LIN
(11) V TS
(20) N V
VB
(21) V, VS(V)
COM
V TS
(12) VB(W)
(13) VDD(W)
VDD
(14) IN(WH)
HIN
(15) IN(WL)
LIN
COM
VB
(22) NW
(23) W, VS(W)
LO
(16) N.C
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
NOTE:
3. Source terminal of each low−side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM 5 product. External
connections should be made as indicated in Figure 3.
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3
FSB50550BL, FSB50550BSL
ELECTRICAL CHARACTERISTICS (TJ = 25°C, VDD = VBS = 15 V Unless Otherwise Specified.)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
500
−
−
V
INVERTER PART (Each MOSFET Unless Otherwise Specified)
Drain−Source Breakdown Voltage
VIN = 0 V, ID = 1 mA (Note 4)
Zero Gate Voltage Drain Current
VIN = 0 V, VDS = 500 V
−
−
1
mA
Static Drain−Source Turn−On
Resistance
VDD = VBS = 15 V, VIN = 5 V, ID = 1.0 A
−
2.3
3.0
W
VSD
Drain−Source Diode Forward Voltage
VDD = VBS = 15 V, VIN = 0 V, ID = −1.0 A
−
−
1.3
V
tON
Switching Times
VPN = 300 V, VDD = VBS = 15 V, ID = 1.0 A
VIN = 0 V ↔ 5 V, Inductive Load L = 3 mH
High− and Low−Side MOSFET Switching
(Note 5)
−
650
−
ns
−
950
−
ns
−
150
−
ns
EON
−
40
−
mJ
EOFF
−
5
−
mJ
BVDSS
IDSS
RDS(on)
tOFF
trr
RBSOA
Reverse Bias Safe Operating Area
VPN = 400 V, VDD = VBS = 15 V, ID = (TBD),
VDS = BVDSS, TJ = 150°C
High− and Low−Side MOSFET Switching (Note 6)
Full Square
CONTROL PART (Each HVIC Unless Otherwise Specified)
IQDD
Quiescent VDD Current
VDD = 15 V, VIN = 0 V Applied between VDD and
COM
−
−
200
mA
IQBS
Quiescent VBS Current
VBS = 15 V, VIN = 0 V Applied between VB(U) − U,
VB(V) − V, VB(W) − W
−
−
100
mA
IPDD
Operating VDD Supply Current
VDD − COM
VDD = 15 V, fPWM = 20 kHz,
duty = 50%, Applied to One
PWM Signal Input for
Low−Side
−
−
900
mA
IPBS
Operating VBS Supply Current
VB(U) − VS(U),
VB(V) − VS(V),
VB(W) − VS(W)
VDD = VBS = 15 V,
fPWM = 20 kHz,
Duty = 50%, Applied to
One PWM Signal Input
for High−Side
−
−
800
mA
Low−Side Under−Voltage Protection
(Figure 8)
VDD Under−Voltage Protection Detection Level
7.4
8.0
9.4
V
VDD Under−Voltage Protection Reset Level
8.0
8.9
9.8
V
High−Side Under−Voltage Protection
(Figure 9)
VBS Under−Voltage Protection Detection Level
7.4
8.0
9.4
V
VBS Under−Voltage Protection Reset Level
8.0
8.9
9.8
V
VTS
HVIC Temperature Sensing Voltage
Output
VDD = 15 V, THVIC = 25°C (Note 7)
600
790
980
mV
VIH
ON Threshold Voltage
Logic HIGH Level
−
−
2.9
V
VIL
OFF Threshold Voltage
Logic LOW Level
0.8
−
−
V
UVDDD
UVDDR
UVBSD
UVBSR
Applied between VIN and
COM
BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified)
VFB
Forward Voltage
IF = 0.1 A, TC = 25°C (Note 8)
−
2.5
−
V
trrB
Reverse Recovery Time
IF = 0.1 A, TC = 25°C
−
80
−
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
FSB50550BL, FSB50550BSL
RECOMMENDED OPERATING CONDITION
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
−
300
400
V
VPN
Supply Voltage
Applied between P and N
VDD
Control Supply Voltage
Applied between VDD and COM
13.5
15.0
16.5
V
VBS
High−Side Bias Voltage
Applied between VB and VS
13.5
15.0
16.5
V
VIN(ON)
Input ON Threshold Voltage
Applied between VIN and COM
3.0
−
VDD
V
VIN(OFF)
Input OFF Threshold Voltage
0
−
0.6
V
1.0
−
−
ms
−
15
−
kHz
tdead
Blanking Time for Preventing Arm−Short
VDD = VBS = 13.5~16.5 V, TJ ≤ 150°C
fPWM
PWM Switching Frequency
TJ ≤ 150°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Built in Bootstrap Diode VF−IF Characteristic
1.0
0.9
0.8
IF [A]
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1
2
3
4
5
6
7
8
9
VF [V]
10
11
12
13
14
15
TC = 255C
Figure 2. Built−in Bootstrap Diode Characteristics (Typical)
NOTES:
4. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM 5 product. VPN should
be sufficiently less than this value considering the effect of the stray inductance so that VPN should not exceed BVDSS in any case.
5. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can
be different according to the field applications due to the effect of different printed circuit boards and wirings. Please see Figure 6 for the
switching time definition with the switching test circuit of Figure 7.
6. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating Area (SOA). Please
see Figure 7 for the RBSOA test circuit that is same as the switching test circuit.
7. Vts is only for sensing−temperature of module and cannot shutdown MOSFETs automatically.
8. Built in bootstrap diode includes around 15 W resistance characteristic. Please refer to Figure 2.
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5
FSB50550BL, FSB50550BSL
These values depend on PWM control algorithm
C1
+15 V
* Example Circuit: V phase
VDC
P
MCU
R5
C5
VDD
VB
HIN
HO
LIN
VS
COM
LO
V
VTS
10 mF
C2
C4
N
HIN
LIN
Output
Note
Inverter
Output
0
0
Z
Both FRFET Off
0
1
0
Low side FRFET On
C3
1
0
VDC
High side FRFET On
1
1
Forbidden
Shoot through
Open
Open
Z
Same as (0,0)
R3
One Leg Diagram of Motion SPM 5 Product
* Example of Bootstrap Parameters
:
C1 = C2 = 1 mF Ceramic Capacitor
Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters
NOTES:
9. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of
parameters is shown above.
10. RC−coupling (R5 and C5) and C4 at each input of Motion SPM 5 products and MCU (Indicated as Dotted Lines) may be used to prevent
improper signal due to surge−noise.
11. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge−voltage.
Bypass capacitors such as C1, C2 and C3 should have good high−frequency characteristics to absorb high−frequency ripple−current.
Figure 4. Case Temperature Measurement
NOTE:
12. Attach the thermocouple on top of the heat−sink of SPM 5 package (between SPM 5 package and heatsink if applied) to get the correct
temperature measurement.
3.5
3.0
VTS [V]
2.5
2.0
1.5
1.0
0.5
20
40
60
80
100
120
140
THVIC [°C]
Figure 5. Temperature Profile of VTS (Typical)
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6
160
FSB50550BL, FSB50550BSL
VIN
VDS
VIN
Irr
120% of ID
100% of ID
ID
10% of ID
VDS
ID
tON
trr
tOFF
(a) Turn−on
(b) Turn−off
Figure 6. Switching Time Definitions
CBS
VDD
ID
VCC
VB
HIN
HO
LIN
VS
COM
LO
L
VDC
+
VDS
−
VTS
One Leg Diagram of Motion SPM 5 Product
Figure 7. Switching and RBSOA (Single−Pulse) Test Circuit (Low−Side)
Input Signal
UV Protection
Status
Low−Side Supply, VDD
RESET
RESET
SET
UVDDR
UVDDD
MOSFET Current
Figure 8. Under−Voltage Protection (Low−Side)
Input Signal
UV Protection
Status
High−Side Supply, VBS
RESET
SET
UVBSR
UVBSD
MOSFET Current
Figure 9. Under−Voltage Protection (High−Side)
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7
RESET
FSB50550BL, FSB50550BSL
C1
(1) COM
(2) VB(U)
(17) P
(3) VDD(U)
R5
(4) IN(UH)
(5) IN(UL)
C5
C2
(6) N.C
VDD
VB
HIN
HO
LIN
VS
COM
LO
(18) U, VS(U)
(19) NU
(7) VB(V)
(8) VDD(V)
(9) IN(VH)
Micom
(10) IN(VL)
(11) VTS
(13) VDD(W)
(14) IN(WH)
(15) IN(WL)
C4
VDD
VB
HIN
HO
LIN
VS
COM
LO
(20) NV
(21) V, VS(V)
M
VTS
(12) VB(W)
(16) N.C
C3 VDC
VDD
VB
HIN
HO
LIN
VS
COM
LO
(22) NW
(23) W, VS(W)
For current−sensing and protection
15 V
Supply
C6
R4
R3
Figure 10. Example of Application Circuit
NOTES:
13. About pin position, refer to Figure 1.
14. RC−coupling (R5 and C5, R4 and C6) and C4 at each input of Motion SPM 5 product and MCU are useful to prevent improper input signal
caused by surge−noise.
15. The voltage−drop across R3 affects the low−side switching performance and the bootstrap characteristics since it is placed between COM
and the source terminal of the low−side MOSFET. For this reason, the voltage drop across R3 should be less than 1 V in the steady−state.
16. Ground−wires and output terminals, should be thick and short in order to avoid surge−voltage and malfunction of HVIC.
17. All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for rejecting
high−frequency ripple current.
SPM and FRFET are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE
CASE MODEJ
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13543G
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE
CASE MODEM
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13546G
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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