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FSL518H, FSL538H,
FSL518A, FSL538A
High Performance Switcher
Integrated with HV Startup
and SENSEFET)
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The FSL5x8 is an integrated peak-current-mode controlled pulse
width modulation (PWM) power switch, specifically designed for
off-line switch-mode power supplies. The PWM controller includes an
advanced soft-start, frequency hopping, optimized gate driver, internal
transconductance amplifier, temperature-compensated precise current
source for loop compensation and enhanced self-protections as well.
Compared to a discrete MOSFET and PWM controller solution, the
FSL5x8 allows to reduce total cost, component count, size, and
weight, while simultaneously increasing efficiency, productivity, and
system reliability. This device provides a basic platform for
cost-effective design of both isolated and non-isolated Flyback
converters.
PDIP−7
CASE 626A
MARKING DIAGRAM
Features
ON AYWWL
• Integrated Rugged 800 V Super-Junction MOSFET with SENSEFET
•
•
•
•
•
•
•
•
•
•
•
•
Technology
Built-in HV Current Source for Start-up
Peak-current-mode Control with Slope Compensation
AC Line Compensation for Accurate Over Power Protection
Advanced Soft-start for Low Electrical Stress
Pulse-by-pulse Current Limit
FSL5x8A: 100 kHz and FSL5x8H: 130 kHz
Line Brown-in, Brown-out Function
Line Over-voltage Protection (LOVP)
Adjustable Burst−mode Operation
Frequency Hopping for Low EMI
All Protections are Auto-Recovery: Brown-out, OLP, OVP, AOCP
and TSD
These Devices are Pb-Free, Halogen Free/BFR Free and RoHS
Compliant
Typical Applications
L5x8y
A
Y
W
WL
L5x8
x
y
= Plant Code
= 1−digit Year Code
= 1−digit Week Code
= 2−digit Die−Run Code
= Specific Device Code
= Device Option (1 or 3)
= Frequency Option (A or H)
PIN CONNECTIONS
GND 1
8 DRAIN
VCC 2
7 DRAIN
FB 3
• Power Supplies for White Goods
• Industrial Auxiliary Power Supply, E-metering SMPS
• Consumer Electronics (Chargers, Set-top-boxes and TVs)
COMP 4
5 LINE
ORDERING INFORMATION
See detailed ordering and shipping information on page 25 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
July, 2019 − Rev. 2
1
Publication Order Number:
FSL538HR/D
FSL518H, FSL538H, FSL518A, FSL538A
PRODUCT INFORMATION & INDICATIVE RECOMMENDED OUTPUT POWER
Output Power Table (Open Frame) (Notes 1, 2)
Part
Number
Package
Operating
Junction
Temperature
FSL518H
PDIP−7
−40 ~ 125°C
130 kHz
0.46
8.0
15 W
12 W
FSL538H
PDIP−7
−40 ~ 125°C
130 kHz
0.66
4.6
21 W
17 W
FSL518A
PDIP−7
−40 ~ 125°C
100 kHz
0.61
8.0
17 W
14 W
FSL538A
PDIP−7
−40 ~ 125°C
100 kHz
0.86
4.6
25 W
20 W
Operation
Frequency
Current Limit (A)
Max. RDS(ON) (W)
230 VAC +
15%
85 ~ 265
VAC
1. The junction temperature can limit the maximum output power.
2. Maximum practical continuous power in an open-frame design at 50°C ambient.
Vo
AC
IN
LINE
DRAIN
FB
PWM
GND
VCC
COMP
(a) Isolated Opto−coupler Feedback (Enable Line Detection)
Vo
AC
IN
LINE
COMP
PWM
VCC
DRAIN
GND
FB
(b) Non−isolated Direct Feedback (Disable Line Detection)
Figure 1. Application Schematic − Isolated or Non-isolated Flyback Converter
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2
FSL518H, FSL538H, FSL518A, FSL538A
LINE
Brown−out
Initial Setting and
Line Detection
V BURH/L
DRAIN
VCC
VCC good
VCC Supply
VCC− START/ STOP
HV Current
Source
LOVP
V COMP
Frequency
Reduction
OSC
VLIMIT
Soft
Start
E/A
FB
PWM
3R
VREF
R
S
Q
R
Q
Gate Driver
LEB
S
Slope
Compensation
COMP
Brown − out
VOLP
tBO
Protection
tD− OLP
TSD
VCC
AOCP
Logic
VCC good
RSENSE
VAOCP
S
Q
R
Q
VCC−OVP
GND
Figure 2. Internal Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Pin Function
Description
1
GND
Ground
SENSEFET source terminal and internal controller ground.
2
VCC
Power Supply
This pin is connected to an external capacitor and provides internal operating current of
the IC. It also includes an auto-recovery over-voltage protection.
3
FB
Feedback
This pin is connected to the input of transconductance amplifier for regulating output voltage of the power converter. If transconductance amplifier is not used, connect FB to
GND.
4
COMP
Feedback-Loop
Compensation
Control-loop compensation. For opto-coupler feedback, connect COMP to opto coupler
directly.
5
LINE
7,8
DRAIN
Brown in/out, LOVP, For line detection(Line OVP, Brown in/out), this pin needs to be connected to the highBurst-mode Setting voltage DC link through voltage divider. And it’s also multiple-function pin for burst−mode
adjustment.
MOSFET Drain
High-voltage power MOSFET drain connection. In addition, during startup and protection
mode, the internal high-voltage current source supplies internal bias current and charges
the external capacitor connected to the VCC pin.
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3
FSL518H, FSL538H, FSL518A, FSL538A
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
DRAIN Pin Voltage
VDS
−0.3 to 800
V
VCC Pin Voltage
VCC
−0.3 to 26
V
Feedback Pin Voltage
VFB
−0.3 to 5.0
V
Compensation Pin Voltage
VCOMP
−0.3 to 5.0
V
Line-detection Pin Voltage
VLINE
−0.3 to VCC
V
DRAIN Pin Pulsed Current (Note 3)
FSL518H/A
FSL538H/A
ID-PULSE
A
2.1
2.8
Single Pulse Avalanche Energy (Note 4)
FSL518H/A
FSL538H/A
EAS
Total Power Dissipation (PDIP−7)
FSL518H/A & FSL538H/A
PD
Junction Temperature (Note 5)
TJ
150
°C
TJ
−40 to +125
°C
TSTG
−55 to +150
°C
ESD Capability HBM, JESD22−A114
ESD Capability HBM, JESD22−A114 (Except DRAIN pin)
1000
2000
V
ESD Capability CDM, JESD22−C101
1000
V
Operating Junction Temperature (Note 6)
Storage Temperature
mJ
6.0
11.7
W
1.25
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty and junction temperature.
4. L= 45 mH, starting TJ = 25°C.
5. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics
6. Junction temperature can limit maximum output power of power converter controlled by the device.
THERMAL CHARACTERISTICS
Rating
Symbol
Thermal Characteristics, PDIP−7
Thermal Resistance, Junction-to-Air (Note 7)
FSL518H/A & FSL538H/A
Thermal Reference, Junction-to-Lead (Note 7)
FSL518H/A & FSL538H/A
Value
Unit
°C/W
RqJA
100
RyJL
18
7. JEDEC recommended environment, JESD51−2, and test board, JESD51−3, with minimum land pattern.
ELECTRICAL CHARACTERISTICS
TJ = −40 to +125°C and VCC = 14 V unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
428
560
614
790
460
610
660
860
492
660
706
930
6.3
3.8
8.0
4.6
Unit
SENSEFET Section
MOSFET Peak Current Limit
TJ = 25°C, Duty = 60%
di/dt = 100 mA/ms
di/dt = 100 mA/ms
di/dt = 143 mA/ms
di/dt = 143 mA/ms
Drain-to-Source On-State Resistance
MOSFET ON, TJ = 25°C
FSL518H/A, IDRAIN = 0.46 A
FSL538H/A, IDRAIN = 0.66 A
Output Capacitance (Note 9)
VDS = 480 V, VGS = 0 V, f = 1 MHz,
TJ = 25°C
FSL518H/A
FSL538H/A
FSL518H
FSL518A
FSL538H
FSL538A
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4
ILIM
RDS(ON)
COSS
mA
Ω
pF
3.8
5.0
FSL518H, FSL538H, FSL518A, FSL538A
ELECTRICAL CHARACTERISTICS (continued)
TJ = −40 to +125°C and VCC = 14 V unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
SENSEFET Section
Effective Output Capacitance (Note 9)
VDS = 0 to 480 V, VGS = 0 V, TJ = 25°C
FSL518H/A
FSL538H/A
COSS(eff)
DRAIN Voltage Rise Time (Note 8)
VDRAIN = 40 V to 360 V
FSL518H/A, IDRAIN = 0.4 A
FSL538H/A, IDRAIN = 0.6 A
tr
DRAIN Voltage Fall Time (Note 8)
VDRAIN = 360 V to 40 V
FSL518H/A, IDRAIN = 0.4 A
FSL538H/A, IDRAIN = 0.6 A
tf
Drain to Source Breakdown Voltage
VGS = 0 V, ID = 250 mA, TJ = 25°C
Zero Gate Voltage Drain Current
VDS = 800 V, VGS = 0 V, TJ = 25°C
VDS = 640 V, VGS = 0 V, TJ = 125°C
BVDSS
pF
31
40
ns
26
35
ns
34
30
800
V
IDSS
25
250
mA
VCC Section
Controller Turn-on Threshold Voltage
VCC-START
15
16
17
V
Under-voltage Lockout Threshold
Voltage
VCC-STOP
7
8
9
V
VCC-HVREG
9
10
11
V
VCC Regulation Voltage
During Protection, TJ = 25°C
Restart Time in Protection Mode (Note 9)
tAR
Soft-start Time
tSS
800
ms
7
10
13
122
94
130
100
138
106
±5
±10
ms
Oscillation Section
Switching Frequency
VCC = 14 V, VCOMP = 3.6 V, TJ = 25°C
FSL5x8H
FSL5x8A
fS
Switching Frequency Variation
TJ = −40 ~ 125°C
ΔfS
Frequency Modulation Range
VCOMP = 3.6 V
FSL5x8H
FSL5x8A
fM
Frequency Modulation Period (Note 9)
VCOMP = 3.6 V
Green-mode Entry Frequency
VCOMP = 1.4 V
FSL5x8H
FSL5x8A
fN
Green-mode Ending Frequency
VBURL = 0.4 V
fG
3.2
ms
kHz
115
89
22
%
kHz
±6.2
±4.8
TFM
kHz
25
28
kHz
Frequency-limiting Voltage
VCOMP-S
VOLP
V
Green-mode Entry COMP Voltage (Note 9)
VCOMP-N
1.4
V
Green-mode Ending COMP Voltage
VCOMP-G
VBURL
V
Burst-Mode Section
0.35
0.45
0.55
0.4
0.5
0.6
0.45
0.55
0.65
V
COMP Threshold Voltage for Entering
Burst−mode when Line Detection is
Enabled
VLINE in VLINE-SET0 during tSET
VLINE in VLINE-SET1 during tSET
VLINE in VLINE-SET2 during tSET
VBURL
COMP Threshold Voltage for Entering
Burst−mode when Line Detection is
Disabled
0.9 V < VLINE < 1.2 V
1.2 V < VLINE < 3.6 V
VBURL
0.4
AV-BURST × VLINE
V
VBURH
VBURL + 0.1
V
COMP Threshold Voltage for Leaving
Burst−mode
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5
FSL518H, FSL538H, FSL518A, FSL538A
ELECTRICAL CHARACTERISTICS (continued)
TJ = −40 to +125°C and VCC = 14 V unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
DMAX
68
75
82
%
Control Section
Maximum Duty Ratio
VCOMP = 3.6 V
COMP Output High Voltage
COMP−pin Open
VCOMP-
5
V
OPEN
COMP Sourcing Current
ICOMP
70
GM
Transconductance of Internal Error
Amplifier
100
135
300
mA
mS
Current-sourcing capability of Internal
Error Amplifier
VFB = VREF − 1 V
IGM-SOURCE
55
90
125
mA
Current-sinking capability of Internal
Error Amplifier
VFB = VREF + 1 V
IGM-SINK
−55
−90
−125
mA
Reference Voltage to Regulate FB-pin
Voltage
VREF
2.45
2.5
2.55
V
Leading-edge Blanking Time of Internal
SENSEFET Current Signal (Note 9)
tLEB
250
ns
Propagation Delay of Turning-off Power
MOSFET (Note 9)
tPD
100
ns
LINE Section
Threshold Voltage for Line Detection
Enable
VLINE > VLINE-DET
VLINE-DET
Threshold Voltage for Line Detection
Disable
VLINE < VLINE-ADJ
VLINE-ADJ
0.15
0.05
tSET
Burst-mode Level Setting Time when Line
Detection is Enabled (Note 9)
100
ISET
1.6
During tSET
VLINE-SET0
12.4
Burst-mode Level 1 Set up Voltage
During tSET
VLINE-SET1
9.3
Burst-mode Level 2 Set up Voltage
During tSET
VLINE-SET2
Sourcing Current for Setting Burst-mode
Level when Line Detection is Disabled
VLINE = 0 V before VCC is charged to
VCC-START
Sourcing Current for Detecting Burst
Setting Zener Voltage in tSET
During tSET, VCC = 15 V, VLINE = 10 V
Burst-mode Level 0 Set up Voltage
IBURST
9.4
AV-BURST
LINE-pin Voltage to Burst-mode Level
Attenuation when Line Detection is
Disabled (Note 9)
V
2.7
V
ms
3.8
mA
V
10
10.6
V
7.9
V
10.6
mA
1/3
V/V
Protections: Over-Voltage Protection (OVP)
VCC-OVP
Over-Voltage Protection Threshold Voltage
for VCC−pin
23.0
tD-OVP
Delay time for OVP (Note 9)
24.5
26.0
6.0
V
ms
Protections: Over-Load Protection (OLP)
OLP-Triggering Threshold Voltage on
COMP−pin
Delay Time for OLP
VCOMP > VOLP after Soft-start Time
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6
VOLP
3.3
3.6
3.9
V
tD-OLP
30
60
90
ms
FSL518H, FSL538H, FSL518A, FSL538A
ELECTRICAL CHARACTERISTICS (continued)
TJ = −40 to +125°C and VCC = 14 V unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Abnormal Over-Current Protection (AOCP)
AOCP Monitoring duration after tLEB
(Note 9)
tAOCP
150
ns
Threshold Drain Current for Triggering
AOCP (Note 9)
IAOCP
ILIM
mA
Number of pulse for AOCP to skip
switching operation for NAOCP-HALT times
(Note 9)
NAOCP-TRIG
2
times
Number of skipped pulses after
NAOCP-TRIG is satisfied (Note 9)
NAOCP-HALT
7
times
NAOCP-
3
times
Number of Pulse for Satisfying NAOCP-TRIG
to Trigger Auto-restart Protection (Note 9)
COUNT
Protections: Line Detection (BI, BO, LOVP)
Brown-out (BO) Threshold Voltage on
LINE−pin
VLINE-BO
0.80
0.85
0.90
V
Brown-in (BI) Threshold Voltage on
LINE−pin
VLINE-BI
0.95
1
1.05
V
DVLINE-
0.09
0.15
0.21
V
Hysteresis between BI and BO
VLINE-BI − VLINE-BO
BIBO
tBO
Delay Time for Brown−out (Note 9)
100
ms
Threshold Voltage for Line Over−Voltage
Protection (LOVP)
VLINE-OVP
4.3
4.5
4.7
V
Recovering Level for LOVP
VLINE-OVP-
4.2
4.4
4.6
V
0.05
0.1
0.15
V
RECOVER
Hysteresis Voltage for LOVP
VLINE-OVP − VLINE-OVP-RECOVER
DVLINE-OVP
tLINE-OVP
2
ms
Junction Temperature to Trigger Thermal
Shutdown (Note 9)
TSD
147
°C
Junction Temperature for Resuming from
Thermal Shutdown (Note 9)
TRECOVER
95
°C
Delay Time for LOVP (Note 9)
Protections: Thermal Shutdown
Total Device Section
Operating Supply Current
(Control Part in Burst−mode)
VCOMP = 0 V, VDRAIN = 12 V,
RDRAIN = 500 W
IOP1
0.9
1.2
mA
Operating Supply Current
VCOMP = 3.2 V, VDRAIN = 12 V
IOP2
1.7
2.0
mA
VCC-pin current at startup condition
VCC = 14.9 V, VCOMP = 3.6 V
(Before VCC Reaches VCC-START)
ISTART
170
205
mA
Startup Charging Current
(JFET saturation current)
VCC = 0 V, VDRAIN = 40 V
Minimum DRAIN-pin Voltage to Start
Operation (Note 10)
VCC = VCOMP = 0 V
ICH
VSTART
1.2
4
mA
40
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Evaluated in the typical flyback application board, TA = 25°C
9. This parameter is not tested in production, but verified by design/characterization.
10. It is guaranteed that ICH can charge VCC up to VCC-START if DRAIN-pin voltage is higher than VSTART.
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 3. VCC-START vs. Temperature
Figure 4. VCC-STOP vs. Temperature
Figure 5. VCC-HVREG vs. Temperature
Figure 6. ICH vs. Temperature
Figure 7. FSL5x8H IOP1 vs. Temperature
Figure 8. FSL5x8H IOP2 vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 9. FSL5x8A IOP1 vs. Temperature
Figure 10. FSL5x8A IOP2 vs. Temperature
Figure 11. FSL5x8H fs vs. Temperature
Figure 12. FSL5x8A fs vs. Temperature
Figure 13. FSL518H ILIM (Normalized to 255C) vs.
Temperature
Figure 14. FSL518A ILIM (Normalized to 255C) vs.
Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 15. FSL538H ILIM (Normalized to 255C) vs.
Temperature
Figure 16. FSL538A ILIM (Normalized to 255C) vs.
Temperature
Figure 17. ICOMP vs. Temperature
Figure 18. GM vs. Temperature
Figure 19. IGM vs. Temperature
Figure 20. VREF vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 21. VBURL vs. Temperature
Figure 22. VBURH vs. Temperature
Figure 23. VLINE-OVP vs. Temperature
Figure 24. IBURST vs. Temperature
Figure 25. FSL518H/A RDS(ON) vs. Temperature
Figure 26. FSL538H/A RDS(ON) vs. Temperature
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11
FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 27. FSL518H/A COSS vs. VDRAIN
Figure 28. FSL538H/A COSS vs. VDRAIN
Figure 29. FSL518H/A Safe Operating Range
Figure 30. FSL538H/A Safe Operating Range
Figure 31. FSL518H/A BVDSS vs. Temperature
Figure 32. FSL538H/A BVDSS vs. Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
TYPICAL CHARACTERISTICS
Figure 33. FSL5x8H/A Power Dissipation vs.
Temperature
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FSL518H, FSL538H, FSL518A, FSL538A
APPLICATION INFORMATION
HV Current Source for VCC Start up and
VCC Regulation
The HV current source utilizes voltage on DRAIN pin to
charge capacitor on VCC pin. This current source is
activated during start-up and provides operating current
when VCC is lower than VCC-HVREG. Thanks to VCC
start-up function, no external start-up circuitry is needed.
The HV current source is disabled when VCC voltage is
charged to VCC-START.
VCC regulation also helps avoiding start-up failure during
soft-start and keeps FSL5x8 operating to count auto-restart
delay time (tAR) in protection mode, as illustrated in Figure
34. It also enables the use of smaller capacitance for VCC
biasing. The VCC regulation is not functional when the
external bias is higher than VCC-HVREG.
DRAIN
VCC
HV Current
Source
VCC−START/STOP
VCC
Regulation
tAR
Figure 34. VCC Start Up and VCC Regulation
Initial Setting for Line Detection and Adjusting
Burst-mode Operation
noise, connecting a ceramic capacitor to LINE pin is
recommended.
When line detection is enabled, voltage on LINE pin is
monitored to offer brown-in (BI), brown-out (BO) and line
over-voltage protections (LOVP).
With IBURST, VLINE reflects resistance of the external
resistor. FSL5x8 adjusts burst-mode operation threshold
based on real-time VLINE level. Please refer to burst
threshold setting table for LINE pin configuration and
settings.
LINE pin is used for both input-voltage detection and
burst-mode setting. When a voltage divider is connected
between bulk capacitor and LINE pin, a Zener diode
connected to LINE pin will allow to set level of burst-mode
operation. If there is no voltage divider, the line-detection
function is disabled and burst-mode operation level is set
linearly by simply connecting a resistor between LINE pin
and GND pin. In order to avoid interference from switching
Architecture B
Architecture A
VBULK
LINE
•
•
•
Input Voltage Detection
Brown−in/out Function
FALSE
Setting
Burst Threshold by
Zener
•
Setting Burst Threshold by
Resistance
VZ
LINE
RBURST
IBURST
Figure 35. Architecture of LINE-pin Setting
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14
FSL518H, FSL538H, FSL518A, FSL538A
BURST THRESHOLD SETTING TABLE
Line Detection Enable/Disable
Architecture A
Enable
Disable
Architecture B
VLINE (V)
VBURH/VBURL (V)
12.4 V < VZ
0.5 / 0.4
9.3 V < VZ < 10.6 V
0.6 / 0.5
VZ < 7.9 V
0.7 / 0.6
0.9 V < IBURST × RBURST < 1.2 V
0.5 / 0.4
1.2 V < IBURST × RBURST < 3.6 V
AV-BURST × (IBURST × RBURST) + 0.1
/AV-BURST × (IBURST × RBURST)
Initial Setting for Configuration of Feedback
Regulation
Being simultaneous to the initial setting of LINE-pin
functions, configuration of feedback regulation is also
decided based on peripheral circuitry to FB pin. If a voltage
divider is connected to FB pin, the IC will regulate output
voltage by referring to the reference voltage, VREF of
transconductance error amplifier.
In the case that external error amplifier is used for output
regulation, simply connect FB pin to GND pin. The external
output regulation circuitry will sinks ICOMP (100 mA) to
control PWM duty cycle for accuracy output regulation.
Controller
Controller
VCOMP−OPEN
VOUT
FB
VOUT
ICOMP
E/A
FB
COMP
IGM −SOURCE
VREF
COMP
(a) Isolated Application
IGM−SINK
(b) Non − Isolated Application
Figure 36. Isolated vs. Non-Isolated Application
Advanced Soft-Start Operation
After VCC is charged to VCC-START and all settings about
LINE-pin and FB-pin functions are done, switching
operation can be initiated with a soft-start period. For
soft−start period of 10 ms, both drain current and switching
frequency limits are settled to target value gradually as
shown in Fig. 37. Thus, output voltage will be increased
smoothly and the voltage stresses in switching devices can
be minimized.
www.onsemi.com
15
FSL518H, FSL538H, FSL518A, FSL538A
Pull high (5 V)
IDRAIN
1.25 ms
VCOMP
ILIM
VSS− LIMIT
Drain Current
8 Steps
Figure 37. Soft-start Operation
Main Control Frequency Reduction
t
comparing drain peak current and VCOMP. The VCOMP can
be controlled by either the input signal of error amplifier or
the signal delivered via opto−coupler and feedback loop for
output regulation.
Operating frequency of switching operation is
synchronized with COMP-pin voltage, VCOMP. When
VCOMP drops, operating frequency will also decrease. This
helps reducing switching losses and thus improve light-load
efficiency operation. The operating frequency will not be
decreased below 22-kHz so acoustic noise can be avoided.
Slope Compensation
Built-in slope compensation is added into the PWM
procedure when duty cycle is higher than 45%. It helps to
avoid sub-harmonic oscillation of peak-current control.
PWM Control
The FSL5x8 operates with peak−current mode to regulate
output voltage. The duty cycle of PWM is determined by
VSENSE
VSLOPE
VSENSE+COMP
45% Duty
ÎÎ
ÎÎ
ÎÎ
45% Duty
ÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
t
t
t
Figure 38. Slope Compensation
Burst−mode Operation
into burst−mode. In burst−mode, switching operation is
halted when VCOMP is lower than VBURL and resumed when
VCOMP is higher than VBURH. By skipping un-needed
switching cycles, the FSL5x8 drastically reduced the power
wasted during light load conditions.
As loading of the power converter decreases, VCOMP
decreases, thus reducing switching frequency of the
oscillator. When minimum operating frequency is reached,
to further reduce delivered output power, the device goes
www.onsemi.com
16
FSL518H, FSL538H, FSL518A, FSL538A
VO
VCOMP
t
VBURH
VBURL
t
IDS
PWM
disabled
PWM
disabled
t
Figure 39. Burst−mode Behavior
Protections
Over Load Protection (OLP)
VBURL and VBURH can be adjusted LINE-pin voltage
detected. It is provided for tuning light load efficiency and
acoustic noise. By adjusting VBURL, minimum peak value
of drain current of each switching cycle is adjusted as
described in Equation 1.
I DRAIN.PEAK.BURL +
V BURL
@I
4 @ 0.6 LIM
VCOMP will be pulled higher than VOLP when drain
current hits current limit and switching frequency operates
at its highest range. If the condition continues for tD-OLP,
OLP will be triggered and switching operation is stopped as
shown in Fig. 40.
The figure also shows typical protection mode behavior of
the IC. The operation current is supplied by HV current
source for tAR that can extend the restart period to reduce
average power dissipation when fault is still present. After
tAR, VCC drops to VCC-STOP to reset protective operation
and then, controller will be restarted.
(eq. 1)
Line Compensation
Propagation delay in turning off power MOSFET makes
drain current exceed current limit by an amount that related
to slope of drain current. The device adjusts its internal
current-limit reference voltage according to duty cycle to
compensate the effect of propagation delay. As a result, the
delivered output power is kept under control across different
input voltage conditions.
www.onsemi.com
17
FSL518H, FSL538H, FSL518A, FSL538A
VCOMP
VOLP
tD−OLP
t
IDRAIN
ILIM
VCC
t
VCC− HVREG
VCC−STOP
tAR
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Protection
Figure 40. Timing Chart of OLP
t
t
Over Voltage Protection (OVP)
OVP will be triggered after delay time tD−OVP when VCC
rises above VCC−OVP.
A malfunction of voltage-feedback circuitry for output
regulation in power converter could result in excessive
energy delivered to output. In this condition, both output
voltage and VCC can be increased by unstable operation, and
IDRAIN
Fault
t
Vcc
VCC −OVP
tD − OVP
VCC − HVREG
tAR
Protection
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Figure 41. Timing Chart of OVP
Abnormal Over-Current Protection (AOCP)
VCC −STOP
t
t
limited leading-edge time duration tLEB + tAOCP of each
switching cycle. If drain current exceeds current limit for a
few consecutive switching cycles, NAOCP-TRIG, switching
will be stopped for number of pulses, NAOCP-HALT. If the
fault condition is met for three times, NAOCP-COUNT, the
controller goes into protection mode as shown in Fig. 42.
When the secondary-side rectifier diodes or the
transformer windings are shorted, a steep drain current with
extremely high di/dt will flow through the MOSFET during
the minimum turn-on time. Under this condition, each
switching cycle generates very high current stress on power
MOSFET. The controller monitors drain current within a
www.onsemi.com
18
FSL518H, FSL538H, FSL518A, FSL538A
IDRAIN
1
3
2
ILIM
VCC
Stop
switching
tLEB+ tAOCP
Protection
{
Stop
switching
FSL5x8H: 1 pulse
FSL5x8A: 2 pulses
t
tAR
VCC − HVREG
VCC −STOP
t
Figure 42. Timing Chart of AOCP
Brown−in, Brown−out (BI/BO) and Line Over-Voltage
Protection (LOVP)
lower than VLINE-BO for tBO during normal operation,
brown-out will be triggered and the controller will go into
protection mode. If VLINE is higher than VLINE-OVP,
switching operation is halted until VLINE drops down below
VLINE-OVP-RECOVER. Both recovering from LOVP or after
BI, the controller performs a soft start sequence.
When a voltage divider is connected between LINE pin
and input bulk capacitor, line-detection function is enabled
and VLINE reflects peak of AC input voltage. If VLINE is
below VLINE-BI after initial setting, switching operation will
not be initiated until VLINE reaches VLINE-BI. If VLINE is
VBULK
tSET
VLINE
VLINE−OVP
t
VLINE−OVP − RECOVER
VLINE−BI
VLINE−BO
IDRAIN
tLINE −OVP
tSET
t
tSS
tBO
tSS
tBO
t
VCC
VCC − HVREG
tAR
tAR
t
Figure 43. LOVP, Brown-out and Brown-in Behavior
Thermal Shutdown (TSD)
exceeds shut-down temperature, TSD, thermal shutdown is
activated. The controller will go into protection mode after
thermal shutdown. If temperature is not lower than
TRECOVER, switching operation will not be resumed.
Since SENSEFET and controller are integrated in the
same package, it is easier for the controller to detect
temperature inside the package. When junction temperature
www.onsemi.com
19
FSL518H, FSL538H, FSL518A, FSL538A
TJ
TSD
TRECOVER
IDRAIN
tSS
V CC
tAR
t
t
VCC −HVREG
Figure 44. Timing Chart of TSD
www.onsemi.com
20
t
FSL518H, FSL538H, FSL518A, FSL538A
DESIGN CONSIDERATIONS
Peripheral Components
VBULK
While designing flyback converters using FSL5x8H/A,
there are some design considerations on selecting value and
rating of components and PCB (Printed Circuit Board)
layout as the following.
• Input/Output Capacitor
It is typical to select the input capacitor as 2~3 mF per
watt of peak input power for universal input range
(85−265 VRMS) and 1 mF per watt of peak input power for
European high input voltage range (195−265 V RMS).
The minimum DC link voltage is obtained as:
V DC
min
+
Ǹ
ǒ
2 @ V line
min
Ǔ
2
*
P in @ ǒ1 * D chǓ
f L @ C DC
RLINE-upper
LINE
R LINE-lower
Figure 45. LINE Pin Settle for BI/BO/LOVP
,
(eq. 2)
Brown−in AC Voltage +
where Dch is the DC link capacitor charging duty ratio
which is typically about 0.2. fL is line voltage frequency.
Considering the output voltage ripple, capacitance at
the output terminal can be determined as the following.
For better voltage ripple at output terminal, low ESR
(Effective Series Resistance) type capacitor is
recommended.
C OUT +
0.25 @ I OUT
V OUT*ripple @ f min
,
V LINE−OVP
C LINE−F +
(eq. 3)
,
(eq. 5)
R LINE−upper ) R LINE−lower
R LINE−lower
1
Ǹ2
3
ǒRLINE−upperńńRLINE−lowerǓ @ fSW
(eq. 6)
(eq. 7)
• Selecting FB/COMP and Consideration when One of
Both is Selected
For non-isolated converters, connects the output
voltage divider to FB pin. For isolated converters, FB pin
should be connected to GND, and the external feedback
circuit should connect to COMP as well.
FSL5x8 includes HV start-up circuit providing startup
current, which determine startup time. It can be calculated
with ICH and VCC capacitance. The typical value of VCC
capacitor is selected in a range of 10 to 47 mF. It is
recommended that VCC capacitor and FSL5x8 should be
placed as close as possible to reject noise decoupling.
I CH
R LINE−lower
1
Ǹ2
Line OVP AC Voltage +
• VCC Capacitance
C VCC @ V CC*START
R LINE−upper ) R LINE−lower
V LINE−BI
where IOUT is a max output load current, VOUT-ripple is
deviation of a ripple voltage and fmin should minimum
freqeuncy between operating frequency deviation.
Start−up Time +
C LINE−F
• Preventing Audible Noise
Even though the switching frequency of the FSL5x8 is
above the range of human hearing, audible noise can be
generated during transient or burst operation. In most
flyback converters, the major noise sources are
transformers and capacitors. Transformers produce
audible noise, since they contain many physically
movable elements, such as coils, isolation tapes and
bobbins. The most effective way to reduce the audible
noise in the transformer is to remove the possibility of
physical movement of the transformer elements by using
adhesive material or by varnishing.
Ceramic capacitors can also produce audible noise,
because of their piezoelectric characteristics. By
replacing the ceramic capacitor with a film capacitor, the
audible noise can be reduced. Another way to lower
audible noise is to reduce the snubber capacitor value,
(eq. 4)
• Consideration on Designing BI/BO/LOVP
Line input voltage can be detected for brown-in (BI),
brown-out (BO) and input line over-voltage protection
(LOVP) by connecting LINE pin with dividing resisters
linking to input bulk capacitor. Each level of BI and
LOVP can be determined as following. Meanwhile,
CLINE-F should be choosen considering some noises on
the line induced by switching of the main switch and etc.
It is typical to select 3~5 times of time constant higher
than switching frequency.
www.onsemi.com
21
FSL518H, FSL538H, FSL518A, FSL538A
• Clamping Circuit for internal MOSFET
which decreases the pulse current that charges the
capacitor every time the FSL5x8 resumes switching
operation in burst−mode.
For more information, please refer to AN−4148.
Due to parasitic or leakage inductance, it is inevitable
that voltage on DRAIN pin of MOSFET shows some
spikes during switching off. A clamping circuit is
generally implemented if the spike can be so high that
makes DRAIN voltage possibly exceeds MOSFET’s
breakdown voltage, BVDSS . The clamping circuit can be
RCD snubber or transient-voltage suppressor. In both
cases, the design target is to clamp the reflected voltage
that appears across primary winding with a clamping
voltage Vclamp .
Vclamp should be set up properly considering power
loss and BVDSS of MOSFET. Vclamp is way too high,
MOSFET is likely to get damage at maximum input
voltage. Whereas, too low one could cause power loss
increasing at the clamp circuit. Generally, value in 2~2.5
times of VRO is usually chosen. Additionally, it should
not exceed over 90% of BVDSS.
• Maximum Duty and Reflected Output Voltage
When MOSFET in FSL5x8 is turned off, the input
voltage together with the reflected output voltage (VRO )
on primary winding of the transformer are imposed on
MOSFET.
V DRAIN
+ Ǹ2 @ V line
max
max
) V RO
(eq. 8)
Vlinemax is maximum ac-input voltage in r.m.s. value.
VRO is a function of maximum duty (Dmax ) and minimum
DC-link voltage.
D max
V RO +
1 * D max
@ V DC
(eq. 9)
min
The designed Dmax should not exceed FSL5x8’s
maximum duty raio specification, DMAX . It is typical to
have 70% of de-rating on VDRAINmax according to
MOSFET’s breakdown voltage. With 800 V of
breakdown voltage in FSL5x8, more room are created to
target higher Dmax .
Ǹ2 @ V
line
When Dmax is assigned, turn ratio of the transformer has
been decided.
n+
NS
+
V RO
V OUT ) V F
,
NP
Lm +
DC
2
min
@ D max
Ǔ
VIN
(eq. 10)
I DRAIN
PEAK
+
V DC
min
@ D max
+
V DC
min
+
+
L
Llk
VDRAIN
−
Figure 46. Magnetic Component and RCD Snubber
IDRAIN
IDRAIN
(eq. 11)
PEAK
t
VDS
The inductance value affects maximum drain current
(IDRAINPEAK ), which should be limited by FSL5x8’s ILIM
specification with some margin. Care needs to be taken
when designing Lm and choosing part from FSL5x8
series.
P in
NS
VRO
−
2
P in @ f SW @ K RF
(eq. 13)
−
+
where NP and NS stands for primary and secondary
windings’ turn ratio of the transformer, VOUT stands for
output voltage, and VF stands for forward voltage of
rectifying diode connecting to the secondary winding.
Inductance (Lm ) of the primary winding can be
obtained from input power (Pin ) and switching frequency
(fsw ), with ripple factor (KRF ) left to be decided. KRF ≥ 1
results in lower inductance and discontinuousconduction-mode (DCM) design, which tend to have
smaller switching loss. KRF < 1 results in a continuousconduction-mode (CCM) design. Which tend to be able
to deliver more power with same maximum drain current.
ǒV
) V clamp v 90% @ BV DSS
AN−4137 and AN−4140 provide detailed flyback
converter, transformer, and snubber design information.
A design tool with accompanying manual is also made for
FSL5x8 series.
• Transformer Design Considerations
NP
max
VRO
Vclamp
VIN
@ D max
2 @ L m @ f SW
(eq. 12)
t
Figure 47. Typical Waveform of DRAIN Current
and Voltage
www.onsemi.com
22
FSL518H, FSL538H, FSL518A, FSL538A
PCB Layout Recommendations
There are some suggestions for grounding connection.
Hereafter are a few hints that would help designers to
make their SMPS working better.
• High-frequency switching current/voltage makes PCB
layout a very important design issue. Good PCB layout
minimizes EMI (Electromagnetic Interference) and helps
the power supply survive during surge/ESD
(ElectroStatic Discharge) tests.
• To improve EMI performance and reduce line frequency
ripples, the output of the bridge rectifier should be
connected to capacitor CDC as close as possible.
• The high-frequency current loop is formed from the
beginning of bridge rectifier, CDC, power transformer,
Integrated MOSFET and return to GND of CDC. The area
enclosed by this current loop should be designed as small
as possible to reduce conduction and radiation noise.
Keep the traces (especially 2a " 2b " 1) short, direct,
and wide. High-voltage traces related the drain of
MOSFET and RCD snubber should be kept far way from
control circuits to prevent unnecessary interference. If
a heatsink is used for MOSFET, connect this heatsink to
power ground.
• As indicated by 2a, the ground of control circuits should
be connected first, then to other circuitry.
• Place CVcc as close to VCC pin of the FSL5x8H/A as
possible for good decoupling. It is recommended to use
a few of micro-farad capacitor and 100 nF ceramic
capacitor for high frequency noise decoupling as well.
• GND: There are two kinds of GND in power conversion
•
•
•
board and should be separated for avoiding interference
and better performance.
Regarding the ESD discharge path, the charges go from
secondary, through the transformer stray capacitance, to
GND first, and back to mains. It should be noted that
control circuits should not be placed on the discharge
path. Point discharge for common choke can decrease
high-frequency impedance and increase ESD immunity.
3 should be a point-discharger route to bypass the static
electricity energy. It is suggested to map out this discharge
route.
Should a Y-cap be required between primary and
secondary, connect this Y-cap to the positive terminal of
CDC. If this Y-cap is connected to primary GND, it should
be connected to the negative terminal of CDC (GND)
directly. Point discharge of this Y-cap helps for ESD;
however, the creepage between these two pointed ends
should be at least 5 mm according to safety requirements.
Thermal Considerations
Power MOSFET dissipates heat during switching
operation. If chip temperature exceed TSD, thermal
shutdown would be triggered and FSL5x8 stops operating to
protect itself from damage. The path of lowest thermal
impedance from FSL5x8’s chip to external are DRAIN pins.
It is recommended to increase area of connected copper to
DRAIN pin as much as possible.
Enlarge DRAIN pin pattern
for better heat emission
Figure 48. Layout Considerations
www.onsemi.com
23
FSL518H, FSL538H, FSL518A, FSL538A
Design Example
Hereafter is a typical schematic of an isolated flyback.
240R
1A/250V
MOV
TVR/1047
AC
Input
2A/600V
DF06M
XC/0.33uF
200k
1nF/
1kV
0R
15V
220uF/
35V
22uF/50V
1uH
12V
470uF/
25V
470uF/25V
1R
1uH
FSV10150V
FSV10120V
200k
22M
47uF/400V
T1
15V+
220uF/
35V
240R
10mH
Z
220pF/
100V
68uF/25V
0R
COMP
100k
GND DRAIN
8
ES1J
COMP
2 VCC DRAIN 7
3 FB
VCC
1nF
15V
12V
5.1k
FOD817A
22uF/
50V
4 COMP LINE 5
FSL538A
RS1D
1
VCC
15V+
NC
150k
5.1k
100nF
100nF/50V
200k
1nF
2M
7.5V
YC/222pF
NCP431
30k
Figure 49. FSL538AFLYGEVB Schematic
REFERENCES
For more details on specific designs, please refer to below documents:
• AN−4148 Audible Noise Reduction Technique for FPS Applications
•
•
•
•
•
•
https://www.onsemi.com/pub/Collateral/AN−4148.pdf.pdf
AN−4137 Design Guidelines for Off-line Flyback Converters Using Power Switch
https://www.onsemi.com/pub/Collateral/AN−4137.pdf.pdf
AN−4140 Transformer Design Consideration for Offline Flyback Converters Using Power Switch
https://www.onsemi.com/pub/Collateral/AN−4140.pdf.pdf
EVBUM2650/D: 14.5 W auxiliary power for white goods and industrial equipment with FSL538HPG
https://www.onsemi.com/pub/Collateral/EVBUM2650−D.PDF
EVBUM2651/D: 15 W auxiliary power for white goods and industrial equipment with FSL538APG
https://www.onsemi.com/pub/Collateral/EVBUM2651−D.PDF
EVBUM2652/D: 8 W auxiliary power for white goods and industrial equipment with FSL518APG
https://www.onsemi.com/pub/Collateral/EVBUM2652−D.PDF
FSL5x8 Application note and Design tool
https://www.onsemi.com/PowerSolutions/supportDoc.do?type=tools&rpn=FSL538
www.onsemi.com
24
24k
GND
FSL518H, FSL538H, FSL518A, FSL538A
ORDERING INFORMATION
Current Limit (A)
RDS.ON,max (W)
Package
Shipping†
FSL518HPG
0.46
8.0
PDIP−7
(Pb-Free)
Tube
FSL518APG
0.61
8.0
PDIP−7
(Pb-Free)
Tube
FSL538HPG
0.66
4.6
PDIP−7
(Pb-Free)
Tube
FSL538APG
0.86
4.6
PDIP−7
(Pb-Free)
Tube
Device
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
www.onsemi.com
25
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE C
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
1
4
E1
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11774D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PDIP−7 (PDIP−8 LESS PIN 6)
PAGE 1 OF 1
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