NCP81151BMNTBG

NCP81151B VR12.5 Compatible Synchronous Buck MOSFET Driver The NCP81151B is a high performance dual MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. It can drive up to 3 nF load with a 25 ns propagation delay and 20 ns transition time. Adaptive anti−cross−conduction and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook systems. The UVLO function guarantees the outputs are low when the supply voltage is low. Features • • • • • • • • • Faster Rise and Fall Times Adaptive Anti−Cross−Conduction Circuit Zero Cross Detection function Output Disable Control Turns Off Both MOSFETs Undervoltage Lockout Power Saving Operation Under Light Load Conditions Direct Interface to NCP6131 and Other Compatible PWM Controllers Thermally Enhanced Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAM 1 1 CPMG G DFN8 CASE 506AA CP = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PINOUT DIAGRAM 8 DRVH 7 SW 3 6 GND 4 5 DRVL BST 1 PWM 2 EN VCC FLAG 9 Typical Applications • Power Management Solutions for Notebook Systems ORDERING INFORMATION Device Package Shipping† NCP81151BMNTBG DFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2015 December, 2015 − Rev. 0 1 Publication Order Number: NCP81151B/D NCP81151B BST VCC DRVH PWM Logic SW Anti−Cross Conduction VCC DRVL EN ZCD Detection UVLO Figure 1. Block Diagram PIN DESCRIPTIONS Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. 3 EN Logic input. A logic high to enable the part and a logic low to disable the part. Three states logic input: EN = High to enable the gate driver; EN = Low to disable the driver; EN = Mid to go into diode mode (both high and low side gate drive signals are low) 4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node. 7 SW 8 DRVH High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane. Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. www.onsemi.com 2 NCP81151B APPLICATION CIRCUIT VIN 5V_POWER TP1 R1 1.02 R164 BST HG PWM SW PWM DRON EN GND VCC Q1 NTMFS4821N 0.027uF TP2 0.0 NCP81151B TP3 R143 0.0 TP4 C4 LG C2 4.7uF C3 4.7uF + CE9 390uF R142 0.0 VREG_SW1_HG TP5 L VREG_SW1_OUT VCCP 235nH TP6 TP7 VREG_SW1_LG Q9 NTMFS4851N Q10 NTMFS4851N R3 2.2 JP13_ETCH CSN11 PAD C5 1uF C1 4.7uF TP8 C6 2700pF JP14_ETCH CSP11 Figure 2. Application Circuit www.onsemi.com 3 NCP81151B ABSOLUTE MAXIMUM RATINGS ELECTRICAL INFORMATION Symbol Pin Name VMAX VMIN VCC Main Supply Voltage Input 6.5 V −0.3 V BST Bootstrap Supply Voltage 35 V wrt/ GND 40 V v 50 ns wrt/ GND 6.5 V wrt/ SW 7.7 V < 50 ns wrt/ SW −0.3 V wrt/SW SW Switching Node (Bootstrap Supply Return) 35 V 40 V v 50 ns −5 V −10 V (200 ns) DRVH High Side Driver Output BST + 0.3 V −0.3 V wrt/SW −2 V (< 200 ns) wrt/SW DRVL Low Side Driver Output VCC + 0.3 V −0.3 V DC −5 V (< 200 ns) PWM DRVH and DRVL Control Input 6.5 V −0.3 V Enable Pin 6.5 V −0.3 V 0V 0V EN GND Ground Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *All signals referenced to AGND unless noted otherwise. THERMAL INFORMATION Symbol RqJA Parameter Thermal Characteristic QFN Package (Note 1) Value Unit 119 °C/W TJ Operating Junction Temperature Range (Note 2) −40 to 150 °C TA Operating Ambient Temperature Range −40 to +100 °C TSTG Maximum Storage Temperature Range −55 to +150 °C MSL Moisture Sensitivity Level − QFN Package 1 *The maximum package power dissipation must be observed. 1. 1 in2 Cu, 1 oz. thickness. 2. JESD 51−7 (1S2P Direct−Attach Method) with 1 LFM. www.onsemi.com 4 NCP81151B NCP81151B ELECTRICAL CHARACTERISTICS (−40°C < TA < +100°C; 4.5 V < VCC < 5.5 V, 4.5 V < BST−SWN < 5.5 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted) Parameter Test Conditions Min Typ Max Unit 5.5 V SUPPLY VOLTAGE 4.5 VCC Operation Voltage UNDERVOLTAGE LOCKOUT VCC Start Threshold 3.8 4.35 4.5 V VCC UVLO Hysteresis 150 200 250 mV 20 mA SUPPLY CURRENT Shutdown Mode ICC + IBST, EN = GND 11 Normal Mode ICC + IBST, EN = 5 V, PWM = OSC 4.7 mA Standby Current ICC + IBST, EN = HIGH, PWM = LOW, No loading on DRVH & DRVL 0.9 mA Standby Current ICC + IBST, EN = HIGH, PWM = HIGH, No loading on DRVH & DRVL 1.1 mA BOOTSTRAP DIODE Forward Voltage VCC = 5 V, forward bias current = 2 mA 0.1 0.4 0.6 V PWM INPUT PWM Input High 3.4 PWM Mid−State 1.3 V 2.7 PWM Input Low 0.7 ZCD Blanking Timer 350 V V ns HIGH SIDE DRIVER Output Impedance, Sourcing Current VBST−VSW = 5 V 0.9 1.7 W Output Impedance, Sinking Current VBST−VSW = 5 V 0.7 1.7 W DRVH Rise Time trDRVH VCC = 5 V, 3 nF load, VBST−VSW = 5 V 16 25 ns DRVH Fall Time tfDRVH VCC = 5 V, 3 nF load, VBST−VSW =5 V 11 18 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 10 30 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 10 40 ns SW Pulldown Resistance SW to PGND 45 kW DRVH Pulldown Resistance DRVH to SW, BST−SW = 0 V 45 kW LOW SIDE DRIVER W Output Impedance, Sourcing Current 0.9 1.7 Output Impedance, Sinking Current 0.4 0.8 W DRVL Rise Time trDRVL CLOAD = 3 nF 16 25 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 11 15 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 10 30 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 5.0 25 ns DRVL Pulldown Resistance DRVL to PGND, VCC = PGND www.onsemi.com 5 45 kW NCP81151B NCP81151B ELECTRICAL CHARACTERISTICS (−40°C < TA < +100°C; 4.5 V < VCC < 5.5 V, 4.5 V < BST−SWN < 5.5 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V, unless otherwise noted) Parameter Test Conditions Min Typ Max Unit EN INPUT Input Voltage High 3.3 Input Voltage Mid 1.35 V 1.8 Input Voltage Low Input bias current −1.0 Propagation Delay Time 20 V 0.6 V 1.0 mA 40 ns 20 mA SW NODE SW Node Leakage Current Zero Cross Detection Threshold Voltage −6.0 mV Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 6 NCP81151B Table 1. DECODER TRUTH TABLE ZCD DRVL DRVH PWM High (Enable High) Input ZCD Reset Low High PWM Mid (Enable High) Positive Current Through the Inductor High Low PWM Mid (Enable High) Zero Current Through the Inductor Low Low PWM Low (Enable High) ZCD Reset High Low X Low Low Enable at Mid 1V 1V Figure 3. PWM DRVH−SW DRVL IL Figure 4. Timing Diagram www.onsemi.com 7 NCP81151B APPLICATION INFORMATION high after the tpdhDRVH delay. When PWM is set low, the driver will monitor the gate voltage of the high side MOSFET. When the DRVH−SWN voltage falls below the top gate drive threshold, DRVL will be set to high after the tpdhDRVL delay. The NCP81151B gate driver is a single phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. The NCP81151B is designed to work with ON Semiconductor’s NCP6131 multi−phase controller. This gate driver is optimized for notebook applications. Layout Guidelines The layout for a DC−DC converter is very important. The bootstrap and VCC bypass capacitors should be placed close to the driver IC. Connect the GND pin to a local ground plane. The ground plane can provide a good return path for gate drives and reduce the ground noise. The thermal slug should be tied to the ground plane for good heat dissipation. To minimize the ground loop for the low side MOSFET, the driver GND pin should be close to the low−side MOSFET source pin. The gate drive trace should be routed to minimize its length. The minimum width is 20 mils. Undervoltage Lockout DRVH and DRVL are held low until VCC reaches 4.5 V during startup. The PWM signal will control the gate status when VCC threshold is exceeded. Three−State EN Signal When EN is set to the mid state, both DRVH and DRVL are set low, to force diode mode operation. PWM Input and Zero Cross Detect (ZCD) The PWM input, along with EN and ZCD, control the state of DRVH and DRVL. When PWM is set high, DRVH will be set high after the adaptive non−overlap delay. When PWM is set low, DRVL will be set high after the adaptive non−overlap delay. When PWM is set to the mid state, DRVH will be set low, and after the adaptive non−overlap delay, DRVL will be set high. DRVL remains high during the ZCD blanking time. When the timer has expired, the SW pin will be monitored for zero cross detection. After the detection, DRVL will be set low. Gate Driver Power Loss Calculation The gate driver power loss consists of the gate drive loss and quiescent power loss. The equation below can be used to calculate the power dissipation of the gate driver. QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. P DRV + ƪ Adaptive Non−overlap Adaptive dead time control is used to avoid shoot−through damage of the power MOSFETs. When the PWM signal pulls high, DRVL will be set low and the driver will monitor the gate voltage of the low side MOSFET. When the DRVL voltage falls below the gate threshold, DRVH will be set to f SW 2 n ǒn MF Q GMF ) n SF ƫ Q GSFǓ ) I CC V CC (eq. 1) Also shown is the standby dissipation factor (ICC x VCC) of the driver. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA−01 ISSUE E DATE 22 JAN 2010 1 SCALE 4:1 D PIN ONE REFERENCE 2X 0.10 C 2X A B ÇÇ ÇÇ ÇÇ 0.10 C L1 DETAIL A E OPTIONAL CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 SIDE VIEW A1 C SEATING PLANE GENERIC MARKING DIAGRAM* 1 DETAIL A D2 1 8X 4 L 8 5 e/2 e 8X XXMG G XX = Specific Device Code M = Date Code G = Pb−Free Device E2 K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. b 0.10 C A B 0.05 C NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* BOTTOM VIEW 1.30 PACKAGE OUTLINE 0.90 8X 0.50 2.30 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON18658D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DFN8, 2.0X2.0, 0.5MM PITCH PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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