UPA2782GR

DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA2782GR SWITCHING N-CHANNEL POWER MOS FET/SCHOTTKY BARRIER DIODE DESCRIPTION The µPA2782GR is N-Channel Power MOSFET, which built a Schottky Barrier Diode inside. This product is designed for synchronous DC/DC converter application. PACKAGE DRAWING (Unit: mm) 8 5 1, 2, 3 ; Source 4 ; Gate 5, 6, 7, 8 ; Drain FEATURES • Built a Schottky Barrier Diode • Low on-state resistance RDS(on)1 = 11 mΩ TYP. (VGS = 10 V, ID = 5.5 A) RDS(on)2 = 16 mΩ TYP. (VGS = 4.5 V, ID = 5.5 A) RDS(on)3 = 19 mΩ TYP. (VGS = 4.0 V, ID = 5.5 A) • Low Ciss: Ciss = 660 pF TYP. • Small and surface mount package (Power SOP8) 1 4 5.37 MAX. +0.10 –0.05 6.0 ±0.3 4.4 0.8 1.8 MAX. 1.44 0.15 0.05 MIN. 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 ORDERING INFORMATION PART NUMBER PACKAGE Power SOP8 0.12 M µ PA2782GR ABSOLUTE MAXIMUM RATINGS (TA = 25°C. All terminals are connected.) Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) [MOSFET] Drain Current (pulse) Note1 Note2 EQUIVALENT CIRCUIT Drain VDSS VGSS ID(DC) ID(pulse) 30 ±20 ±11 ±44 2.5 2 1 150 V V A A A W W °C °C Gate Protection Diode Source Gate Schottky Diode Average Forward Current Total Power Dissipation Total Power Dissipation [SCHOTTKY] IF(AV) PT PT Tch, Tj Note3 Note3 [MOSFET] [SCHOTTKY] Channel & Junction Temperature Storage Temperature Tstg −55 to + 150 Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2. Rectangle wave, 50% Duty Cycle 2 3. Mounted on ceramic substrate of 1200 mm x 2.2 mm Caution Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16421EJ1V0DS00 (1st edition) Date Published April 2003 NS CP(K) Printed in Japan 2002 µPA2782GR ELECTRICAL CHARACTERISTICS (TA = 25°C, unless other wise noted. All terminals are connected.) CHARACTERISTICS Zero Gate Voltage Drain Current Note SYMBOL IDSS TEST CONDITIONS VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V, TA = 125°C MIN. TYP. MAX. 50 10 ±10 UNIT µA mA Gate Leakage Current Gate Cut-off Voltage Drain to Source On-state Resistance Note IGSS VGS(off) RDS(on)1 RDS(on)2 RDS(on)3 VGS = ±20 V, VDS = 0 V VDS = 10 V, ID = 1 mA VGS = 10 V, ID = 5.5 A VGS = 4.5 V, ID = 5.5 A VGS = 4.0 V, ID = 5.5 A VDS = 10 V VGS = 0 V f = 1 MHz VDD = 15 V, ID = 5.5 A VGS = 10 V RG = 10 Ω 1.0 11 16 19 660 340 83 9 5 29 6 VDD = 15 V VGS = 5 V ID = 11 A IF = 1 A, VGS = 0 V IF = 1 A, VGS = 0 V, TA = 125°C 7.1 2.1 3.1 0.45 0.37 25 14 µA V mΩ mΩ mΩ pF pF pF ns ns ns ns nC nC nC 2.5 15 22.5 29 Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage Note Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) 0.5 V V ns nC Reverse Recovery Time Reverse Recovery Charge trr Qrr IF = 7 A, VGS = 0 V di/dt = 100 A/µs Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE D.U.T. RL VGS PG. RG Wave Form D.U.T. VGS 0 10% VGS 90% IG = 2 mA 50 Ω RL VDD VDD PG. 90% VDS 90% 10% 10% VGS 0 τ τ = 1 µs Duty Cycle ≤ 1% VDS VDS Wave Form 0 td(on) ton tr td(off) toff tf 2 Data Sheet G16421EJ1V0DS µPA2782GR TYPICAL CHARACTERISTICS (TA = 25°C. All terminals are connected.) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA dT - Percentage of Rated Power - % 120 TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 PT - Total Power Dissipation - W 100 2.4 2 1.6 1.2 0.8 0.4 0 Mounted on ceramic substrate of 2 1200 mm x 2 .2 mm MOSFET 80 60 SCHOTTKY 40 20 0 0 25 50 75 100 125 150 175 0 20 40 60 80 100 120 140 160 TA - Ambient Temperature - °C TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 ID(pulse) ID(DC) 10 DC 1 RDS(on) Limited (at VGS = 10 V) 100 ms Power Dissipation Limited 0.1 Single pulse Mounted on ceramic substrate of 2 1200 mm x 2.2 mm 0.01 0.01 0.1 1 10 100 10 ms PW = 100 µs 1 ms ID - Drain Current - A VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (MOSFET) 1000 Rth(t) - Transient Thermal Resistance - °C/W 100 Rth(ch-A) = 62.5°C/W 10 1 Mounted on ceramic substrate of 1200 mm × 2.2 mm Single pulse 0.1 1m 10 m 100 m 1 10 100 1000 2 PW - Pulse Width - s Data Sheet G16421EJ1V0DS 3 µPA2782GR TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (SCHOTTKY) 1000 Rth(t) - Transient Thermal Resistance - °C/W Rth(j-A) = 125°C/W 100 10 1 Mounted on ceramic substrate of 1200 mm x 2.2 mm Single pulse 2 0.1 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE 50 Pulsed 45 3 VDS = 10 V ID = 1 mA GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE VGS(off) - Gate Cut-off Voltage - V ID - Drain Current - A 40 VGS = 10 V 35 30 25 20 15 10 5 0 0 0.5 1 1.5 2 4.5 V 2.5 2 4.0 V 1.5 1 0.5 0 - 50 0 50 100 150 VDS - Drain to Source Voltage - V Tch - Channel Temperature - °C RDS(on) - Drain to Source On-state Resistance - mΩ 30 Pulsed 25 VGS = 4.0 V 4.5 V 15 10 V 10 RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 30 Pulsed 25 20 20 15 ID = 5.5 A 10 5 5 0 0.1 1 10 100 0 0 5 10 15 20 ID - Drain Current - A VGS - Gate to Source Voltage - V 4 Data Sheet G16421EJ1V0DS µPA2782GR RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 40 Pulsed CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 10000 Ciss, Coss, Crss - Capacitance - pF 35 30 25 20 15 10 V 10 5 0 - 50 VGS = 4.0 V 4.5 V V GS = 0 V f = 1 MHz 1000 C iss C oss 100 C rss 0 50 100 150 10 0.01 0.1 1 10 100 Tch - Channel Temperature - °C VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS 1000 DYNAMIC INPUT/OUTPUT CHARACTERISTICS 30 6 ID = 11 A 25 VDD = 24 V 15 V 6V 5 VDS - Drain to Source Voltage - V VDD = 15 V VGS = 10 V RG = 10 Ω 100 20 VGS 4 td(off) 10 td(on) tf tr 15 3 10 VDS 5 2 1 1 0.1 1 10 100 0 0 2 4 6 8 0 ID - Drain Current - A QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE 100 100000 10000 1000 SOURCE TO DRAIN DIODE REVERSE CURRENT IF - Diode Forward Current - A 125°C 10 T A = 2 5°C IR - Reverse Current - µA VDS = 30 V 100 10 1 0.1 0.01 - 50 24 V 1 VGS = 0 V Pulsed 0.1 0 0.2 0.4 0.6 0.8 1 1.2 0 50 100 150 VF(S-D) - Source to Drain Voltage - V Tj - Junction Temperature - °C Data Sheet G16421EJ1V0DS 5 VGS - Gate to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns µPA2782GR • The information in this document is current as of April, 2003. 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