UPC8104

DATA SHEET DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC8104GR UP CONVERTER + QUADRATURE MODULATOR IC FOR DIGITAL MOBILE COMMUNICATION SYSTEMS DESCRIPTION The µPC8104GR is a silicon monolithic integrated circuit designed as quadrature modulator for digital mobile communication systems. This modulator consists of 1.9 GHz up-converter and 400 MHz quadrature modulator which are packaged in 20 pin SSOP. The device has power save function and can operate 2.7 to 5.5 V supply voltage, therefore, it can contribute to make RF block small, high performance and low power consumption. FEATURES • • • • 20 pin SSOP suitable for high density surface mounting. High linearity up converter is incorporated; PRFout(sat) = −6 dBm TYP. Low phase difference due to digital phase shifter is adopted. Wide operating frequency range. Up converter; fRFout = 800 MHz to 1.9 GHz Modulator ; fMODout = 100 MHz to 400 MHz, fI/Q = DC to 10 MHz • • • External IF filter can be applied between modulator output and up converter input terminal. Supply voltage: VCC = 2.7 to 5.5 V Equipped with power save function. APPLICATION • • Digital cordless phones Digital cellular phones ORDERING INFORMATION PART NUMBER PACKAGE 20 pin plastic SSOP SUPPLYING FORM Embossed tape 12 mm wide. QTY 2.5 kp/Reel. Pin 1 indicates pull-out direction of tape. µPC8104GR-E1 * For evaluation sample order, please contact your local NEC sales office. (Order number: µPC8104GR) Caution electro-static sensitive device The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10099EJ4V0DS00 (4th edition) Date Published October 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1995, 1999 µPC8104GR INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View) Lo1 in 1 Lo1 in 2 GND 3 (MOD) I4 I5 Q6 Q7 GND 8 (UP Con) RF out 9 GND 10 (UP Con) 90˚ Phase Shifter REG. 20 VCC 19 Power Save 18 GND 17 GND 16 MOD out 15 Up Con in 14 Up Con in 13 VCC (UP Con) 12 Lo2 in 11 Lo2 in APPLICATION EXAMPLE (PHS) RX DEMO. I Q SW ÷N PLL PLL µ PC8104GR I 0˚ TX PA φ 90˚ Q Filter 2 Data Sheet P10099EJ4V0DS00 µPC8104GR ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Power Save Voltage Power Dissipation Operating Temperature Storage Temperature SYMBOL VCC VPS PD TA Tstg RATING 6.0 6.0 430 −40 to +85 −55 to +150 UNIT V V mW °C °C TEST CONDITION TA = +25 °C TA = +25 °C TA = +85 °C Note1 Note 1: Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Operating Temperature Up Converter RF Frequency Up Converter Input Freq. Modulator Output Frequency Lo1 Input Frequency Lo2 Input Frequency I/Q Input Frequency SYMBOL VCC TA fRFout fUpConin fMODout fLo1in fLo2in fI/Qin 800 DC 1800 10 MHz MHz PLo1in = −10 dBm PLo2in = −10 dBm PI/Qin = 600 mVp-p MAX (Single ended) MIN. 2.7 −40 0.8 100 TYP. 3.0 +25 MAX. 5.5 +85 1.9 400 UNIT V °C GHz MHz TEST CONDITIONS ELECTRICAL CHARACTERISTICS (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS ≥ 1.8 V) PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS UP CONVERTER + QUADRATURE MODULATOR TOTAL Total Circuit Current Total Circuit Current at Power-Save Mode Total Output Power Lo Carrier Leak Note2 IccTOTAL Icc(PS)TOTAL 18 28 0.1 37 10 −8.5 −30 −30 mA No input signal VPS ≤ 1.0 V I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) µA dBm dBc dBc PRFout LOL ImR −18.5 −13.5 −40 −40 Image Rejection (Side Band Leak) Note 2: Lo1 + Lo2 Data Sheet P10099EJ4V0DS00 3 µPC8104GR STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS ≥ 1.8 V) PARAMETER UP CONVERTER BLOCK Up Con. Circuit Current Up Con. Circuit Current at Power-Save Mode Conversion Gain Maximum Output Power Output Intercept Point IccUpCon Icc(PS)UpCon 12 5 mA No input signal VPS ≤ 1.0 V SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS µA dB dBm dBm CG PRF(sat) OIP3 4 −6 0 fRFout = 1.9 GHz fUpConin = 240.0 MHz/240.2 MHz QUADRATURE MODULATOR BLOCK MOD. Circuit Current MOD. Circuit Current at Power-Save Mode Output Power Lo1 Carrier Leak Image Rejection (Side Band Leak) I/Q 3rd Order Intermodulation Distortion I/Q Input Impedance I/Q Bias Current Lo1 Input VSWR Power Save Rise Time Power Save Fall Time IccMOD Icc(PS)MOD −16.5 −40 −40 −50 −30 −30 −30 10 16 21 5 mA No input signal VPS ≤ 1.0 V µA dBm dBc dBc PMODout LOL ImR I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) IM3I/Q dBc kΩ I/Q DC = 1.5 V PI/Qin = 500 mVp-p (Single ended) (I → I, Q → Q) ZI/Q II/Q ZLo1 TPS(RISE) TPS(FALL) 20 5 1.2:1 2.0 2.0 5.0 5.0 µA X:1 µs µs VPS(OFF) → VPS(ON) VPS(ON) → VPS(OFF) 4 Data Sheet P10099EJ4V0DS00 µPC8104GR PIN EXPLANATION PIN NO. 1 ASSIGNMENT Lo1in SUPPLY VOL. (V) − PIN VOL.(V) 0 FUNCTION AND APPLICATION Lo1 input for phase shifter. This input impedance is 50 Ω matched internally. Bypass of Lo1 input. This pin is grounded through internal capacitor. Open in case of single ended. Connect to the ground with minimum inductance. Track length should be kept as short as possible. Input for I signal. This input impedance is larger than 20 kΩ. Relations between amplitude and VCC/2 bias of input signal are following. VCC/2 (v) ≥ 1.35 ≥ 1.5 ≥ 1.75 Amp. (mVp-p) Note 400 600 1000 EQUIPMENT CIRCUIT 1 50 Ω 2 Lo1in − 2.4 2 3 GND for modulator 0 − 4 I VCC/2 − 4 5 5 I VCC/2 − Input for I signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. Relations between amplitude and VCC/2 bias of input signal are following. VCC/2 (v) ≥ 1.35 ≥ 1.5 ≥ 1.75 Amp. (mVp-p) Note 400 600 1000 6 Q VCC/2 − 7 Q VCC/2 − 7 6 16 MODout − 1.5 Output from modulator. This is emitter follower output. 16 Note In case of that I/Q input signals are single ended. Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations. Data Sheet P10099EJ4V0DS00 5 µPC8104GR PIN EXPLANATION PIN NO. 8 ASSIGNMENT GND for Upconverter SUPPLY VOL. (V) 0 PIN VOL.(V) − FUNCTION AND APPLICATION Connect to the ground with minimum inductance. Track length should be kept as short as possible. Bypass of Lo2 input. Grounded through external capacitor. EQUIPMENT CIRCUIT 10 12 11 Lo2in − 2.0 11 12 Lo2in − 0 Lo2 input of Up-converter. This pin is high impedance input. Supply voltage pin for Upconverter. RF output from Up-Converter. This pin is open collector output. 9 13 VCC for Upconverter RFout 2.7 to 5.5 − − 9 VCC 14 UpConin − 2.0 IF input for Up-converter. This pin is high impedance input. 15 UpConin − 2.0 Bypass of IF input. Grounded through external capacitor. 14 15 17 GND 0 − 18 − Connect to the ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can be controlled ON/SLEEP state with bias as follows; VP/S (v) 1.8 to 5.5 0 to 1.0 STATE ON SLEEP 19 19 Power Save VP/S 20 VCC for Modulator 2.7 to 5.5 − Supply voltage pin for modulator. Internal regulator can be kept stable condition of supply bias against the variable temperature or VCC. : Externally 6 Data Sheet P10099EJ4V0DS00 µPC8104GR EXPLANATION OF INTERNAL FUNCTION BLOCK 90° PHASE SHIFTER FUNCTION/OPERATION Input signal from Lo1 is send to digital circuit of T-type flip-flop through frequency doubler. Output signal from T-type F/F is changed to same frequency as Lo1 input and that have quadrature phase shift, 0°, 90°, 180°, 270°. These circuits have function of self phase correction to make correctly quadrature signals. BLOCK DIAGRAM from Lo1in ×2 ÷ 2 F/F BUFFER AMP. Buffer amplifiers for each phase signals to send to each mixers. MIXER Each signals from buffer amp. are quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to good performance for image rejection. I I Q Q ADDER Output signals from each mixers are added with adder and send to final amplifier. to MODout Data Sheet P10099EJ4V0DS00 7 µPC8104GR TYPICAL CHARACTERISTICS (TA = +25 °C) Unless otherwise specified VCC = VPS = 3 V, I/Q DC offset = I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mVp-p (single ended), PLo1in = −10 dBm, PLo2in = −10 dBm, (continuous wave) SUPPLY VOLTAGE vs CIRCUIT CURRENT 40 [UP CONVERTER BLOCK] SUPPLY VOLTAGE vs CONVERSION GAIN 35 10 RF : 1.9 GHz Lo2 : 1.66 GHz, –20 dBm IF : 240 MHz, –20 dBm VPS = VCC = 3 V 30 CG - Conversion Gain - dB ICC - Circuit Current - mA 25 5 20 15 0 10 5 VCC = VPS = 3 V RF None ICC Total ICC MOD ICC Up Con 0 1 2 3 4 5 6 VCC - Supply Voltage - V 0 0 1 2 3 4 VCC - Supply Voltage - V 5 6 8 Data Sheet P10099EJ4V0DS00 µPC8104GR [UP CONVERTER BLOCK] [UP CONVERTER BLOCK] INPUT POWER vs OUTPUT POWER, IM3 +10 OIP3 = +0.2 dBm 0 Lo2 INPUT POWER vs CONVERSION GAIN fRFout = 1.9 GHz fLo2in = 1.66 GHz fIFin = 240 MHz PIFin = –20 dBm VCC = VPS = 3 V 10 –10 Pout - Up Con. Output Power, IM3 - dBm CG - Conversion Gain - dB IM3 –20 5 –30 PRFout –40 0 –50 –40 –60 fRFout = 1.9 GHz fLo2in = 1.66 GHz PLo2in = –10 dBm fIFin1 = 240.0 MHz fIFin2 = 240.2 MHz VCC = VPS = 3V –30 –20 –10 0 PUpConin - Up Con. Input Power - dBm +10 –30 –20 –10 0 PLo2in - Lo2 Input Power - dBm +10 –70 –80 –40 Data Sheet P10099EJ4V0DS00 9 µPC8104GR [UP CONVERTER BLOCK] SUPPLY VOLTAGE vs CONVERSION GAIN RF : 900 MHz Lo2 : 1 140 MHz, –20 dBm IF : 240 MHz, –20 dBm VPS = VCC = 3 V [UP CONVERTER BLOCK] Lo2 INPUT POWER vs CONVERSION GAIN fRFout = 900 MHz fLo2in = 1 140 MHz fIFin = 240 MHz PIFin = –20 dBm 15 VCC = VPS = 3 V 15 GC - Conversion Gain - dB 10 CG - Conversion Gain - dB 10 5 5 0 1 2 3 4 VCC - Supply Voltage - V 5 6 –40 –30 –20 –10 0 PLo2in - Lo2 Input Power - dBm +10 [UP CONVERTER BLOCK] INPUT POWER vs OUTPUT POWER, IM3 +10 OIP3 = +7 dBm 0 [MODULATOR BLOCK] Lo1 INPUT POWER vs OUTPUT POWER, LOCAL LEAK, IMAGE REJECTION, I/Q 3RD ORDER INTERMODULATION DISTORTION 10 384 kbps RNYQ 0 α = 0.5 All zero –10 –10 –10 Pout - Up Con. Output Power, IM3 - dBm LOL (ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBc Pout PRFout –30 –20 LOL (ISOLO) –30 –30 –40 IM3 –50 –40 ImR –60 fRFout = 900 MHz fLo2in = 1 140 MHz PLo2in = –10 dBm fIFin1 = 240.0 MHz fIFin2 = 240.2 MHz VCC = VPS = 3 V –30 –20 –10 0 PUpConin - Up Con. Input Power - dBm +10 –50 –40 –70 –60 IM3I/Q –80 –40 –70 –30 –20 –10 0 PLo1in - Lo1 Input Power - dBm –50 +10 10 Data Sheet P10099EJ4V0DS00 PMODout - Modulator Output Power - dBm –20 –20 µPC8104GR [MODULATOR BLOCK] I/Q INPUT SIGNAL vs OUTPUT POWER, LOCAL LEAK, IMAGE REJECTION, I/Q 3RD ORDER INTERMODULATION DISTORTION 10 (PHS) 384 Kbps RNYQ α = 0.5 (0000) All zero –10 [MODULATOR BLOCK] Lo1 INPUT FREQUENCY vs OUTPUT POWER, LOCAL LEAK, IMAGE REJECTION, I/Q 3RD, ORDER INTERMODULATION DISTORTION LOL(ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBC –10 Pout –10 LOL (ISOLO) - Local Leak, ImR - Image Rejection, IM3 I/Q - dBc 0 ImR –30 –30 PMODout - Modulator Output Power - dBm –10 Pout –20 –40 LOL (ISOLO) –50 –40 –20 –50 –30 LOL (ISOLO) –40 ImR –50 –30 –60 IM3I/Q –60 –70 –40 50 100 200 500 –70 fLo1 - Lo1 Input Frequency - MHz –60 IM3I/Q –70 0 0.5 PI/Qin - I/Q Input Signal - Vp-p 1 –50 [MODULATOR + UP CONVERTER] I/Q INPUT SIGNAL vs VECTOR ERROR, MAGNITUDE ERROR, PHASE ERROR VCC = 3 V Lo1: 240 MHz –10 dBm Lo2: 1 660 MHz –8 dBm I/Q DC 1 500 mV AC 384 kbps RNYQ α = 0.5 PN9 [MODULATOR BLOCK] Lo1 INPUT FREQUENCY vs VECTOR ERROR, MAGNITUDE ERROR, PHASE ERROR VCC = 3 V Lo1: 15 dBm I/Q DC 1 500 mV AC 430 mVp-p 384 kbps RNYQ α = 0.5 PN9 10 10 ∆φ - Phase Error - deg. ∆ A - Magnitude Error - %rms ∆ M - Vector Error - %rms 7 ∆φ - Phase Error - deg. ∆ A - Magnitude Error - %rms ∆ M - Vector Error - %rms 7 5 ∆M ∆A 5 3 2 1 0 0 500 ∆φ 3 2 1 ∆M ∆A ∆φ 0 100 200 300 400 500 1 000 1 500 0 PI/Qin - I/Q Input Signal - mVp-p fLo1 - Lo1 Input Frequency - MHz Data Sheet P10099EJ4V0DS00 11 PMODout - Modulator Output - Power - dBm –20 –20 µPC8104GR [MODULATOR + UP CONVERTER] TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM REF 0.0 dBm 10 dB/ –ATT 10 dB REF 0.0 dBm 10 dB/ [MODULATOR BLOCK] TYPICAL SINE WAVE MODULATION OUTPUT SPECTRUM ATT 10 dB RBW 3 kHz VBW 10 kHz SWP 5.0 s RBW 1 kHz VBW 1 kHz SWP 2.0 s CENTER 1.9000000 GHz SPAN 200.0 kHz CENTER 240.0000 MHz SPAN 200.0 kHz 384 Kbps, RNYQ α = 0.5, MOD Pattern (0000), all zero. [MODULATOR + UP CONVERTER] [MODULATOR BLOCK] TYPICAL π/4 DQPSK MODULATION OUTPUT SPECTRUM 42 kbps, RNYQ α = 0.5, MOD Pattern REF 0.0 dBm 10 dB/ ATT 10 dB MARKER 1.4999000 GHz 72.00 dB REF –10.0 dBm 10 dB/ ADJ BS 21.0 kHz DL –10.0 dBm 1 2 3 ATT 0 dB MARKER 289.9000 MHz 76.50 dB ADJ BS 21.0 kHz DL 0.0 dBm 1 2 3 4 4 RBW 3 kHz VBW 3 kHz SWP 5.0 s CENTER 1.500000 GHz SPAN 500 kHz RBW 3 kHz VBW 3 kHz SWP 5.0 s CENTER 240.0000 MHz SPAN 500 kHz ∗∗∗ Multi Marker List ∗∗∗ No. 1: 1.4999000 GHz –72.00 dB No. 2: 1.4999500 GHz –66.00 dB No. 3: 1.5000500 GHz –68.75 dB No. 4: 1.5001000 GHz –72.00 dB ∗∗∗ Multi Marker List ∗∗∗ No. 1: 239.9000 MHz –76.50 dB No. 2: 239.9500 MHz –70.50 dB No. 3: 240.0500 MHz –71.00 dB No. 4: 240.1000 MHz –75.75 dB [MODULATOR + UP CONVERTER] [MODULATOR BLOCK] TYPICAL π/4 DQPSK MODULATION OUTPUT SPECTRUM 384 kbps, RNYQ α = 0.5, MOD Pattern (PN9) REF –10.0 dBm 10 dB/ ADJ BS 192 kHz DL –10.0 dBm 1 2 ATT 0 dB MARKER 1.899100 GHz 69.50 dB 3 4 REF –10.0 dBm 10 dB/ ADJ BS 192 kHz DL –10.0 dBm 1 2 ATT 0 dB MARKER 239.100 MHz 68.75 dB 3 4 RBW 3 kHz VBW 10 kHz SWP 5.0 s CENTER 1.900000 GHz SPAN 2.000 MHz ∗∗∗ Multi Marker List ∗∗∗ No. 1: 1.899100 GHz –69.50 dB No. 2: 1.899400 GHz –69.00 dB No. 3: 1.900600 GHz –69.00 dB No. 4: 1.900900 GHz –69.50 dB RBW 3 kHz VBW 10 kHz SWP 5.0 s CENTER 240.000 MHz SPAN 2.000 MHz ∗∗∗ Multi Marker List ∗∗∗ No. 1: 239.100 MHz –68.75 dB No. 2: 239.400 MHz –68.25 dB No. 3: 240.600 MHz –68.25 dB No. 4: 240.900 MHz –69.00 dB 12 Data Sheet P10099EJ4V0DS00 µPC8104GR RFout OUTPUT IMPEDANCE 3; 162.25 Ω –87.695 Ω 955.19 fF 1 900.000 000 MHz MARKER 3 1.9 GHz RF out Marker 1. 900 MHz 2. 1.5 GHz 3. 1.9 GHz 3 1 2 START 800.000 000 MHz STOP 2 000.000 000 MHz Lo2in INPUT IMPEDANCE 2; 20.184 Ω –113.66 Ω 843.51 fF 1 660.000 000 MHz MARKER 2 1.66 GHz Lo2 in Marker 1. 900 MHz 2. 1.66 GHz 3. 1.8 GHz 2 3 1 START 800.000 000 MHz STOP 1 900.000 000 MHz Data Sheet P10099EJ4V0DS00 13 µPC8104GR MODout OUTPUT IMPEDANCE 2; 49.244 Ω 13.58 Ω 9.0056 nH 240.000 000 MHz MARKER 2 240 MHz 2 3 MOD out (IF out) Marker 1 1. 100 MHz 2. 240 MHz 3. 400 MHz START 50.000 000 MHz STOP 500.000 000 MHz UP CON. in INPUT IMPEDANCE 2; 262.19 Ω –394.97 Ω 1.679 pF 240.000 000 MHz MARKER 2 240 MHz Up Con in (IF in) Marker 2 1 3 1. 100 MHz 2. 240 MHz 3. 400 MHz START 50.000 000 MHz STOP 500.000 000 MHz 14 Data Sheet P10099EJ4V0DS00 µPC8104GR Lo1in INPUT IMPEDANCE 2; 51.727 Ω –2.0059 Ω 330.5 pF 240.000 000 MHz MARKER 2 240 MHz Lo1 in Marker 2 31 1. 100 MHz 2. 240 MHz 3. 400 MHz START 50.000 000 MHz STOP 500.000 000 MHz TEST CIRCUIT (fRF = 1.9 GHz) 1 000 pF Lo2 100 pF S.G VCC 10 kΩ 100 pF 17 GND 16 MOD out 15 Up Con in 14 Up Con in 13 VCC 12 Lo2 in 11 Lo2 in 100 pF fLo2 = 1.5 to 1.8 GHz PIN = –10 dBm 20 VCC 19 Power Save Lo1 in 18 GND Lo1 in RFout 9 GND GND 1 Lo1 S.G 1000 pF fLo1 = 100 to 400 MHz PIN = –10 dBm 2 Open 3 4 5 6 7 8 10 GND Q Q I I 0.1 µ H S.P.A L C I I Q Q I/Q Signal Generator f : DC to hundreds kHz A : 0.5 Vp-p (I, Q only) V : 1.5 V (I, I, Q, Q) 100 pF fRF = 1.9 GHz L: (Micro Stripline) C: around 3 pF Data Sheet P10099EJ4V0DS00 15 µPC8104GR TEST BOARD P.S. VCC (MOD) 10 000 pF 10 000 pF VCC (Up Con.) 10 000 pF 1 000 pF 10 K 1 000 pF Lo1 1 000 pF 100 pF Lo2 1 000 pF 3 pF In case of this test board, the output signal from MOD. is directly connected to the up converter input port through 1000 pF, which is DC coupling. We recommend to insert a low pass filter between MOD output and up converter input port to reject harmonics of the Lo1 signal and to avoid saturation of the up converter. GND fRF = 1.9 GHz fLo2 = 1.66 GHz fLo1 = 240 MHz 100 pF 100 pF 3 pF RFout 100 pF 100 nH (OPEN) 1 000 pF Iin 10 000 pF Qin I 10 000 pF Q 16 Data Sheet P10099EJ4V0DS00 µPC8104GR PACKAGE DIMENSIONS 20 PIN PLASTIC SSOP (225 mil) (UNIT: mm) 20 11 detail of lead end 3˚–3˚ +7˚ 1 6.7 ± 0.3 10 1.8 MAX. 1.5 ± 0.1 6.4 ± 0.2 4.4 ± 0.1 1.0 ± 0.2 0.5 ± 0.2 0.65 0.22 –0.05 0.1 ± 0.1 +0.10 0.15 0.10 M 0.15 0.575 MAX. +0.10 –0.05 NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. Data Sheet P10099EJ4V0DS00 17 µPC8104GR NOTE ON CORRECT USE (1) Observe precautions for handling because of electrostatic sensitive devices. (2) Form a ground pattern as wide as possible to keep the minimum ground impedance (to prevent undesired oscillation). (3) Keep the track length of the ground pins as short as possible. (4) Connect a bypass capacitor (e.g. 1 000 pF) to the VCC pin. (5) I, Q DC offset voltage should be same as the I, Q DC offset voltage (to prevent changing the local leak level with power save control.) RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. µPC8104GR Soldering Method Infrared ray reflow Soldering Conditions Peak package’s surface temperature: 235 °C or below, Reflow time: 30 seconds or below (210 °C or higher), Note Number of reflow process: 3, Exposure limit : None Peak package’s surface temperature: 215 °C or below, Reflow time: 40 seconds or below (200 °C or higher), Note Number of reflow process: 3, Exposure limit : None Solder temperature: 260 °C or below Flow time: 10 seconds or below, Note Number of reflow process: 1, Exposure limit : None Terminal temperature: 300 °C or below Flow time: 3 seconds/pin or below, Note Exposure limit : None Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating method Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and relative humidity at 65 % or less. Caution Apply only a single process at once, except for “Partial heating method”. For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E) The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. 18 Data Sheet P10099EJ4V0DS00 µPC8104GR [MEMO] Data Sheet P10099EJ4V0DS00 19 µPC8104GR • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • N o part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • D escriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8