UPD168002

DATA SHEET MOS INTEGRATED CIRCUIT µ PD168002 MONOLITHIC 6-CHANNEL H-BRIDGE DRIVER DESCRIPTION The µ PD168002 is a monolithic 6-channel H-bridge driver that consists of a CMOS control circuit and a MOS output stage. It can reduce the current consumption and the voltage loss at the output stage compared with conventional driver using bipolar transistors, thanks to employment of a MOS process. The µ PD168002 employs P-channel MOS FET in the output stage, and is eliminated the charge pump circuit. Therefore, the circuit current consumption during operation can be significantly reduced. The package is a 48-pin TQFP that helps reduce the mounting area and height. The µ PD168002 can be used to drive one stepping motor and four DC motors, and is suitable for the motor driver of CD-ROM/CD audios. FEATURES • Six H-bridge circuits employing power MOS FET • Low current consumption due to elimination of charge pump circuit • Input logic frequency: 100 kHz supported • 3 V power supply supported for logic Minimum operating supply voltage: 2.7 V • 5 V, 10 V power supply supported for motor ch1, ch2, ch5 and ch6: 10 V driving ch3 and ch4: 5 V driving • Undervoltage lockout circuit Shuts down the internal circuit at VDD = 1.7 V TYP. • Overheat protection circuit • 48-pin TQFP (□7 mm) ORDERING INFORMATION Part Number Package 48-pin plastic TQFP (fine pitch) (7 x 7) µ PD168002GA-9EU The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16040EJ1V0DS00 (1st edition) Date Published November 2003 NS CP(K) Printed in Japan 2002 µ PD168002 1. BLOCK DIAGRAM PGND PGND PGND 25 OUT5A OUT5B OUT6A 37 PGND OUT2A VM2 OUT2B PGND OUT1A VM1 OUT1B PGND IN1A IN1/IN1B EN12/IN2A 48 36 OUT6B LGND (NC) (NC) VM5 VM6 24 PGND OUT4A Sled H-bridge 2 Spindle H-bridge 5 Loading H-bridge 6 Tracking H-bridge 4 VM4 OUT4B PGND OUT3A Sled H-bridge 1 H-bridge ch3 to ch6 control circuit Focus H-bridge 3 VM3 OUT3B PGND H-bridge ch1 to ch2 control circuit STB6 STB5 STB34 13 1 12 IN2/IN2B IN3A IN3B IN4A IN4B IN5A IN5B IN6A IN6B SEL12 Cautions 1. Be sure to connect all of the pins which have more than one. 2. A pull-down resistor (50 to 200 kΩ) is internally connected to the logic input pins. Logic input pins: IN1A, IN1/IN1B, EN12/IN2A, IN2/IN2B, IN3A, IN3B, IN4A, IN4B, IN5A, IN5B, IN6A, IN6B, SEL12, STB12, STB34, STB5 and STB6 3. The power supply pins for motor, VM1 and VM2, VM3 and VM4, and VM5 and VM6, are connected each other inside. These pins must be applied from the same potential. 2 Data Sheet S16040EJ1V0DS STB12 VDD µ PD168002 2. PIN FUNCTIONS Package: 48-pin plastic TQFP (fine pitch) (7 x 7) (1/2) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name IN2/IN2B IN3A IN3B IN4A IN4B VDD IN5A IN5B IN6A IN6B SEL12 STB12 STB34 STB5 STB6 PGND OUT3B VM3 OUT3A PGND OUT4B VM4 OUT4A PGND PGND OUT6B VM6 OUT6A PGND OUT5B VM5 OUT5A PGND LGND (NC) ch2 input pin or ch2 input pin B ch3 input pin A ch3 input pin B ch4 input pin A ch4 input pin B Logic power supply pin ch5 input pin A ch5 input pin B ch6 input pin A ch6 input pin B ch1 and ch2 input logic selection pin ch1 and ch2 standby pin ch3 and ch4 standby pin ch5 standby pin ch6 standby pin GND pin ch3 output B ch3 power supply pin ch3 output A GND pin ch4 output B ch4 power supply pin ch4 output A GND pin GND pin ch6 output B ch6 power supply pin ch6 output A GND pin ch5 output B ch5 power supply pin ch5 output A GND pin GND pin Unused Function Caution Be sure to connect all of the pins which have more than one. Data Sheet S16040EJ1V0DS 3 µ PD168002 (2/2) Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name (NC) PGND OUT2A VM2 OUT2B PGND OUT1A VM1 OUT1B PGND IN1A IN1/IN1B EN12/IN2A Unused GND pin ch2 output A ch2 power supply pin ch2 output B GND pin ch1 output A ch1 power supply pin ch1 output B GND pin ch1 input pin A ch1 input pin or ch1 input pin B ch1 and ch2 control pin or ch2 input pin A Function Caution Be sure to connect all of the pins which have more than one. 4 Data Sheet S16040EJ1V0DS µ PD168002 3. STANDARD CONNECTION EXAMPLE Spindle motor Loading motor M M PGND PGND 37 PGND OUT2A VM2 Sled motor M OUT2B PGND OUT1A VM1 OUT1B 8V PGND IN1A IN1/IN1B EN12/IN2A 48 36 PGND OUT5A OUT5B OUT6A OUT6B LGND (NC) (NC) VM5 VM6 25 24 PGND OUT4A Sled H-bridge 2 Spindle H-bridge 5 Loading H-bridge 6 Tracking H-bridge 4 VM4 OUT4B PGND OUT3A Tracking coil 5V Sled H-bridge 1 H-bridge ch3 to ch6 control circuit Focus H-bridge 3 VM3 OUT3B PGND STB6 STB5 STB34 13 Focus coil H-bridge ch1 to ch2 control circuit 1 12 IN2/IN2B IN3A IN3B IN4A IN4B IN5A IN5B IN6A IN6B SEL12 STB12 VDD 3V Caution This diagram is the example of connection and is not what was created as a purpose of mass production. Data Sheet S16040EJ1V0DS 5 µ PD168002 4. FUNCTION OPERATION TABLE 4.1 Relationship between SEL Pin and Input Pins SEL pin L H 46-pin Unused ch1 input pin IN1A 47-pin ch1 input pin IN1 ch1 input pin IN1B 48-pin ch1 and ch2 control pin EN12 ch2 input pin IN2A 1-pin ch2 input pin IN2 ch2 input pin IN2B Remark L: Low level, H: High level 4.2 ch1 and ch2 Input/output Truth Table (1) SEL12 = L Input EN12 L H H IN x L H OUTA Z H L Output OUTB Z L H Stop (output high impedance) Forward revolution (OUTA → OUTB) Reverse revolution (OUTB → OUTA) Output Status Remark x: High level or low level, Z: Output high impedance (2) SEL12 = H Input INA L L H H INB L H L H OUTA L L H H Output OUTB L H L H Stop (short brake) Reverse revolution (OUTB → OUTA) Forward revolution (OUTA → OUTB) Stop (short brake) Output Status 4.3 ch3 to ch5 Input/output Truth Table Input INA L L H (H) INB L H L (H) OUTA L L H (H) Output OUTB L H L (H) Stop (short brake) Reverse revolution (OUTB → OUTA) Forward revolution (OUTA → OUTB) Stop (short brake) Output Status Caution At ch3 to ch5, inputting INA = H and INB = H prohibits. 4.4 ch6 Input/output Truth Table Input INA L L H H INB L H L H OUTA L L H H Output OUTB L H L H Stop (short brake) Reverse revolution (OUTB → OUTA) Forward revolution (OUTA → OUTB) Stop (short brake) Output Status 6 Data Sheet S16040EJ1V0DS µ PD168002 5. STANDBY FUNCTION The µ PD168002 realizes a standby function by combination of an input signal. The specified output is set to high impedance (Hi-Z) status by setting STB to low level. Each pin can be independently controlled, and can be set to standby status of the self current consumption of the IC reduced as much as possible by setting all pins to low level. In the standby status, the overheat protection circuit and the undervoltage lockout circuit do not operate. Pin Function ch1 ch2 Hi-Z ON Output Status when Pin = L ch3 ON Hi-Z ch4 ON Hi-Z ch5 ON ON ch6 ON ON STB12 STB34 Sled block standby Focus and tracking block standby Hi-Z ON STB5 STB6 Spindle block standby Loading block standby ON ON ON ON ON ON ON ON Hi-Z ON ON Hi-Z Remark ON: Status which can turn on output, Hi-Z: High impedance 6. OPERATION WAVEFORM EXAMPLES (1) Example of the clockwise revolution of the right figure when 2-phase diving Phase A IN (IN1) Phase B IN (IN2) (2) OUTA → OUTB ch1 OUTA → OUTB ch2 (2) Example of the counter-clockwise revolution of the right figure when 2-phase diving Phase A IN (IN1) OUTB → OUTA OUTB → OUTA (1) Phase B IN (IN2) Remark SEL12 = L, EN12 = H Data Sheet S16040EJ1V0DS 7 µ PD168002 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol VDD VM Control block Motor block (ch3 and ch4) Motor block (ch1, ch2, ch5 and ch6) Input voltage Output pin voltage 1 Output pin voltage 2 DC output current 1 DC output current 2 Instantaneous output current 1 Instantaneous output current 2 Power consumption Peak junction temperature Storage temperature VIN VOUT1 VOUT2 ID(DC)1 ID(DC)2 ID(pulse)1 ID(pulse)2 PT Tch(MAX) Tstg Motor block (ch3 and ch4) Motor block (ch1, ch2, ch5 and ch6) DC (ch3 to ch5) DC (ch1, ch2 and ch6) PW < 10 ms, Duty Cycle ≤ 20% (ch3 to ch5) PW < 10 ms, Duty Cycle ≤ 20% (ch1, ch2 and ch6) Condition Rating −0.5 to +6.0 −0.5 to +6.0 −0.5 to +12.0 −0.5 to VDD + 0.5 6.2 12.2 ±0.3 ±0.15 ±0.6 ±0.3 1.0 150 −55 to +150 Unit V V V V V V A/ch A/ch A/ch A/ch W °C °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol VDD VM Control block Motor block (ch3 and ch4) Motor block (ch1, ch2, ch5 and ch6) Input voltage DC output current 1 DC output current 2 Instantaneous output current 1 Instantaneous output current 2 VIN ID(DC)1 ID(DC)2 ID(pulse)1 ID(pulse)2 DC (ch3 to ch5) DC (ch1, ch2 and ch6) PW < 10 ms, Duty Cycle ≤ 20% (ch3 to ch5) PW < 10 ms, Duty Cycle ≤ 20% (ch1, ch2 and ch6) Logic input frequency Operating temperature range fIN TA −40 100 85 kHz °C Condition MIN. 2.7 2.7 6.0 0 −0.2 −0.1 −0.4 −0.2 TYP. MAX. 5.5 5.5 11.0 VDD +0.2 +0.1 +0.4 +0.2 Unit V V V V A/ch A/ch A/ch A/ch 8 Data Sheet S16040EJ1V0DS µ PD168002 Electrical Characteristics (Unless otherwise specified, TA = 25°C, VDD = 3 V, VM = 5 V (ch3 and ch4), VM = 8 V (ch1, ch2, ch5 and ch6) ) Parameter VDD pin current in standby mode VDD pin current in during operation VM pin current in during operation Symbol IDD(STB) IDD(ACT) IM Output with no load, IN pin, EN pin: Low level High-level input current Low-level input current Input pull-down resistance High-level input voltage Low-level input voltage H-bridge on-state resistance 1 (ch1, ch2 and ch5) H-bridge on-state resistance 2 (ch3 and ch4) H-bridge on-state resistance 3 (ch6) Output leakage current IM(off) Ron3 Ron2 IIH IIL RIND VIH VIL Ron1 2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V IM = 0.1 A (ch1 and ch2), IM = 0.2 A (ch5), sum of upper and lower stages IM = 0.2 A, sum of upper and lower stages IM = 0.1 A, sum of upper and lower stages Per VM pin, All control pin: Low level (VM = MAX. value in the recommended range) Low-voltage detection voltage Output turn-on time Output turn-off time Note Note Condition All control pin: Low level MIN. TYP. MAX. 1.0 1.0 100 Unit µA mA µA µA µA kΩ V VIN = VDD VIN = 0 V −1.0 50 0.7 x VDD 60 200 0.3 x VDD 2.0 3.0 V Ω 1.2 2.0 Ω 3.5 5.0 Ω 10 µA VDDS ton2 toff2 IM = 0.1 A (ch1, ch2 and ch6), Refer to Figure 7−1. H-bridge Switching Waveform (when SEL12 = L) and Figure 7−2. H-bridge Switching Waveform (when SEL12 = H) . 0.2 0.05 1.7 0.6 0.3 2.5 2.0 1.0 V µs µs Output turn-on time Output turn-off time Note Note ton1 toff1 IM = 0.2 A (ch3 to ch5), Refer to Figure 7−2. H-bridge Switching Waveform (when SEL12 = H) (only when VINB = L) . 0.05 0.05 0.15 0.2 1.0 1.0 µs µs Note For the turn-on time and the turn-off time, to fix one of two input pins to low level is conditions. Remark The overheat protection circuit operates under Tch > 150°C. All outputs goes high impedance in the protection status. Note that the overheat protection circuit and the undervoltage lockout circuit do not operate in the standby status. Data Sheet S16040EJ1V0DS 9 µ PD168002 Switching Characteristics Waveform Figure7−1. H-bridge Switching Waveform (when SEL12 = L) 100% EN12 50% 50% 0% ton tr 90% IOUT 90% toff tf 10% 10% 100% VIN 0% ton toff 100% 90% IOUT 0% tf 50% 10% −10% −50% −90% tr −100% −50% −90% tf 50% 10% −10% 90% toff 100% ton 50% 50% tr Remark The high impedance period of about 50 ns is prepared for the through-current prevention at the time of mode switching. The tr (rise time) is designed as 50 ns, and the tf (fall time) is designed as about 50 ns. 10 Data Sheet S16040EJ1V0DS µ PD168002 Figure7−2. H-bridge Switching Waveform (when SEL12 = H) When VINB = L 100% 90% VINA 10% ton tr 90% IOUT toff tf 90% OUT1A → OUT1B Hi-Z 10% 10% Hi-Z When VINB = H Note 100% 90% VINA 10% toff OUT1B → OUT1A 90% IOUT tr tr ton OUT1B → OUT1A 90% 10% Brake 10% Note The conditions of VINB = H is valid only at ch1, ch2 and ch6. The through current may be flowed, if the switching operation is performed under the conditions of VINB = H at ch3 to ch5. Remark The high impedance period of about 50 ns is prepared for the through-current prevention at the time of mode switching. The tr (rise time) is designed as 50 ns, and the tf (fall time) is designed as about 50 ns. Data Sheet S16040EJ1V0DS 11 µ PD168002 8. PACKAGE DRAWING 48-PIN PLASTIC TQFP (FINE PITCH) (7x7) A B 36 37 25 24 detail of lead end S C D Q 48 1 13 12 R F G H P I M J K S N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 9.0 ± 0.2 7.0 ± 0.2 7.0 ± 0.2 9.0 ± 0.2 0.75 0.75 0.22 + 0.05 − 0.04 0.10 0.5 (T.P.) 1.0 ± 0.2 0.5 ± 0.2 0.145 + 0.055 − 0.045 0.10 1.0 ± 0.1 0.1 ± 0.05 +7° 3°−3° 1.27 MAX. S48GA-50-9EU-2 12 Data Sheet S16040EJ1V0DS µ PD168002 9. RECOMMENDED SOLDERING CONDITIONS The µ PD168002 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Surface Mount Device µ PD168002GA-9EU: 48-pin plastic TQFP (fine pitch) (7 x 7) Process Infrared reflow Conditions Package peak temperature: 235°C, Time: 60 seconds MAX. (at 210°C or higher) , Count: Three times or less, Exposure limit: None, Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Symbol IR35-00-3 Caution Do not use different soldering methods together (except for partial heating) . Data Sheet S16040EJ1V0DS 13 µ PD168002 N OTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 14 Data Sheet S16040EJ1V0DS µ PD168002 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades on NEC Semiconductor Devices (C11531E) • T he information in this document is current as of November, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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