UPD6376

DATA SHEET MOS INTEGRATED CIRCUIT µPD6376 AUDIO 2-CHANNEL 16-BIT D/A CONVERTER The µPD6376 is an audio 2-channel 16-bit D/A converter. The µPD6376 has low sound quality deterioration by employing the resistor string configuration and 0-point offset, and low power consumption by using the CMOS process. It operates on a single 5-V power supply, and it is pincompatible with the µPD6372 when Pin 1 is low level or open. FEATURES • Single 5-V power supply • CMOS structure • On-chip output operational amplifier circuit • On-chip 0-point offset circuit • Resistor string configuration • 8 fS (2 ch × 400 kHz) supported • On-chip 2-channel DAC • L-R in-phase output ORDERING INFORMATION Part Number Package 16-pin plastic SOP (300 mil) µPD6376GS The information in this document is subject to change without notice. Document No. S12799EJ5V0DS00 (5th edition) (Previous No. IC-2531) Date Published December 1997 N Printed in Japan The mark shows major revised points. © 1991 µPD6376 BLOCK DIAGRAM Digital power supply block Analog power supply block 10 L.REF MAIN DAC 11 L.OUT SHIFT REGISTER LATCH LRCK/WDCK 13 LRSEL/RSI 14 SI/LSI 15 CLK 16 4/8 fS SEL 1 SUB DAC TIMING GENERATOR SUB DAC 6 R.OUT MAIN DAC 9 R.REF D.GND 2 3 NC 4 D.VDD 5 12 7 8 A.VDD A.GND 2 µPD6376 PIN CONFIGURATION (Top View) 16-Pin Plastic SOP (300 mil) 4/8 fS SEL D.GND NC D.VDD A.GND R.OUT A.VDD A.VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK SI/LSI LRSEL/RSI LRCK/WDCK A.GND L.OUT L.REF R.REF 3 µPD6376 1. PIN FUNCTIONS Pin No. 1 Symbol 4/8 fS SEL Name I/O Input Function When this pin is Low or leaves Open, L-ch data and R-ch data is input in time-division from Pin 15. When this pin is High, L-ch data is input from Pin 15, and R-ch data is input from Pin 14. (Pulled down in IC with 100-kΩ resistor) GND pin of logic block Not connected to internal chip Power supply pin to logic block GND pin to analog block Right analog signal output pin Power supply pin to analog block 2 3 4 5 6 7 8 9 10 11 12 13 D.GND NC D.VDD A.GND R.OUT A.VDD A.VDD R.REF L.REF L.OUT A.GND LRCK/WDCK Digital GND Non Connection Digital VDD Analog GND R-ch OUTPUT Analog VDD Analog VDD R-ch Voltage Reference L-ch Voltage Reference L-ch OUTPUT Analog GND Left/Right Clock WORD Clock –– –– –– –– Output –– –– Reference voltage pin. Normally connected to A. GND through via capacitor to lower impedance Output –– Input Left analog signal output pin GND pin of analog block When Pin Functions When Pin Functions 1 is Low or leaves Open: as L-R judgment signal input pin. 1 is High: as input data word judgment signal input pin. 14 LRSEL/RSI Left/Right Selection R-ch Series Input Input When Pin 1 is Low or leaves Open: Functions as pin to select L-R polarity for LRCK signal. When LRCK signal is High, set LRSEL pin to Low to input L-ch data; When LRCK signal is LOW, set LRSEL pin to High to input L-ch data. When Pin 1 is High: Functions as R-ch serial data input pin. 15 SI/LSI Series Input L-ch Series Input Input When Pin 1 is Low or Open: Functions as L-ch and R-ch serial data input pin alternately. When Pin 1 is High: Functions as L-ch serial data input pin. Input pin for read clock of serial input data 16 CLK CLOCK Input 4 µPD6376 2. INPUT SIGNAL FORMAT • Input data must be input as 2’s complement, MSB first. 2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See the table below. 2’s Complement (MSB) 0111 0111 1111 1111 ······ 1111 1111 (LSB) 1111 1110 L.OUT, R.OUT Pin Voltage TYP. (V) (Reference Values)Note 2.6 ·················· Decimal Number +32767 +32766 ······ 0000 0000 1111 0000 0000 1111 ······ 0000 0000 1111 0001 0000 1111 +1 0 –1 ······ 1.6 ·················· 1000 1000 0000 0000 0000 0000 0001 0000 –32767 –32768 0.6 Note When A.VDD = 5.0 V Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature. • Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of CLK. • CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same as 1 clock cycle. 5 µPD6376 2.1 Supplying Clock to CLK even outside Sample Data Interval 2.1.1 Serial data input (Pin 1 is Low or Open) Synchronize the reverse timing of LRCK with the falling edge of CLK upon completion of LSB input (Point A in Figure 2-1). Figure 2-1 Timing Chart for Serial Data Input A Interval of 1 sample data CLK SI LRCK LSB 16 MSB 12 3 4 5 6 7 8 LSB 9 10 11 12 13 14 15 16 MSB 12 3 4 A 2.1.2. Inputting parallel data (Pin 1 is High) Synchronize the timing of the falling edge of WDCK with the falling edge of CLK upon completion of LSB input of data (LSI, RSI) (Point A in Figure 2-2.). Figure 2-2 Parallel Data Input Timing Chart A A CLK LSI RSI WDCK LSB 16 LSB 16 MSB 12 MSB 12 3 3 4 4 5 5 6 6 7 7 8 8 LSB 9 10 11 12 13 14 15 16 LSB 9 10 11 12 13 14 15 16 MSB 12 MSB 12 6 µPD6376 2.2 Supplying Clock to CLK only during Sample Data Interval The analog outputs of the L.OUT and R.OUT pins are updated after the input of 4.5 clocks following data input. (See 4. ELECTRICAL CHARACTERISTICS, Timing Charts 1 and 2.) 2.2.1 Inputting serial data (Pin 1 Low or Open) Place the LRCK reverse timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-3) and the next MSB input start time (Point B in Figure 2-3) (so as to include Points A and B). Figure 2-3 Timing Chart of Serial Data Input A B 1-sample data interval CLK SI LRCK LRCK reverse interval LRCK reverse interval LSB 16 MSB 12 3 4 5 6 7 8 LSB 9 10 11 12 13 14 15 16 MSB 12 3 4 A B 2.2.2 Inputting parallel data (Pin 1 High) Place the WDCK falling edge timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-4) and the next MSB input start time (Point B in Figure 2-4) (so as to include Points A and B). Place the WDCK rising edge timing between the third falling edge of CLK from MSB input completion (Point C in Figure 2-4) and the falling edge of CLK upon LSB input start (Point D in Figure 2-4) (so as to include Points C and D). Figure 2-4 Timing Chart of Parallel Data Input A B C DA B CLK LSI RSI WDCK WDCK falling edge interval WDCK rising edge interval WDCK falling edge interval LSB 16 LSB 16 MSB 12 MSB 12 3 3 4 4 5 5 6 6 7 7 8 8 LSB 9 10 11 12 13 14 15 16 LSB 9 10 11 12 13 14 15 16 MSB 12 MSB 12 7 µPD6376 3. USAGE CAUTIONS Insertion of a muting circuit in the next stage after the µPD6376 is recommended. If no muting circuit is inserted in the next stage, shock noise may be generated when power is applied. 8 µPD6376 4. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Output pin voltage Logic input voltage Operating ambient temperature Storage temperature Symbol VDD VOUT VIN TA Tstg Rating –0.3 to +7.0 –0.3 to VDD+0.3 –0.3 to VDD+0.3 –20 to +75 –40 to +125 Unit V V V °C °C Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the device reliability may be impaired. The absolute maximum ratings are values that may physically damage the product. Be sure to use the product within the ratings. Recommended Operating Range Parameter Supply voltage Logic input voltage (High) Logic input voltage (Low) Operating temperature range Output load resistance Conversion frequency Clock frequency Clock pulse width SI, LRCK set time SI, LRCK hold time Symbol VDD VIH VIL TA RL fS fCLK fSCK tDC tCD 40 12 12 R.OUT or L.OUT pin Condition MIN. 4.5 0.7VDD 0 –20 5 400 10 +25 TYP. 5.0 MAX. 5.5 VDD 0.3VDD +75 Unit V V V °C kΩ kHz MHz ns ns ns Electrical Characteristics (TA = 25°C, VDD = +5 V) Parameter Resolution Total harmonic distortion 1 Total harmonic distortion 2 Full-scale output voltage Cross talk S/N ratio Dynamic range Circuit current Symbol RES THD1 THD2 VFS C.T S/N D.R IDD 0 dB per channel, fIN = 1 kHz JIS-A fIN = 1 kHz, –60 dB fIN = 1 kHz, 0 dB 85 96 92 6.0 12 fIN = 1 kHz, 0 dB fIN = 1 kHz, –20 dB Condition MIN. TYP. 16 0.04 0.1 2.0 95 0.09 0.3 2.3 MAX. Unit Bit % % Vp-p dB dB dB mA 9 10 TIMING CHART 1 • When Pin 1 is Low or Open (serial input) 4.5 clocks CLK LSB 16 MSB 1 2 3 4 N LRCK (L-ch) Note LRCK (L-ch) (R-ch) 5 6 7 8 LSB 9 10 11 12 13 14 15 16 MSB 1 2 3 4 N (R-ch) 5 6 7 8 9 10 11 SI L.OUT N–1 R.OUT N–1 Analog output update Note When the LRCK signal is High, set the LRSEL pin to Low to input L-ch data. When the LRCK signal is Low, set the LRSEL pin to High to input L-ch data. tSCK tSCK CLK tDC SI tCD CLK LRCK tDC tCD µPD6376 TIMING CHART 2 • When Pin 1 is High (parallel input) 4.5 clocks CLK LSB 16 LSB 16 MSB 1 MSB 1 2 3 2 3 4 N 4 N WDCK 5 6 7 8 5 6 7 8 LSB 9 10 11 12 13 14 15 16 LSB 9 10 11 12 13 14 15 16 MSB 1 MSB 1 2 3 4 N+1 5 6 7 8 9 10 11 2 3 4 5 6 7 8 9 10 11 LSI RSI L.OUT N–1 N R.OUT N–1 N Analog output update tSCK tSCK CLK tDC SI tCD CLK WDCK µPD6376 tDC tCD 11 µPD6376 Typical Characteristics (TA = 25°C) THD vs. Frequency Characteristics 1.0 0.5 0.3 0.2 THD (%) THD (%) THD vs. VDD Characteristics 1.0 fS = 88.2 kHz fIN = 1 kHz, 0 dB 0.5 0.3 Note fS = 88.2 kHz VDD = 5.0 V Note 0.1 0.05 (–20 dB) 0.2 0.1 (Full Scale) 0.03 0.02 0.01 0.1 0.05 0.03 0.2 0.3 0.5 1 23 5 10 20 0.02 0.01 0 Frequency f (kHz) 3.0 4.0 VDD (V) 5.0 6.0 7.0 Voltage Gain vs. Frequency Characteristics Note fS = 88.2 kHz VDD = 5.0 V 10.0 THD vs. VOUT Characteristics fS = 88.2 kHz fIN = 1 kHz VDD = 5.0 V Note Voltage Gain (dB) 0 5.0 3.0 –5 2.0 1.0 –10 0.1 Frequency f (kHz) THD (%) 0.2 0.3 0.5 1 23 5 10 20 0.5 0.3 0.2 THD vs. RL Characteristics 10 fS = 88.2 kHz fIN = 1 kHz, 0 dB VDD = 5.0 V THD (%) 0.1 0.05 0.03 1.0 Note 0.02 0.1 0.01 –60 –50 –40 –30 VOUT (dB) –20 –10 0 0.01 100 1k 10 k 100 k 1M Load Resistance RL (Ω) Note 20 kHz low-pass filter: 298BLR-010N (Toko) used 12 µPD6376 5. APPLICATION CIRCUIT EXAMPLE (1) fS to 4 fS mode (L/R data serial input mode) Note 384 fS LRCK SI CLK 8 7 6 5 4 3 2 1 1 2 +10 V 1000 pF +5 V 47 µF 47 µF + + 9 10 µF + 5.6 kΩ 5.6 kΩ + OP Amp. 16 15 14 13 12 11 10 100 kΩ +5 V 1000 pF 5.6 kΩ +5 V 1000 pF 5.6 kΩ 5.6 kΩ 1000 pF 1/2 – + 22 µF µ PD6376GS 3 4 5 6 7 8 5.6 kΩ +10 V OP Amp. 22 µF + 2/2 5.6 kΩ L-ch OUT 100 kΩ NPC SM5807 9 10 11 12 13 14 15 16 +5 V 0.1 µ F +5 V 0.1 µ F 10 µ F + + – 100 kΩ +5 V 5.6 kΩ +5 V R-ch OUT 100 kΩ . Note Assuming secondary active LPF (Gain: K = 2, quality factor: Q = 1, cutoff frequency: f C = 30 kHz) . oversampling, the attenuation characteristics are moderate. If oversampling is not performed, use a high-order filter. Remark Operational amplifier (OP Amp.): µPC4558 (2) 8 fS mode (L/R data parallel input mode) Note LRCK SI CLK 1 2 3 4 5 28 27 26 25 24 23 22 NPC SM5813 21 20 19 18 17 16 15 +10 V 1000 pF 47 µF 47 µ F 16 15 14 13 12 11 10 10 µF + 5.6 kΩ 5.6 kΩ + OP Amp. + + 9 100 kΩ +5 V 1000 pF 5.6 kΩ +5 V 1000 pF 5.6 kΩ 5.6 kΩ 1/2 – + 22 µF 384 fS 6 7 8 9 10 11 12 13 14 µ PD6376GS +5 V 1 2 3 4 5 6 7 8 5.6 kΩ +10 V OP Amp. 22 µF L-ch OUT 100 kΩ +5 V 0.1 µ F 0.1 µ F 10 µ F + + 1000 pF 100 kΩ +5 V 5.6 kΩ +5 V 2/2 – + 5.6 kΩ R-ch OUT 100 kΩ . Note Secondary active LPF (K = 2, Q = 1, fC = 30 kHz) . Remark Operational amplifier (OP Amp.): µPC4558 13 µPD6376 6. MEASURING CIRCUIT EXAMPLE 3.6 kΩ VDD +5 V 298BLR-010N (TOKO) 5.6 kΩ + LPF 100 µF + 47 µ F 298BLR-010N (TOKO) 0.1 µ F 100 µF + LPF 5.6 kΩ 5.6 kΩ – 2/2 1/2 100 µF + OP Amp. 100 kΩ 200 Ω + 5.6 kΩ 47 µF 47 µF µPD6376 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 3.6 kΩ L R + + 3.6 kΩ – h.p. 339 A (30 kHz LPF ON) + LRCK SI CLK 3.6 kΩ 0.1 µ F OP Amp. VREF (+2.5 V) Sampling frequency fS = 88.2 kHz 14 100 kΩ Anritsu MG22A 2/2 100 µF + 200 Ω µPD6376 7. PACKAGE DRAWINGS 16 PIN PLASTIC SOP (300 mil) 16 9 detail of lead end 1 A 8 H I J F G K E C D M N M B L NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 10.46 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 –0.05 0.1±0.1 1.8 MAX. 1.55 7.7±0.3 5.6 1.1 0.20 +0.10 –0.05 0.6±0.2 0.12 0.10 ° 3 ° +7° –3 P INCHES 0.412 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 –0.003 0.004±0.004 0.071 MAX. 0.061 0.303±0.012 0.220 0.043 0.008 +0.004 –0.002 0.024 +0.008 –0.009 0.005 0.004 ° 3 ° +7° –3 P16GM-50-300B-4 15 µPD6376 8. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met when performing soldering for the µPD6376. For more detailed information, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than the recommended conditions, please consult with an NEC sales representative. Surface Mount Type Soldering Conditions µPD6376GS: 16-pin Plastic SOP (300 mil) Soldering Process Infrared reflow Soldering Conditions Peak package temperature: 230°C, Time: 30 seconds max. (at 210°C or higher), Count: Once Peak package temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Once Pin temperature: 300°C or less, Time: 3 seconds max. (per pin row) Symbol IR30-00-1 VPS VP-15-00-1 Pin Partial heating –– Caution Do not use different soldering methods together (except for pin partial heating). 16 µPD6376 [MEMO] 17 µPD6376 [MEMO] 18 µPD6376 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 19 µPD6376 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 2