DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703003A, 703004A, 703025A
V853TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD703003A, 703004A, and 703025A are members of the V850 Family TM of 32-bit single-chip microcontrollers designed for real-time control operations. These microcontrollers provide on-chip features including a 32-bit CPU core, ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an A/D converter, a D/A converter, and PWM. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. V853 User’s Manual Hardware: U10913E
V850 Family User’s Manual Architecture: U10243E
FEATURES
• Number of instructions: 74 • Minimum instruction execution time: 30 ns (@ 33 MHz operation) • General-purpose registers: 32 bits × 32 registers • Instruction set optimized for control applications • On-chip memory ROM: 256 KB ( µPD703025A) 128 KB ( µPD703003A) 96 KB (µPD703004A) RAM: 8 KB ( µPD703025A) 4 KB (µPD703003A, 703004A) • Advanced on-chip interrupt controller • Real-time pulse unit suitable for control operations • Powerful serial interface (on-chip dedicated baud rate generator) • On-chip clock generator • 10-bit resolution A/D converter: 8 channels • 8-bit resolution D/A converter: 2 channels • 8-/9-/10-/12-bit resolution PWM: 2 channels • Power saving functions
APPLICATIONS
• AV: Camcorders, VCRs, etc. • Office equipment: PPCs, LBPs, printers, etc. • Industrial equipment: Motor controllers, NC machine tools, etc. • Communications equipment: Mobile telephones, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13188EJ4V0DS00 (4th edition) Date Published July 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
©
1998
µPD703003A, 703004A, 703025A
ORDERING INFORMATION
Part Number Package Maximum Internal Internal Operating ROM RAM Frequency (MHz) (Bytes) (Bytes) 25 33 25 33 25 33 128 K 128 K 96 K 96 K 256 K 256 K 4K 4K 4K 4K 8K 8K
µPD703003AGC-25-xxx-8EU µPD703003AGC-33-xxx-8EU µPD703004AGC-25-xxx-8EU µPD703004AGC-33-xxx-8EU µPD703025AGC-25-xxx-8EU µPD703025AGC-33-xxx-8EU
100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION
• 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703003AGC-25-xxx-8EU µPD703003AGC-33-xxx-8EU µPD703004AGC-25-xxx-8EU
µPD703004AGC-33-xxx-8EU µPD703025AGC-25-xxx-8EU µPD703025AGC-33-xxx-8EU
Caution Connect the IC (Internally Connected) pin directly to VSS.
2
P43/AD3 P42/AD2 VSS VDD P41/AD1 P40/AD0 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ WAIT IC MODE RESET CVDD/CKSEL X2 X1 CVSS CLKOUT VSS VDD P110/TO140
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P31/TO131 P32/TCLR13 P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P63/A19 P62/A18 P61/A17 P60/A16 VSS VDD P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 P47/AD7 P46/AD6 P45/AD5 P44/AD4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P30/TO130 P27/SCK1 P26/RXD1/SI1 P25/TXD1/SO1 P24/SCK0 P23/RXD0/SI0 P22/TXD0/SO0 P21/PWM1 P20/PWM0 NMI VDD VSS P17/INTP123/SCK2 P16/INTP122/SI2 P15/INTP121/SO2 P14/INTP120 P13/TI12 P12/TCLR12 P11/TO121 P10/TO120 AVDD AVSS AVREF1 P77/ANI7 P76/ANI6
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 ANO0 ANO1 AVREF2 AVREF3 P07/INTP113/ADTRG P06/INTP112 P05/INTP111 P04/INTP110 P03/TI11 P02/TCLR11 P01/TO111 P00/TO110 P117/INTP143 P116/INTP142 P115/INTP141 P114/INTP140 P113/TI14 P112/TCLR14 P111/TO141
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
PIN NAMES
A16 to A19: AD0 to AD15: ADTRG: ANI0 to ANI7: ANO0, ANO1: ASTB: AVDD: AVREF1 to AVREF3: AVSS: CVDD: CVSS: CKSEL: CLKOUT: DSTB: HLDAK: HLDRQ: IC: INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143 LBEN: MODE: NMI: P00 to P07: P10 to P17: P20 to P27: Lower Byte Enable Mode Non-maskable Interrupt Request Port 0 Port 1 Port 2 Address Bus Address/Data Bus AD Trigger Input Analog Input Analog Output Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Power Supply for Clock Generator Ground for Clock Generator Clock Select Clock Output Data Strobe Hold Acknowledge Hold Request Internally Connected P30 to P37: P40 to P47: P50 to P57: P60 to P63: P70 to P77: P90 to P96: P110 to P117: PWM0, PWM1: RESET: R/W: RXD0, RXD1: SCK0 to SCK3: SI0 to SI3: SO0 to SO3: TO110, TO111,: TO120, TO121, TO130, TO131, TO140, TO141 TCLR11 to TCLR14: Timer Clear TI11 to TI14: TXD0, TXD1: UBEN: WAIT: X1, X2: VDD: VSS: Timer Input Transmit Data Upper Byte Enable Wait Crystal Power Supply Ground Port 3 Port 4 Port 5 Port 6 Port 7 Port 9 Port 11 Pulse Width Modulation Reset Read/Write Status Receive Data Serial Clock Serial Input Serial Output Timer Output
INTP110 to INTP113,: Interrupt Request from Peripherals
Data Sheet U13188EJ4V0DS00
3
µPD703003A, 703004A, 703025A
INTERNAL BLOCK DIAGRAM
Mask ROM NMI INTP110 to INTP113 INTP120 to INTP123 INTP130 to INTP133 INTP140 to INTP143 TO110, TO111 TO120, TO121 TO130, TO131 TO140, TO141 TCLR11 to TCLR14 TI11 to TI14 SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 Note 2 INTC Note 1 PC
32-bit barrel shifter
CPU
Instruction queue
Multiplier 16 × 16 → 32
System registers
BCU
ASTB DSTB R/W UBEN LBEN WAIT A16 to A19 AD0 to AD15 HLDRQ HLDAK
RPU
RAM
General-purpose registers 32 bits × 32 ALU
BRG0 SO1/TXD1 SI1/RXD1 SCK1
UART1/CSI1 BRG1
A/D converter
D/A converter
Port P110 to P117 P90 to P96 P70 to P77 P60 to P63 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P17 P00 to P07
CG
ANI0 to ANI7 AVREF1 AVSS AVDD ADTRG
SO2 SI2 SCK2
CSI2 BRG2
ANO0, ANO1 AVREF2, AVREF3
CKSEL CLKOUT X1 X2 MODE RESET VDD VSS CVDD CVSS
SO3 SI3 SCK3 PWM0, PWM1
CSI3
PWM
Notes 1. µPD703003A:
128 KB 96 KB 256 KB 8 KB
µPD703004A: µPD703025A: µPD703025A:
2. µPD703003A, 703004A: 4 KB
4
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
CONTENTS
1. DIFFERENCES AMONG PRODUCTS ............................................................................................
6
2. PIN FUNCTIONS .............................................................................................................................. 7 2.1 Port Pins ................................................................................................................................ 7 2.2 Non-Port Pins ........................................................................................................................ 9 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 11 3. ELECTRICAL SPECIFICATIONS .................................................................................................... 14 4. PACKAGE DRAWING ..................................................................................................................... 36 5. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 37
Data Sheet U13188EJ4V0DS00
5
µPD703003A, 703004A, 703025A
1. DIFFERENCES AMONG PRODUCTS
Item Internal ROM
µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A
Mask ROM 128 KB 96 KB 256 KB 8 KB Flash memory 128 KB 4 KB 256 KB 8 KB
Internal RAM Operation Normal mode operation mode
4 KB Single-chip Implemented mode ROM-less mode Implemented Not implemented
Implemented Not implemented
Flash memory programming mode VPP pin Value of CKC register after reset
Not implemented
Implemented
Not implemented 00H MODE = 0: 03H MODE = 1: 00H
Implemented 00H MODE = 0: 03H MODE = 1: 00H
Electrical specifications Other
Power consumption levels vary (see specific product’s data sheet). Depending on the products, noise tolerance and noise emission will vary due to the differences in circuit scale and mask layout.
6
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
2. PIN FUNCTIONS
2.1 Port Pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. P50 to P57 I/O Port 5 8-bit I/O port Input/output can be specified in 1-bit units. AD8 to AD15 I/O Port 3 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port 2 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port 1 8-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function TO110 TO111 TCLR11 TI11 INTP110 INTP111 INTP112 INTP113/ADTRG TO120 TO121 TCLR12 TI12 INTP120 INTP121/SO2 INTP122/SI2 INTP123/SCK2 PWM0 PWM1 TXD0/SO0 RXD0/SI0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 TO130 TO131 TCLR13 TI13 INTP130 INTP131/SO3 INTP132/SI3 INTP133/SCK3 AD0 to AD7
Data Sheet U13188EJ4V0DS00
7
µPD703003A, 703004A, 703025A
(2/2)
Pin Name P60 to P63 I/O I/O Port 6 4-bit I/O port Input/output can be specified in 1-bit units. P70 to P77 Input Port 7 8-bit input port P90 P91 P92 P93 P94 P95 P96 P110 P111 P112 P113 P114 P115 P116 P117 I/O Port 11 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port 9 7-bit I/O port Input/output can be specified in 1-bit units. LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ TO140 TO141 TCLR14 TI14 INTP140 INTP141 INTP142 INTP143 ANI0 to ANI7 Function Alternate Function A16 to A19
8
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
2.2 Non-Port Pins (1/2)
Pin Name TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TCLR11 TCLR12 TCLR13 TCLR14 TI11 TI12 TI13 TI14 INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 INTP130 INTP131 INTP132 INTP133 INTP140 INTP141 INTP142 INTP143 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 Input Serial receive data input (3-wire) for CSI0 to CSI3 Output Serial transmit data output (3-wire) for CSI0 to CSI3 Input External maskable interrupt request input, also used as external capture trigger input for timer 14 Input External maskable interrupt request input, also used as external capture trigger input for timer 13 Input External maskable interrupt request input, also used as external capture trigger input for timer 12 Input External maskable interrupt request input, also used as external capture trigger input for timer 11 Input External count clock input for timers 11 to 14 Input External clear signal input for timers 11 to 14 I/O Output Function Pulse signal output from timers 11 to 14 Alternate Function P00 P01 P10 P11 P30 P31 P110 P111 P02 P12 P32 P112 P03 P13 P33 P113 P04 P05 P06 P07/ADTRG P14 P15/SO2 P16/SI2 P17/SCK2 P34 P35/SO3 P36/SI3 P37/SCK3 P114 P115 P116 P117 P22/TXD0 P25/TXD1 P15/INTP121 P35/INTP131 P23/RXD0 P26/RXD1 P16/INTP122 P36/INTP132
Data Sheet U13188EJ4V0DS00
9
µPD703003A, 703004A, 703025A
(2/2)
Pin Name SCK0 SCK1 SCK2 SCK3 TXD0 TXD1 RXD0 RXD1 PWM0 PWM1 AD0 to AD7 AD8 to AD15 A16 to A19 LBEN UBEN R/W DSTB ASTB HLDAK HLDRQ ANI0 to ANI7 ANO0, ANO1 NMI CLKOUT CKSEL WAIT MODE RESET X1 X2 ADTRG AVREF1 AVREF2 AVREF3 AVDD AVSS CVDD CVSS VDD VSS IC — — — — — — — Positive power supply for A/D converter Ground potential for A/D converter Positive power supply for on-chip clock generator Ground potential for on-chip clock generator Positive power supply Ground potential Internally connected pin (Connect directly to VSS) CKSEL — — — — Output Input Input Output Input Output Input Input Input Input Input — Input Input Input Output Output Output Higher address bus used for external memory expansion External data bus’s lower byte enable signal output External data bus’s higher byte enable signal output External read/write status output External data strobe signal output External address strobe signal output Bus hold acknowledge output Bus hold request input Analog input to A/D converter Analog output from D/A converter Non-maskable interrupt request input System clock output Input for specifying clock generator’s operation mode Control signal input for inserting wait in bus cycle Operation mode specification System reset input Resonator connection for system clock. Input is via X1 when using an external clock. A/D converter external trigger input Reference voltage input for A/D converter Reference voltage input for D/A converter CVDD — — — — — P07/INTP113 — — — — — I/O 16-bit multiplexed address/data bus for external memory expansion Output PWM pulse signal output Input Serial receive data input for UART0 and UART1 Output Serial transmit data output for UART0 and UART1 I/O I/O Function Serial clock I/O (3-wire) for CSI0 to CSI3 Alternate Function P24 P27 P17/INTP123 P37/INTP133 P22/SO0 P25/SO1 P23/SI0 P26/SI1 P20 P21 P40 to P47 P50 to P57 P60 to P63 P90 P91 P92 P93 P94 P95 P96 P70 to P77 — — —
10
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. Figure 2-1 illustrates the various circuit types using partially abridged diagrams. When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended. Table 2-1. Types of Pin Input/Output Circuits (1/2)
Pin Name P00/TO110, P01/TO111 P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113/ADTRG P10/TO120, P11/TO121 P12/TCLR12, P13/TI12 P14/INTP120 P15/INTP121/SO2 P16/INTP122/SI2 P17/INTP123/SCK2 P20/PWM0, P21/PWM1 P22/TXD0/SO0 P23/RXD0/SI0, P24/SCK0 P25/TXD1/SO1 P26/RXD1/SI1, P27/SCK1 P30/TO130, P31/TO131 P32/TCLR13, P33/TI13 P34/INTP130 P35/INTP131/SO3 P36/INTP132/SI3 P37/INTP133/SCK3 P40/AD0 to P47/AD7 P50/AD8 to P57/AD15 P60/A16 to P63/A19 P70/ANI0 to P77/ANI7 P90/LBEN P91/UBEN P92/R/W P93/DSTB P94/ASTB P95/HLDAK P96/HLDRQ P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 P114/INTP140 to P117/INTP143 ANO0, ANO1 NMI 8 9 5 Connect directly to VSS. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. 5 10-A 8 5 8 5 8 Input/Output Circuit Type 5 8 Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
5 8
5
12 2
Leave open. Connect directly to VSS.
Data Sheet U13188EJ4V0DS00
11
µPD703003A, 703004A, 703025A
Table 2-1. Types of Pin Input/Output Circuits (2/2)
Pin Name CLKOUT WAIT MODE RESET CVDD/CKSEL AVREF1 to AVREF3, AVSS AVDD IC — — — Connect directly to VSS. Connect directly to VDD. Connect directly to VSS. Input/Output Circuit Type 3 1 2 Recommended Connection of Unused Pins Leave open. Connect directly to VDD. —
12
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
Figure 2-1. Pin Input/Output Circuits
Type 1
Type 8
VDD P-ch IN/OUT
VDD P-ch IN N-ch
Data
Output disable
N-ch
Type 2
Type 9
P-ch IN IN N-ch
+ –
Comparator
VREF (threshold voltage)
Input enable Schmitt-triggered input with hysteresis characteristics Type 3 Type 10-A VDD
VDD P-ch OUT N-ch
Pull-up enable Data
P-ch VDD P-ch IN/OUT
Open drain Output disable
N-ch
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Type 12
Analog output voltage
P-ch N-ch
OUT
Input enable
Data Sheet U13188EJ4V0DS00
13
µPD703003A, 703004A, 703025A
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter Power supply voltage Symbol VDD CVDD CVSS AVDD AVSS Input voltage Clock input voltage Output current, low VI1 VK IOL VDD pin CVDD pin CVSS pin AVDD pin AVSS pin Note, VDD = 5.0 V ±10% X1 pin, VDD = 5.0 V ±10% Per pin Total for all pins Output current, high IOH Per pin Total for all pins Output voltage Analog input voltage VO VIAN VDD = 5.0 V ±10% P70/ANI0 to P77/ANI7 AVDD > VDD VDD ≥ AVDD Analog reference input voltage AVREF AVREF1 to AVREF3 AVDD > VDD VDD ≥ AVDD Operating ambient temperature Storage temperature TA Tstg Conditions Ratings –0.5 to +7.0 –0.5 to VDD + 0.3 –0.5 to +0.5 –0.5 to VDD + 0.3 –0.5 to +0.5 –0.5 to VDD + 0.3 –0.5 to VDD + 1.0 4.0 100 –4.0 –100 –0.5 to VDD + 0.3 –0.5 to VDD + 0.3 –0.5 to AVDD + 0.3 –0.5 to VDD + 0.3 –0.5 to AVDD + 0.3 –40 to +85 –65 to +150 Unit V V V V V V V mA mA mA mA V V V V V °C °C
Note X1, P70/ANI0 to P77/ANI7, and AVREF1 to AVREF3 are excluded. Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. However, open-drain pins and open collector pins can be directly connected. A direct connection to an external circuit can be made to avoid conflicting output from high-impedance pins if the external circuit is designed for the correct timing. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance. Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Condition fC = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF
14
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
Operating Conditions
Operation Mode Direct mode, PLL mode Internal Operating Clock Frequency (φ) 2 to 33 MHzNote 1 5 to 33 MHzNote 2 Operating Ambient Temperature (TA) –40 to +85°C –40 to +85°C Power Supply Voltage (VDD) 5.0 V ±10% 5.0 V ±10%
Notes 1. When not using A/D converter 2. When using A/D converter Recommended Oscillator (1) Ceramic resonator connection (TA = –40 to +85°C) (a) µPD703003A, 703004A
X1 X2 Rd C1 C2
Manufacturer
Part Number
Oscillation Frequency fXX (MHz) 5.0 5.0 5.0 5.0 5.0 5.0 6.6 6.6 6.6 6.6 6.6 6.6 5.0 5.0 6.6 5.0 5.0 6.6 6.6
Recommended Circuit Constant C1 (pF) 33 On-chip On-chip On-chip 33 On-chip 33 On-chip On-chip On-chip 33 On-chip On-chip On-chip On-chip 100 On-chip 100 On-chip C2 (pF) 33 On-chip On-chip On-chip 33 On-chip 33 On-chip On-chip On-chip 33 On-chip On-chip On-chip On-chip 100 On-chip 100 On-chip Rd (Ω) 680 680 680 680 680 680 — — — — — — — — — — — — —
Oscillation Stabilization Time MIN. (V) MAX. (V) (MAX.) TOST (ms) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 0.14 0.14 0.14 0.14 0.14 0.14 0.10 0.10 0.10 0.10 0.10 0.10 0.18 0.16 0.17 0.31 0.31 0.30 0.30
Oscillation Voltage Range
Kyocera Corporation
KBR-5.0MSA/MSB KBR-5.0MKC KBR-5.0MKD KBR-5.0MKS PBRC5.00A PBRC5.00B KBR-6.6MSA/MSB KBR-6.6MKC KBR-6.6MKD KBR-6.6MKS PBRC6.60A PBRC6.60B
TDK
CCR5.0MC3 FCR5.0MC5 CCR6.6MC3
Murata Mfg. Co., Ltd.
CSA5.00MG040 CST5.00MGW040 CSA6.60MTZ040 CST6.60MTW040
Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible. 2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines. 3. Sufficiently evaluate the matching between the µPD703003A or 703004A and the resonator.
Data Sheet U13188EJ4V0DS00
15
µPD703003A, 703004A, 703025A
(b) µPD703025A
X1
X2 Rd C1 C2
Manufacturer
Part Number
Oscillation Frequency fXX (MHz) 4.0 5.0 4.0 4.0 4.0 6.6 6.6 6.6
Recommended Circuit Constant C1 (pF) On-chip On-chip 100 On-chip On-chip 100 On-chip On-chip C2 (pF) On-chip On-chip 100 On-chip On-chip 100 On-chip On-chip Rd (Ω) — — — — — — — —
Oscillation Stabilization Time MIN. (V) MAX. (V) (MAX.) TOST (ms) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 0.28 0.20 0.20 0.20 0.16 0.20 0.20 0.09
Oscillation Voltage Range
TDK
CCR4.0MC3 CCR5.0MC3
Murata Mfg. Co., Ltd.
CSA4.00MG040 CST4.00MGW040 CSTS0400MG06 CSA6.60MTZ040 CST6.60MTW040 CSTS0660MG06
Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible. 2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines. 3. Sufficiently evaluate the matching between µPD703025A and the resonator.
(2) External clock input
X1 X2 Open
High-speed CMOS inverter External clock
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pin as possible. 2. Sufficiently evaluate the matching between the µPD703003A, 703004A, or 703025A and the high-speed CMOS inverter.
16
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
Parameter Input voltage, high Symbol VIH Conditions Except for X1 and pins listed in Note Note Input voltage, low VIL Except for X1 and pins listed in Note Note Clock input voltage, high Clock input voltage, low Schmitt-triggered input Threshold voltage Schmitt-triggered input hysteresis width Output voltage, high VXH VXL VT + VT – VT+ VOH – V T– X1 X1 Note, rising edge Note, falling edge Note IOH = –2.5 mA IOH = –100 µA Output voltage, low Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Software pull-up resistor VOL ILIH ILIL ILOH ILOL R IOL = 2.5 mA VI = VDD VI = 0 V VO = VDD VO = 0 V P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3 15 40 0.5 0.7VDD VDD – 0.4 0.45 10 –10 10 –10 90 MIN. 2.2 0.8VDD –0.5 –0.5 0.8VDD –0.5 3.0 2.0 TYP. MAX. VDD + 0.3 VDD + 0.3 +0.8 0.2VDD VDD + 0.5 +0.6
(1/2)
Unit V V V V V V V V V V V V
µA µA µA µA
kΩ
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. 2. φ = Internal system clock frequency
Data Sheet U13188EJ4V0DS00
17
µPD703003A, 703004A, 703025A
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
Parameter Power µPD703003A, When operating supply 703004A current In HALT mode In IDLE mode In STOP mode Symbol IDD1 Direct PLL IDD2 Conditions modeNote MIN. TYP. MAX. 1.9 × φ + 5 2.1 × φ + 17 2.0 × φ + 7 2.2 × φ + 20 1.2 × φ + 5 1.3 × φ + 13 1.3 × φ + 7 1.4 × φ + 15 8 × φ + 300 10 × φ + 500 0.1 × φ + 2 0.2 × φ + 3 2 50
(2/2)
Unit mA mA mA mA
modeNote
Direct modeNote PLL modeNote modeNote
IDD3
Direct
µA
mA
PLL modeNote IDD4
µA
µPD703025A When operating
In HALT mode In IDLE mode In STOP mode
IDD1
Direct modeNote PLL modeNote
2.5 × φ + 2 2.8 × φ + 16.5 2.6 × φ + 4 2.9 × φ +19.5 1.3 × φ + 5 1.4 × φ + 13 1.3 × φ + 10 1.4 × φ + 18 8 × φ + 300 10 × φ + 500 0.1 × φ + 2 0.2 × φ + 3 2 50
mA mA mA mA
IDD2
Direct PLL
modeNote
modeNote
IDD3
Direct modeNote PLL modeNote
µA
mA
IDD4
µA
Note When using A/D converter: φ = 5 to 33 MHz When not using A/D converter: φ = 2 to 33 MHz Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. The power supply current does not include AVREF1 to AVREF3 or the current that flows across a software pull-up resistor. 2. φ = Internal system clock frequency
18
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
Data Retention Characteristics (TA = –40 to +85°C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDD = VDDDR –40°C ≤ TA ≤ +50°C 50°C < TA ≤ 85°C Power supply voltage rise time Power supply voltage fall time Power supply voltage hold time (vs. STOP mode setting) tRVD tFVD tHVD Note Note 200 200 0 0 0.9VDDDR 0 VDDDR 0.1VDDDR Conditions MIN. 1.5 0.2VDDDR 0.2VDDDR TYP. MAX. 5.5 50 200 Unit V
µA µA µs µs
ms ns V V
STOP mode release signal input time tDREL Data retention high-level input voltage Data retention low-level input voltage VIHDR VILDR
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1 Remark TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
STOP mode setting (fifth clock after PSC register is set) VDD VDD tHVD tFVD VDDDR tRVD tDREL VDD
RESET (input)
VIHDR
NMI (input) (Released at falling edge)
VIHDR
NMI (input) (Released at rising edge) VILDR
Data Sheet U13188EJ4V0DS00
19
µPD703003A, 703004A, 703025A
AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) AC test input waveform (a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/ SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/ TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
VDD 0.8VDD 0.2VDD 0.8VDD 0.2VDD
Point of mesurement
0V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V 0.8 V
Point of mesurement
2.2 V 0.8 V
0.4 V
AC test output measurement points
2.2 V 0.8 V 2.2 V 0.8 V
Point of mesurement
Load condition
DUT (Device under testing) CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device’s load capacitance to below 50 pF.
20
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(1) Clock timing
Parameter Symbol Conditions 25 MHz Version MIN. X1 input cycle tCYX Direct mode PLL mode (PLL locked) X1 input high-level width X1 input low-level width tWXH t WXL Direct mode PLL mode Direct mode PLL mode X1 input rise time tXR Direct mode PLL mode X1 input fall time t XF Direct mode PLL mode CPU operating frequency CLKOUT output cycle CLKOUT input high-level width CLKOUT input low-level width CLKOUT input rise time CLKOUT input fall time – 20 200 7 80 7 80 7 15 7 15 Note 2 40 0.5T – 5 0.5T – 5 5 5 Direct mode 3 17 3 25 Note 3 Note 2 30 0.5T – 5 0.5T – 5 5 5 17 MAX. Note 1 Note 1 33 MHz Version MIN. 15 151 6 60 6 60 7 10 7 10 33 Note 3 MAX. Note 1 Note 1 ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns Unit
φ
tCYK tWKH tWKL tKR
tKF
Delay time from X1↓ to CLKOUT tDXK
Notes 1. When using A/D converter: 100 ns When not using A/D converter: 250 ns 2. When using A/D converter: 5 MHz When not using A/D converter: 2 MHz 3. When using A/D converter: 200 ns When not using A/D converter: 500 ns Remark T = tCYK
X1 (input)
CLKOUT (output)
Data Sheet U13188EJ4V0DS00
21
µPD703003A, 703004A, 703025A
(2) Input waveform (a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/ INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/ SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/ SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Parameter Symbol Conditions 25 MHz Version MIN. Input rise time Input fall time tIR2 tIF2 MAX. 20 20 33 MHz Version MIN. MAX. 20 20 ns ns Unit
VDD Input signal 0V
0.8VDD 0.2VDD 0.2VDD
0.8VDD
(b) Pins other than those listed in (a) above
Parameter Symbol Conditions 25 MHz Version MIN. Input rise time Input fall time tIR1 tIF1 MAX. 10 10 33 MHz Version MIN. MAX. 10 10 ns ns Unit
2.4 V Input signal 0.4 V
2.2 V 0.8 V 0.8 V
2.2 V
(3) Output waveform (other than CLKOUT)
Parameter Symbol Conditions 25 MHz Version MIN. Output rise time Output fall time tOR tOF MAX. 10 10 33 MHz Version MIN. MAX. 10 10 ns ns Unit
2.2 V Output signal 0.8 V
2.2 V 0.8 V
22
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(4) Reset timing
Parameter Symbol Conditions 25 MHz Version MIN. RESET high-level width RESET low-level width tWRSH tWRSL When power supply is ON and STOP mode has been released Other than when power supply is ON and STOP mode has been released 500 500 + TOST MAX. 33 MHz Version MIN. 500 500 + TOST MAX. ns ns Unit
500
500
ns
Remark TOST: Oscillation stabilization time
RESET (input)
Data Sheet U13188EJ4V0DS00
23
µPD703003A, 703004A, 703025A
(5) Read timing (1/2)
Parameter Symbol Conditions 25 MHz Version MIN. Delay time from CLKOUT↑ to address tDKA Delay time from CLKOUT↑ to R/W, UBEN, LBEN tDKA2 Delay time from CLKOUT↑ to address float tFKA Delay time from CLKOUT↓ to ASTB tDKST Delay time from CLKOUT↑ to DSTB tDKD Data input setup time (to CLKOUT↑) tSIDK Data input hold time (from CLKOUT↑) tHKID WAIT setup time (to CLKOUT↓) tSWTK WAIT hold time (from CLKOUT↓) tHKWT Address hold time (from CLKOUT↑) tHKA Address setup time (to ASTB↓) tSAST –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C Address hold time (from ASTB↓) tHSTA Delay time from DSTB↓ to address float tFDA Data input setup time (to address) tSAID –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C Data input setup time (to DSTB↓) tSDID Delay time from ASTB↓ to DSTB↓ tDSTD Data input hold time (from DSTB↑) tHDID Delay time from DSTB↑ to address output tDDA Delay time from DSTB ↑ to ASTB↑ tDDSTH Delay time from DSTB ↑ to ASTB↓ tDDSTL DSTB low-level width tWDL –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C ASTB high-level width WAIT setup time (to address) tWSTH tSAWT1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C tSAWT2 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB↓) tSSTWT1 n≥1 n≥1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C tSSTWT2 WAIT hold time (from ASTB↓) tHSTWT1 tHSTWT2 n≥1 n≥1 n≥1 nT (1 + n)T (0.5 + n)T (1.5 + n)T T – 18 T – 20 (1 + n)T – 15 nT (1 + n)T –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C 0.5T – 10 0 (1 + i)T 0.5T – 10 (1.5 + i)T – 10 (1 + n)T – 10 (1 + n)T – 13 T – 10 1.5T – 20 1.5T – 24 (1.5 + n)T – 20 (1.5 + n)T – 24 (0.5 + n)T (1.5 + n)T T – 18 T – 20 (1 + n)T – 15 3 –2 3 3 3 5 5 5 5 0 0.5T – 10 0.5T – 12 0.5T – 10 0 (2 + n)T – 22 (2 + n)T – 25 (1 + n)T – 20 (1 + n)T – 24 0.5T – 10 0 (1 + i)T 0.5T – 10 (1.5 + i)T – 10 (1 + n)T – 10 (1 + n)T – 13 T – 10 1.5T – 20 1.5T – 24 (1.5 + n)T – 20 (1.5 + n)T – 24 MAX. 20 +13 15 15 15 33 MHz Version MIN. 3 –2 3 3 3 5 5 5 5 0 0.5T – 10 0.5T – 12 0.5T – 10 0 (2 + n)T – 22 (2 + n)T – 25 (1 + n)T – 20 (1 + n)T – 24 MAX. 20 +13 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. 3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle. 4. Maintain at least one of the two data input hold times, either tHKID () or tHDID ().
24
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(5) Read timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
A16 to A19 (output)
R/W (output) UBEN (output) LBEN (output)
AD0 to AD15 (I/O)
A0 to A15 (output)
D0 to D15 (input)
ASTB (output)
DSTB (output)
WAIT (input)
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ4V0DS00
25
µPD703003A, 703004A, 703025A
(6) Write timing (1/2)
Parameter Symbol Conditions 25 MHz Version MIN. Delay time from CLKOUT↑ to address tDKA Delay time from CLKOUT↑ to R/W, UBEN, LBEN tDKA2 Delay time from CLKOUT↓ to ASTB tDKST Delay time from CLKOUT↑ to DSTB tDKD WAIT setup time (to CLKOUT↓) tSWTK WAIT hold time (from CLKOUT↓) tHKWT Address hold time (from CLKOUT↑) tHKA Address setup time (to ASTB↓) tSAST –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C Address hold time (from ASTB↓) tHSTA Delay time from ASTB↓ to DSTB↓ tDSTD Delay time from DSTB ↓ to ASTB↓ tDDSTH DSTB low-level width tWDL –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C ASTB high-level width WAIT setup time (to address) tWSTH tSAWT1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C tSAWT2 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB↓) tSSTWT1 n≥1 n≥1 n ≥ 1, –40°C ≤ TA ≤ +70°C n ≥ 1, 70°C < TA ≤ 85°C tSSTWT2 WAIT hold time (from ASTB↓) tHSTWT1 tHSTWT2 Delay time from CLKOUT↑ to data output tDKOD n≥1 n≥1 n≥1 –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C nT (1 + n)T 20 23 10 0 (1 + n)T – 15 T – 10 0 (1 + n)T – 15 T – 10 (0.5 + n)T (1.5 + n)T T – 18 T – 20 (1 + n)T – 15 nT (1 + n)T 20 23 10 3 –2 3 3 5 5 0 0.5T – 10 0.5T – 12 0.5T – 10 0.5T – 10 0.5T – 10 (1 + n)T – 10 (1 + n)T – 13 T – 10 1.5T – 20 1.5T – 24 (1.5 + n)T – 20 (1.5 + n)T – 24 (0.5 + n)T (1.5 + n)T T – 18 T – 20 (1 + n)T – 15 MAX. 20 +13 15 15 33 MHz Version MIN. 3 –2 3 3 5 5 0 0.5T – 10 0.5T – 12 0.5T – 10 0.5T – 10 0.5T – 10 (1 + n)T – 10 (1 + n)T – 13 T – 10 1.5T – 20 1.5T – 24 (1.5 + n)T – 20 (1.5 + n)T – 24 MAX. 20 +13 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Delay time from DSTB ↓ to data output tDDOD Data output hold time (from CLKOUT↑) tHKOD Data output setup time (to DSTB↑) tSODD Data output hold time (from DSTB↑) tHDOD
Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function.
26
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(6) Write timing (2/2): 1 wait
T1 T2 TW T3
CLKOUT (output)
A16 to A19 (output)
R/W (output) UBEN (output) LBEN (output)
AD0 to AD15 (I/O)
A0 to A15 (output)
D0 to D15 (output)
ASTB (output)
DSTB (output)
WAIT (input)
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ4V0DS00
27
µPD703003A, 703004A, 703025A
(7) Bus hold timing (1/2)
Parameter Symbol Conditions 25 MHz Version MIN. HLDRQ setup time (to CLKOUT↓) tSHQK HLDRQ hold time (from CLKOUT↓) tHKHQ HLDAK delay time from CLKOUT↑ tDKHA HLDRQ high-level width HLDAK low-level width tWHQH tWHAL –40°C ≤ TA ≤ +70°C 70°C < TA ≤ 85°C Delay time from CLKOUT↑ to bus float tDKF Delay time from HLDAK↑ to bus output tDHAC Delay time from HLDRQ↓ to HLDAK↓ tDHQHA1 Delay time from HLDRQ↑ to HLDAK↑ tDHQHA2 0.5T –3 (2n + 7.5)T + 20 1.5T + 20 0.5T T + 10 T – 10 T – 12 20 –3 (2n + 7.5)T + 20 1.5T + 20 5 5 20 T + 10 T – 10 T – 12 20 MAX. 33 MHz Version MIN. 5 5 20 MAX. ns ns ns ns ns ns ns ns ns ns Units
Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function.
28
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A16 to A19 (output), Note
AD0 to AD15 (I/O)
D0 to D15 (input or output)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output) Remark Broken lines indicate high impedance.
Data Sheet U13188EJ4V0DS00
29
µPD703003A, 703004A, 703025A
(8) Interrupt timing
Parameter Symbol Conditions 25 MHz Version MIN. NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width tWNIH tWNIL tWITH tWITL n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 n = 110 to 113, 120 to 123, 130 to 133, 140 to 143 500 500 3T + 10 3T + 10 MAX. 33 MHz Version MIN. 500 500 3T + 10 3T + 10 MAX. ns ns ns ns Unit
Remark T = tCYK
NMI (input)
INTPn (input)
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
30
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(9) CSI timing (1/2) (a) Master mode (i) Timing of CSI0 to CSI2
Symbol Conditions 25 MHz Version MIN. SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn↑) SIn hold time (from SCKn↑) tCYSK1 tWSKH1 tWSKL1 tSSISK1 tHSKSI1 Output Output Output 160 0.5tCYSK1 – 20 0.5tCYSK1 – 20 30 0 18 0.5tCYSK1 – 5 0.5tCYSK1 – 5 MAX. 33 MHz Version MIN. 120 0.5tCYSK1 – 20 0.5tCYSK1 – 20 30 0 18 MAX. ns ns ns ns ns ns ns Unit
Parameter
SOn output delay time (from SCKn↓) tDSKSO1 SOn output hold time (from SCKn↑) tHSKSO1
Remark n = 0 to 2 (ii) Timing of CSI3
Parameter Symbol Conditions RL = 1.5 kΩ CL = 50 pF 25 MHz Version MIN. SCK3 cycle SCK3 high-level width SCK3 low-level width SI3 setup time (to SCK3↑) SI3 hold time (from SCK3↑) tCYSK3 tWSKH3 tWSKL3 tSSISK3 tHSKSI3 RL = 1.5 kΩ CL = 50 pF Output Output Output 500 0.5tCYSK3 – 70 0.5tCYSK3 – 70 100 50 150 0.5tCYSK3 – 5 0.5tCYSK3 – 5 MAX. 33 MHz Version MIN. 500 0.5tCYSK3 – 70 0.5tCYSK3 – 70 100 50 150 MAX. ns ns ns ns ns ns ns Unit
SO3 output delay time (from SCK3↓) tDSKSO3 SO3 output hold time (from SCK3↑) tHSKSO3
Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines. (b) Slave mode (i) Timing of CSI0 to CSI2
Symbol Conditions 25 MHz Version MIN. SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn↑) SIn hold time (from SCKn↑) tCYSK2 tWSKH2 tWSKL2 tSSISK2 tHSKSI2 Input Input Input 160 50 50 10 10 30 tWSKH2 tWSKH2 MAX. 33 MHz Version MIN. 120 30 30 10 10 30 MAX. ns ns ns ns ns ns ns Unit
Parameter
SOn output delay time (from SCKn↓) tDSKSO2 SOn output hold time (from SCKn↑) tHSKSO2
Remark n = 0 to 2
Data Sheet U13188EJ4V0DS00
31
µPD703003A, 703004A, 703025A
(9) CSI timing (2/2) (ii) Timing of CSI3
Parameter Symbol Conditions 25 MHz Version MIN. SCK3 cycle SCK3 high-level width SCK3 low-level width SI3 setup time (to SCK3↑) SI3 hold time (from SCK3↑) tCYSK4 tWSKH4 tWSKL4 tSSISK4 tHSKSI4 RL = 1.5 kΩ CL = 50 pF Input Input Input 500 180 180 100 50 150 tWSKH4 tWSKH4 MAX. 33 MHz Version MIN. 500 180 180 100 50 150 MAX. ns ns ns ns ns ns ns Unit
SO3 output delay time (from SCK3↓) tDSKSO4 SO3 output hold time (from SCK3↑) tHSKSO4
Remark RL and CL are the load resistance and load capacitance of the SCK3 and SO3 output lines.
SCKn (I/O)
SIn (Input)
Input data
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 3
32
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
(10) RPU timing
Parameter Symbol Conditions 25 MHz Version MIN. TI1n high-level width TI1n low-level width TCLR1n high-level width TCLR1n low-level width tWTIH tWTIL tWTCH tWTCL 3T + 10 3T + 10 3T + 10 3T + 10 MAX. 33 MHz Version MIN. 3T + 10 3T + 10 3T + 10 3T + 10 MAX. ns ns ns ns Unit
Remark T = tCYK
TI1n (input)
TCLR1n (input)
Remark n = 1 to 4
Data Sheet U13188EJ4V0DS00
33
µPD703003A, 703004A, 703025A
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter Symbol Conditions 25 MHz Version MIN. Resolution Overall errorNote 1 — — — Quantization error Conversion time — tCONV 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD Sampling time tSAMP 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD Zero-scale errorNote 1 — — Full-scale errorNote 1 — — Non-linearity errorNote 1 — — Analog input voltageNote 2 Reference voltage AVREF1 current AVDD power supply current VIAN AVREF1 AIREF1 AIDD 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD –0.3 3.5 1.2 2.3 48 48 8 8 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±3.5 ±4.5 ±2.5 ±4.5 ±2.5 ±4.5 AVDD + 0.3 AVDD 3.0 6.0 –0.3 3.5 1.2 2.3 4.5 V ≤ AVREF1 ≤ AVDD 3.5 V ≤ AVREF1 ≤ AVDD 10 TYP. 10 MAX. 10 ±0.4 ±0.7 ±1/2 60 60 10 10 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±3.5 ±4.5 ±2.5 ±4.5 ±2.5 ±4.5 AVDD + 0.3 AVDD 3.0 6.0 33 MHz Version MIN. 10 TYP. 10 MAX. 10 ±0.4 ±0.7 ±1/2 bit %FSR %FSR LSB tCYK tCYK tCYK tCYK LSB LSB LSB LSB LSB LSB V V mA mA Unit
Notes 1. Excludes quantization error. 2. When VIAN = 0, the conversion result becomes 000H. When 0 < VIAN < AVREF1, conversion has 10-bit resolution. When AVREF1 ≤ VIAN ≤ AVDD, the conversion result becomes 3FFH.
34
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter Symbol Conditions 25 MHz Version MIN. Resolution Overall error — — Load condition: 2 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 Load condition: 2 MΩ, 30 pF AVREF2 = 0.75VDD AVREF3 = 0.25VDD Load condition: 4 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 Load condition: 4 MΩ, 30 pF AVREF2 = 0.75VDD AVREF3 = 0.25VDD Load condition: 2 MΩ, 30 pF 8 0.75VDD 0 DACS0, DACS1 = 55H 2 4 VDD 0.25VDD 0.75VDD 0 2 4 8 TYP. 8 MAX. 8 0.8 33 MHz Version MIN. 8 TYP. 8 MAX. 8 0.8 bit % Unit
—
1.0
1.0
%
—
0.6
0.6
%
—
0.8
0.8
%
Settling time Output resistance AVREF2 input voltage AVREF3 input voltage Resistance between AVREF2 and AVREF3
— RO AVREF2 AVREF3 RAIREF
10 8
10
µs
kΩ
VDD 0.25VDD
V V kΩ
Data Sheet U13188EJ4V0DS00
35
µPD703003A, 703004A, 703025A
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.00 ± 0.20 14.00 ± 0.20 14.00 ± 0.20 16.00 ± 0.20 1.00 1.00 0.22 + 0.05 − 0.04 0.08 0.50 (T.P.) 1.00 ± 0.20 0.50 ± 0.20 0.17 + 0.03 − 0.07 0.08 1.40 ± 0.05 0.10 ± 0.05 3°+7° −3° 1.60 MAX.
S100GC-50-8EU, 8EA-2
36
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
5. RECOMMENDED SOLDERING CONDITIONS
The µPD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representatives. Table 5-1. Soldering Conditions
µPD703003AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703003AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703004AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703004AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703025AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm) µPD703025AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) Pin temperature: 300°C max., Time 3 seconds max. (per pin row) Recommended Condition Symbol IR35-107-2
VPS
VP15-107-2
Partial heating
—
Note After opening a dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U13188EJ4V0DS00
37
µPD703003A, 703004A, 703025A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
RELATED DOCUMENTS
µPD703003 Data Sheet (U12261E) µPD70F3003 Data Sheet (U12036E) µPD70F3003A, 70F3025A Data Sheet (U13189E)
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850 Family and V853 are trademarks of NEC Corporation.
38
Data Sheet U13188EJ4V0DS00
µPD703003A, 703004A, 703025A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
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NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
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Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U13188EJ4V0DS00
39
µPD703003A, 703004A, 703025A
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
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