UPD750006A

DATA SHEET MOS INTEGRATED CIRCUIT µPD750004,750006,750008,750004(A),750006(A),750008(A) 4 BIT SINGLE-CHIP MICROCONTROLLER The µPD750008 is one of the 75XL series 4-bit single-chip microcontrollers, which provide data processing capability equal to that of an 8-bit microcontroller. The µPD750008 is an advanced model of the µPD75008. It features an enhanced CPU function and enables highspeed operation at a low voltage of 2.2 V. It can be substituted for the µPD75008. In addition, it is best suited to applications using batteries. The µPD750008(A) has a higher reliability than the µ PD750008. A built-in one-time PROM product, µ PD75P0016, is also available. It is suitable for small-scale production and evaluation of application systems. The following user’s manual describes the details of the functions of the µPD750008. Be sure to read it before designing application systems. µPD750008 User’s Manual: U10740E FEATURES • Capable of low-voltage operation: VDD = 2.2 to 5.5 V • Internal memory Program memory (ROM) : 4096 × 8 bits (µPD750004 and µPD750004(A)) : 6144 × 8 bits (µPD750006 and µPD750006(A)) : 8192 × 8 bits (µPD750008 and µPD750008(A)) Data memory (RAM) : 512 × 4 bits • Function for specifying the instruction execution time (useful for high-speed operation and saving power) 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (when operating at 4.19 MHz) 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (when operating at 6.0 MHz) 122 µs (when operating at 32.768 kHz) • Enhanced timer function (4 channels) • Can be easily substituted for the µPD75008 because this product succeeds to the functions and instructions of the µPD75008. APPLICATIONS • µPD750004, µPD750006, and µPD750008 Cordless telephones, radio devices, audio products, and home electric appliances • µPD750004(A), µPD750006(A), and µPD750008(A) Electrical equipment for automobiles The µPD750004, µPD750006, µPD750008, µPD750004(A), µPD750006(A), and µPD750008(A) differ only in quality grade. In this manual, the µPD750008 is described unless otherwise specified. Users of other than the µPD750008 should read µPD750008 as referring to the pertinent product. When the description differs among µPD750004, µPD750006, and µPD750008, they also refer to the pertinent (A) products. µPD750004 → µPD750004(A), µPD750006 → µPD750006(A), µPD750008 → µPD750008(A) The information in this document is subject to change without notice. Document No. U10738EJ3V0DS00 (3rd edition) Date Published February 1997 J Printed in Japan The mark shows major revised points. © 1994 1990 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) ORDERING INFORMATION Part number Package 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Quality grade Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special µPD750004CU-××× µPD750004GB-×××-3BS-MTX µPD750006CU-××× µPD750006GB-×××-3BS-MTX µPD750008CU-××× µPD750008GB-×××-3BS-MTX µPD750004CU(A)-××× µPD750004GB(A)-×××-3BS-MTX µPD750006CU(A)-××× µPD750006GB(A)-×××-3BS-MTX µPD750008CU(A)-××× µPD750008GB(A)-×××-3BS-MTX Remark ××× is a mask ROM code number. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. DIFFERENCES BETWEEN µPD75000× AND µPD75000×(A) Product number µPD750004 µPD750006 µPD750004(A) µPD750006(A) µPD750008(A) Special Item Quality grade µPD750008 Standard 2 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) FUNCTIONS Item Command execution time Function • 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz) • 122 µs (when the subsystem clock operates at 32.768 kHz) 4096 × 8 bits ( µPD750004) 6144 × 8 bits ( µPD750006) 8192 × 8 bits ( µPD750008) RAM General-purpose register I/O port CMOS input CMOS I/O 512 × 4 bits • When operating in 4 bits: 8 × 4 banks • When operating in 8 bits: 4 × 4 banks 8 18 Can incorporate 7 pull-up resistors that are specified with the software. Can directly drive the LED. Can incorporate 18 pull-up resistors that are specified with the software. Can directly drive the LED. Can withstand 13 V. Can incorporate pull-up resistors that are specified with the mask option. Total Timer 34 4 channels • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 1 channel • Basic interval timer/watchdog timer: 1 channel • lock timer: 1 channel Internal memory ROM N-ch open drain I/O 8 Serial interface • Three-wire serial I/O mode ... switchable between the start LSB and the start MSB • Two-wire serial I/O mode • SBI mode 16 bits Bit sequential buffer (BSB) Clock output (PCL) • Φ, 524 kHz, 262 kHz, 65.5 kHz (when the main system clock operates at 4.19 MHz) • Φ, 750 kHz, 375 kHz, 93.8 kHz (when the main system clock operates at 6.0 MHz) • 2 kHz, 4 kHz, 32 kHz (when the main system clock operates at 4.19 MHz or when the subsystem clock operates at 32.768 kHz) Buzzer output (BUZ) • 2.93 kHz, 5.86 kHz, 46.9 kHz (when the main system clock operates at 6.0 MHz) Vectored interrupt External : Internal : External : Internal : 3 4 1 1 Test input System clock oscillator Standby Operating ambient temperature range Supply voltage Package • • Ceramic or crystal oscillator for main system clock Crystal oscillator for subsystem clock STOP/HALT mode TA = -40 to +85 °C VDD = 2.2 to 5.5 V 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 3 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ......................................................................................... BLOCK DIAGRAM ...................................................................................................................... PIN FUNCTIONS ......................................................................................................................... 3.1 3.2 3.3 3.4 PORT PINS ...................................................................................................................................... NON-PORT PINS ............................................................................................................................ PIN INPUT/OUTPUT CIRCUITS ..................................................................................................... CONNECTION OF UNUSED PINS ................................................................................................ 6 8 9 9 10 11 13 4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION ........................................................................ 4.1 4.2 DIFFERENCES BETWEEN Mk Ι MODE AND Mk ΙΙ MODE ........................................................ SETTING OF THE STACK BANK SELECTION REGISTER (SBS) ............................................ 14 14 15 5. 6. MEMORY CONFIGURATION ..................................................................................................... PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 DIGITAL I/O PORTS ....................................................................................................................... CLOCK GENERATOR .................................................................................................................... CONTROL FUNCTIONS OF SUBSYSTEM CLOCK OSCILLATOR ............................................ CLOCK OUTPUT CIRCUIT ............................................................................................................ BASIC INTERVAL TIMER/WATCHDOG TIMER ........................................................................... CLOCK TIMER ................................................................................................................................ TIMER/EVENT COUNTER .............................................................................................................. SERIAL INTERFACE ...................................................................................................................... BIT SEQUENTIAL BUFFER ........................................................................................................... 16 21 21 21 23 24 25 26 27 30 32 7. 8. 9. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ................................................................ STANDBY FUNCTION................................................................................................................ RESET FUNCTION ..................................................................................................................... 33 35 36 39 40 53 67 10. MASK OPTION ........................................................................................................................... 11. INSTRUCTION SET .................................................................................................................... 12. ELECTRICAL CHARACTERISTICS .......................................................................................... 13. CHARACTERISTIC CURVE (REFERENCE VALUES) ............................................................. 4 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 14. PACKAGE DRAWINGS .............................................................................................................. 15. RECOMMENDED SOLDERING CONDITIONS ......................................................................... APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ...................... APPENDIX B DEVELOPMENT TOOLS .......................................................................................... APPENDIX C RELATED DOCUMENTS .......................................................................................... 70 73 74 76 80 5 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 1. PIN CONFIGURATION (TOP VIEW) • 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) µPD750004CU-×××, µ PD750004CU(A)-××× µPD750006CU-×××, µ PD750006CU(A)-××× µPD750008CU-×××, µPD750008CU(A)-××× XT1 XT2 RESET X1 X2 P33 P32 P31 P30 P81 P80 P03/SI/SB1 P02/SO/SB0 P01/SCK P00/INT4 P13/TI0 P12/INT2 P11/INT1 P10/INT0 IC VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ IC : Internally connected (Connect directly to VDD.) 6 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) • 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) µPD750004GB-×××-3BS-MTX, µPD750004GB(A)-×××-3BS-MTX µPD750006GB-×××-3BS-MTX, µPD750006GB(A)-×××-3BS-MTX µPD750008GB-×××-3BS-MTX, µPD750008GB(A)-×××-3BS-MTX P20/PTO0 P21/PTO1 P10/INT0 P11/INT1 P12/INT2 P23/BUZ P73/KR7 P22/PCL VDD P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53 P52 P51 P50 1 2 3 4 5 6 7 8 9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 NC IC P13/TI0 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P80 P81 P30 P31 P32 P33 10 11 23 12 13 14 15 16 17 18 19 20 21 22 NC P43 P42 P41 P40 XT1 XT2 RESET X1 IC : Internally connected (Connect directly to VDD.) PIN NAMES P00 - 03 P10 - 13 P20 - 23 P30 - 33 P40 - 43 P50 - 53 P60 - 63 P70 - 73 P80, 81 SCK SI : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Key Return 0 - 7 Serial Clock Serial Input SO SB0, SB1 RESET TI0 BUZ PCL INT0, 1, 4 INT2 X1, X2 XT1, XT2 NC IC : : : : : : : : : : : : Serial Output Serial Data Bus 0, 1 Reset Timer Input 0 Programmable Timer Output 0, 1 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 No Connection Internally Connected PTO0, PTO1 : KR0 - KR7 : VSS X2 7 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/ WATCHDOG TIMER BIT SEQ. BUFFER (16) PROGRAM COUNTER CY ALU INTBT TI0/P13 PTO0/P20 8-BIT TIMER/EVENT COUNTER #0 INTT0 TOUT0 SP (8) SBS PORT 0 4 P00 - P03 BANK PORT 1 4 P10 - P13 PTO1/P21 8-BIT TIMER COUNTER #1 INTT1 PORT 2 GENERAL REGISTER PORT 3 PROGRAM MEMORYNote (ROM) 4 P20 - P23 4 P30 - P33 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 DECODE AND CONTROL DATA MEMORY (RAM) 512 × 4 BITS PORT 4 4 P40 - P43 PORT 5 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60KR7/P73 INTERRUPT CONTROL 8 4 P50 - P53 PORT 6 4 P60 - P63 PORT 7 fx/2N WATCH TIMER INTW CLOCK CLOCK OUTPUT DIVIDER CONTROL CPU CLOCK Φ SYSTEM CLOCK GENERATOR SUB MAIN PORT 8 STAND BY CONTROL 4 P70 - P73 BUZ/P23 2 P80, P81 PCL/P22 XT1 XT2 X1 X2 IC VDD VSS RESET Note The ROM capacity depends on the product. 8 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 3. PIN FUNCTIONS 3.1 PORT PINS Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 - P33 I/O I/O Input/ output Input I/O I/O I/O Input Shared pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 PTO0 PTO1 PCL BUZ Programmable 4-bit I/O port (PORT3). I/O can be specified bit by bit. Built-in pull-up resistors can be connected by software in units of 4 bits. N-ch open-drain 4-bit I/O port (PORT4). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 13 V in open-drain mode. N-ch open-drain 4-bit I/O port (PORT5). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 13 V in open-drain mode. Programmable 4-bit I/O port (PORT6). I/O can be specified bit by bit. Built-in pull-up resistors can be connected by software in units of 4 bits. × Input E-B 4-bit input port (PORT1). Built-in pull-up resistors can be connected by software in units of 4 bits. A noise eliminator can be selected only when the P10/INT0 pin is used. 4-bit I/O port (PORT2). Built-in pull-up resistors can be connected by software in units of 4 bits. × Input Function 4-bit input port (PORT0). For P01 - P03, built-in pull-up resistors can be connected by software in units of 3 bits. 8-bit I/O × When reset Input I/O circuit typeNote 1 B F F -A -B -C -C M B × Input E-B P40 - P43 Notes 2 I/O - High level (when pull-up resistors are provided) or high impedance High level (when pull-up resistors are provided) or high impedance Input M-D P50 - P53Notes 2 I/O - M-D P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 I/O KR0 KR1 KR2 KR3 F -A I/O KR4 KR5 KR6 KR7 4-bit I/O port (PORT7). Built-in pull-up resistors can be connected by software in units of 4 bits. Input F -A I/O - 2-bit I/O port (PORT8). Built-in pull-up resistors can be connected by software in units of 2 bits. × Input E-B Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. When pull-up resistors that can be specified with the mask option are not incorporated (when pins are used as N-ch open-drain input ports), the input leak low current increases when an input instruction or bit operation instruction is executed. 9 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 3.2 NON-PORT PINS Input/ output Input Shared pin P13 I/O circuit typeNote 1 B Pin name TI0 Function Inputs external event pulse to the timer/event counter Timer/event counter output Timer counter output Clock output Arbitrary frequency output (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (both rising and falling edges are detected) Edge detection vectored interrupt input Note 2 (detection edge selectable). A noise eliminator Note 3 can be selected when INT0/P10 is used. Rising edge detection testable input Falling edge detection testable input Falling edge detection testable input Crystal/ceramic connection pin for main system clock generation. When external clock signal is used, it is applied to X1, and its reverse phase signal is applied to X2. Crystal connection pin for subsystem clock generation. When external clock signal is used, it is applied to XT1, and it reverse phase signal is applied to XT2. XT1 can be used as a 1-bit input (test). System reset input (active low) Internally connected. (To be connected directly to VDD) Positive power supply Ground potential Note 3 When reset Input -C PTO0 PTO1 PCL BUZ Output P20 P21 P22 P23 Input E-B SCK SO/SB0 I/O P01 P02 Input F F -A -B SI/SB1 P03 M -C INT4 Input P00 B INT0 INT1 INT2 KR0 - KR3 KR4 - KR7 X1 X2 Input P10 P11 Input B -C Input I/O I/O Input - P12 P60 - P63 P70 - P73 - Input Input - F F -A -A - XT1 Input - - - XT2 - RESET IC Input - - - B - VDD VSS - - - - Notes 1. The circle ( 3. Asynchronous ) indicates the Schmitt trigger input. 2. With a noise eliminator/asynchronously selectable 10 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuit of each µPD750008 pin is shown below in a simplified manner. Type A Type D VDD Data VDD P-ch OUT P-ch IN Output disable N-ch N-ch CMOS input buffer Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type B Type E-B VDD P.U.R. P.U.R. enable P-ch IN Data Type D Output disable IN/OUT Schmitt trigger input with hysteresis Type A P.U.R.: Pull-Up Resistor Type B-C Type F-A VDD VDD P.U.R. P.U.R. P.U.R. enable P.U.R. enable Data Type D Output disable P-ch P-ch IN/OUT IN Type B P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor 11 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Type F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch VDD P-ch IN/OUT P-ch Type M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT Data Output disable N-ch P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor Type M-D VDD P.U.R. (Mask option) N-ch (Withstand voltage: +13 V) IN/OUT Data Output disable Input instruction VDD P-ch P.U.RNote Voltage restriction circuit (Withstand voltage: +13 V) P.U.R.: Pull-Up Resistor Note Pull-up resistor that operates only when pull-up resistors that can be specified with the mask option are not incorporated and an input instruction is executed. (When the pin is low, the current flows from VDD to the pin.) 12 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 3.4 CONNECTION OF UNUSED PINS Table 3-1 Connection of Unused Pins Pin name P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 - P12/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30 - P33 P40 - P43 Input state Input state Recommended connection To be connected to VSS or VDD To be connected to VSS or VDD through a separate resistor To be connected to VSS To be connected to VSS or VDD : To be connected to VSS or VDD through a separate resistor Output state : To be left open : To be connected to VSS (Do not connect to a pull-up resistor specified with a mask option.) Output state : To be connected to VSS P50 - P53 P60/KR0 - P63/KR3 P70/KR4 - P73/KR7 P80, P81 XT1Note XT2Note IC Input state : To be connected to VSS or VDD through a separate resistor Output state : To be left open To be connected to VSS To be left open To be connected directly to VDD Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the builtin feedback resistor). 13 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION 4.1 DIFFERENCES BETWEEN Mk Ι MODE AND Mk ΙΙ MODE The CPU of the µPD750008 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable. Bit 3 of the stack bank selection register (SBS) determines the mode. • Mk Ι mode: • Mk ΙΙ mode: This mode has the upward compatibility with the µPD75008. It can be used in the 75XL CPUs having a ROM of up to 16 KB. This mode is not compatible with the µPD75008. It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more. Table 4-1 shows the differences between Mk Ι mode and Mk ΙΙ mode. Table 4-1 Differences between Mk Ι Mode and Mk ΙΙ Mode Mk Ι mode Number of stack bytes in a subroutine instruction BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 3 machine cycles 2 machine cycles 4 machine cycles 3 machine cycles 2 bytes Mk ΙΙ mode 3 bytes None Available Caution Mk ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL series. This mode enhances a software compatibility with products whose program area is larger than 16K bytes. In Mk ΙΙ mode, one more stack byte is required for execution of subroutine call instructions per stack compared with Mk Ι mode. When a CALL !addr or CALLF !faddr instruction is executed, it takes one more machine cycle. Therefore, Mk Ι mode should be used for applications for which RAM efficiency or processing capabilities is more critical than a software compatibility. 14 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 4.2 SETTING OF THE STACK BANK SELECTION REGISTER (SBS) The Mk Ι mode and Mk ΙΙ mode are switched by stack bank selection register. Fig. 4-1 shows the register configuration. The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk Ι mode, initialize the register to 100×BNote at the beginning of the program. To use the CPU in Mk ΙΙ mode, initialize it to 000× BNote. Note Specify the desired value in ×. Fig. 4-1 Address F84H 3 SBS3 2 SBS2 1 SBS1 Stack Bank Selection Register Format 0 SBS0 Symbol SBS Stack area designation 0 0 0 1 Memory bank 0 Memory bank 1 Other settings are inhibited. 0 Bit 2 must be set to 0. Mode switching designation 0 1 Mk ΙΙ mode Mk Ι mode Caution The CPU operates in Mk Ι mode after the RESET signal is issued, because bit 3 of SBS is set to 1. Set bit 3 of SBS to 0 (Mk ΙΙ mode) to use the CPU in Mk ΙΙ mode. 15 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 5. MEMORY CONFIGURATION • Program memory (ROM) : 4096 × 8 bits (0000H-0FFFH): µPD750004 6144 × 8 bits (0000H-17FFH): µPD750006 8192 × 8 bits (0000H-1FFFH): µPD750008 • 0000H to 0001H Vector address table for holding the RBE and MBE values and program start address when a RESET signal is issued (allowing a reset start at an arbitrary address) • 0002H to 000DH Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt (allowing interrupt processing to be started at an arbitrary address) • 0020H to 007FH Table area referenced by the GETI instruction • Data memory (RAM) • Data area : 512 × 4 bits (000H to 1FFH) • Peripheral hardware area: 128 × 4 bits (F80H to FFFH) 16 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Fig. 5-1 Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 2 H MBE RBE 0 0 INTBT/INT4 INTBT/INT4 0 0 4 H MBE RBE 0 0 INT0 INT0 0 0 6 H MBE RBE 0 0 INT1 INT1 0 0 8 H MBE RBE 0 0 INTCSI INTCSI 0 0 A H MBE RBE 0 0 INTT0 INTT0 0 0 C H MBE RBE 0 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address Program Memory Map (in µPD750004) 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF ! faddr instruction entry address 0 0 0 H MBE RBE Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16 020H GETI instruction reference table 07FH 080H BRCB !caddr instruction branch address 7FFH 800H Branch destination address and subroutine entry address when GETI instruction is executed FFFH Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 17 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Fig. 5-2 Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0 0 0 6 H MBE RBE 0 INT1 INT1 0 0 0 8 H MBE RBE 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address Program Memory Map (in µPD750006) 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) BRCB !caddr instruction branch address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16 0 0 0 0 H MBE RBE 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 17FFH Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 18 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Fig. 5-3 Address 7 6 5 0 Internal reset start address Internal reset start address 0 0 0 2 H MBE RBE 0 INTBT/INT4 INTBT/INT4 0 0 0 4 H MBE RBE 0 INT0 INT0 0 0 0 6 H MBE RBE 0 INT1 INT1 0 0 0 8 H MBE RBE 0 INTCSI INTCSI 0 0 0 A H MBE RBE 0 INTT0 INTT0 0 0 0 C H MBE RBE 0 INTT1 INTT1 start address start address start address start address start address start address start address start address start address start address start address start address Program Memory Map (in µPD750008) 0 (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) (high-order 5 bits) (low-order 8 bits) BRCB !caddr instruction branch address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1 or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address -15 to -1, +2 to +16 0 0 0 0 H MBE RBE 0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 19 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Fig. 5-4 Data Memory Map Data memory Area for 000H general-purpose register 01FH 020H (32 × 4) Memory bank 256 × 4 (224 × 4) Data area Static RAM (512 × 4) 0 Stack areaNote 0FFH 100H 256 × 4 1 1FFH Not contained F80H Peripheral hardware area FFFH 128 × 4 15 Note Memory bank 0 or 1 can be selected as the stack area. 20 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 DIGITAL I/O PORTS The µPD750008 has the following three types of I/O port: • 8 CMOS input pins (PORT0 and PORT1) • 18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8) • 8 N-ch open-drain I/O pins (PORT4 and PORT5) Total: 34 pins Table 6-1 Digital Ports and Their Features Port name PORT0 Function 4-bit input Operation and feature When the serial interface function is used, dual-function pins function as output pins in some operation modes. 4-bit input port Remarks Also used as INT4, SCK, SO/SB0, or SI/SB1. Also used as INT0, INTI, INT2 or TI0. Also used as PTO0, PTO1, PCL, or BUZ. PORT3 PORT4 PORT5 4-bit I/O (N-ch open-drain can withstand 13 V) Allows input or output mode setting in units of 1 bit. Allows input or output mode setting in units of 4 bits. Whether to use pull-up resistors can be specified bit by bit with the mask option. Allows input or output mode setting in units of 1 bit. Allows input or output mode setting in units of 4 bits. 2-bit I/O Ports 4 and 5 can be paired, allowing data I/O in units of 8 bits. - PORT1 PORT2 4-bit I/O Allows input or output mode setting in units of 4 bits. PORT6 4-bit I/O PORT7 Ports 6 and 7 can be paired, allowing data I/O in units of 8 bits. Also used as one of KR0 to KR3. Also used as one of KR4 to KR7. - PORT8 Allows input or output mode setting in units of 2 bits. 6.2 CLOCK GENERATOR The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Fig. 6-1 shows the configuration of the clock generator. Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control register (SCC). The main system clock and subsystem clock are used. The instruction execution time can be made variable. • 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (when the main system clock is at 4.19 MHz) • 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (when the main system clock is at 6.0 MHz) • 122 µs (when the subsystem clock is at 32.768 kHz) 21 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Fig. 6-1 Clock Generator Block Diagram • • • • • • • XT1 Subsystem clock generator fXT Clock timer XT2 X1 Basic interval timer (BT) Timer/event counter Timer counter Serial interface Clock timer INT0 noise eliminator Clock output circuit X2 Main system clock generator fX 1/2 1/4 1/16 1/1 to 1/4096 Frequency divider WM.3 SCC SCC3 SCC0 Internal bus Oscillator disable signal Selector Frequency divider Selector 1/4 Φ  • CPU  • INT0 noise  eliminator  • Clock   output  circuit PCC PCC0 PCC1 4 HALT Note HALT flip-flop PCC2 S STOP Note PCC3 R Q PCC2, PCC3 clear signal STOP flip-flop Q S Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fX = Main system clock frequency 2. fXT = Subsystem clock frequency 3. Φ = CPU clock 4. PCC: Processor clock control register 5. SCC: System clock control register 6. One clock cycle (tCY) of the CPU clock (Φ) is equal to one machine cycle of an instruction. 22 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.3 CONTROL FUNCTIONS OF SUBSYSTEM CLOCK OSCILLATOR The subsystem clock oscillator of the µPD750008 subseries has two control functions to decrease the supply current. • The function to select with the software whether to use the built-in feedback resistorNote • The function to suppress the supply current by reducing the drive current of the built-in inverter when the supply voltage is high (VDD ≥ 2.7 V) Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-in feedback resistor), connect XT1 to VSS , and open XT2. This makes it possible to reduce the supply current required by the subsystem clock oscillator. Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See Fig. 6-2.) Fig. 6-2 Subsystem Clock Oscillator SOS.0 VDD Feedback resistor Inverter SOS.1 XT1 XT2 23 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.4 CLOCK OUTPUT CIRCUIT The clock output circuit outputs a clock pulse from the P22/PCL pin. This clock pulse is used for remote control waveform output, peripheral LSIs, etc. • Clock output (PCL): Φ, 524, 262, or 65.5 kHz (at 4.19 MHz) Φ, 750, 375, or 93.8 kHz (at 6.0 MHz) Fig. 6-3 From the clock generator Φ fX/23 Selector fX/24 fX/2 6 Clock Output Circuit Configuration Output buffer PCL/P22 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable. 24 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.5 BASIC INTERVAL TIMER/WATCHDOG TIMER The basic interval timer/watchdog timer has these functions: • Interval timer operation which generates a reference timer interrupt • Operation as a watchdog timer for detecting program crashes and resetting the CPU • Selection of wait time for releasing the standby mode and counting the wait time • Reading out the count value Fig. 6-4 Block Diagram of the Basic Interval Timer/Watchdog Timer From the clock generator fX /25 fX /2 7 Clear signal Clear signal MPX fX /2 fX /2 9 Basic interval timer (8-bit frequency divider) Set signal BT interrupt request flag 12 BT IRQBT Vectored interrupt request signal 3 Wait release signal for standby release BTM0 BTM 8 Internal bus WDTM 1 Internal reset signal SET1 Note BTM3 SET1Note BTM2 4 BTM1 Note Instruction execution 25 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.6 CLOCK TIMER The µPD750008 contains one channel for a clock timer. The clock timer provides the following functions: • Sets the test flag (IRQW) with a 0.5 sec interval. The standby mode can be released by IRQW. • The 0.5 second interval can be generated from either the main system clock (4.194304 MHz) or subsystem clock (32.768 kHz). • The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient for program debugging, testing, etc. • Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The frequency divider circuit can be cleared so that a zero-second start of the clock can be made. Fig. 6-5 Clock Timer Block Diagram fw 27 fX 128 (32.768 kHz) fXT (32.768 kHz) (256 Hz: 3.91 ms) From the clock generator fW (32.768 kHz) Selector Frequency divider (4 kHz) (2 kHz) fw 2 14 Selector INTW IRQW set signal 2 Hz 0.5 sec Clear fw 2 3 fw 2 4 Selector Output buffer P23/BUZ WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 PORT2.3 P23 output latch Bit 2 of PMGB Port 2 input/ output mode 8 Bit test instruction Internal bus ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz. 26 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.7 TIMER/EVENT COUNTER The µPD750008 contains one channel for a timer/event counter and one channel for a timer counter. Figs. 6-6 and 6-7 show their configurations. The timer/event counter provides the following functions: • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTOn pin (n = 0, 1) • Event counter operation (channel 0 only) • Divides the TI0 pin input by N and outputs to the PTO0 pin (frequency divider operation) (channel 0 only) • Supplies serial shift clock to the serial interface circuit (channel 0 only) • Count read function 27 28 Fig. 6-6 Timer/Event Counter Block Diagram Internal bus 8 TM0 TMOD0 Modulo register (8) T0 enable flag P20 output latch signal Port 2 input/ output mode SET1Note 8 TOE0 PORT2.0 8 Bit 2 of PMGB TM06 TM05 TM04 TM03 TM02 Port input buffer TOUT0 Match 8 Comparator (8) 8 Reset T0 TOUT flip-flop To serial interface PTO0/P20 Output buffer INTT0 Input buffer Count register (8) CP Clear signal TI0/P13 fX/24 6 From the clock fX/2 generator fX/28 fX/210 Timer operation start signal MPX IRQT0 set signal RESET IRQT0 clear signal µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Note Instruction execution Fig. 6-7 Timer Counter Block Diagram Internal bus 8 TM1 TMOD1 Modulo register (8) T1 enable flag P21 output latch Port 2 input/ output mode SET1Note 8 TOE1 PORT2.1 8 Bit 2 of PMGB 0 TM16 TM15 TM14 TM13 TM12 8 Match Comparator (8) 8 Reset T1 TOUT flip-flop Output buffer PTO1/P21 INTT1 Count register (8) CP Clear signal IRQT1 set signal From the clock generator      Timer operation start signal fX/26 fX/28 fX/210 fX/212 MPX RESET IRQT1 clear signal Note Instruction execution µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 29 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.8 SERIAL INTERFACE µPD750008 has an 8-bit synchronous serial interface. The serial interface has the following four types of mode. • Operation stop mode • Three-wire serial I/O mode • Two-wire serial I/O mode • SBI mode 30 Fig. 6-8 Serial Interface Block Diagram Internal bus 8/4 8 8 Slave address register (SVA) (8) Coincidence RELT signal Address comparator (8) SET CLR SO latch Shift register (SIO) (8) D Q CMDT SBIC 8 Bit test CSIM Bit test Bit manipulation P03/SI/SB1 Selector ACKT Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD ACKE P02/SO/SB0 Busy/ acknowledge output circuit Selector BSYE P01/SCK INTCSI Serial clock counter INTCSI control circuit IRQCSI set signal 3 P01 output latch Serial clock control circuit Serial clock selector fx/2 4 fx/2 fx/26 TOUT0 (from timer/event counter) External SCK µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 31 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 6.9 BIT SEQUENTIAL BUFFER: 16 BITS The bit sequential buffer (BSB) is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. Fig. 6-9 Address Bit Symbol 3 FC3H 2 1 0 3 Bit Sequential Buffer Format FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L = FH L = CH L = BH L = 8H L = 7H L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. In pmem.@L addressing, bit specification is shifted according to the L register. 2. In pmem.@L addressing, the bit sequential buffer can be manipulated at any time regardless of MBE/ MBS specification. 32 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS The µPD750008 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge detection testable input pins. The interrupt control circuit of the µPD750008 has the following functions. (1) Interrupt functions • Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using the interrupt flag (IE×××) and interrupt master enable flag (IME). • The interrupt start address can be set arbitrarily. • Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS) • Test function of an interrupt request flag (IRQ×××) (The software can confirm that an interrupt occurred.) • Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.) (2) Test functions • Whether test request flags (IRQ×××) are issued can be checked with software. • Release of the standby mode (A test source to be released can be selected with test enable flags.) 33 Selector 34 Fig. 7-1 Internal bus Interrupt Control Circuit Block Diagram 2 IME IST1 IST0 IPS 1 4 IM2 Interrupt enable flag (IE×××) IM1 IM0 INTBT IRQBT VRQn Decoder INT4/P00 IRQ4 Both-edge detector IRQ0 INT0/P10 Note Edge detector IRQ1 INT1/P11 Edge detector IRQCSI INTCSI Priority control circuit Vector table address generator INTT0 IRQT0 INTT1 IRQT1 INTW IRQW INT2/P12 IRQ2 Rising edge detector Selector Standby release signal KR0/P60 KR7/P73 Falling edge detector IM2 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Note Noise eliminator (Standby release is not possible when the noise eliminator is selected.) µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 8. STANDBY FUNCTION The µ PD750008 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation while waiting for program execution. Table 8-1 Item Instruction for setting System clock for setting Operation status Mode Standby Mode Statuses HALT mode HALT instruction Can be set either with the main system clock or the subsystem clock. Only the CPU clock Φ stops its operation (oscillation continues). Can operate only at main system clock oscillation. (IRQBT is set at reference time intervals.) Can operate only when external SCK input is selected as the serial clock or at main system clock oscillation. Can operate only when TI0 pin input is specified as the count clock or at main system clock oscillation. Can operate.Note 1 Can operate. STOP mode STOP instruction Can be set only when operating on the main system clock. The main system clock stops its operation. Clock oscillator Basic interval timer/watchdog timer Serial interface Does not operate. Can operate only when the external SCK input is selected for the serial clock. Timer/event counter Can operate only when the TI0 pin input is selected for the count clock. Timer counter Clock timer Does not operate. Can operate when f XT is selected as the count clock. INT1, INT2, and INT4 can operate. Only INT0 cannot operate.Note 2 Does not operate. External interrupt CPU Release signal An interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the generation of a RESET signal Notes 1. Operation is possible only when the main system clock operates. 2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register (IM0) (when IM02 = 1). 35 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 9. RESET FUNCTION The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Fig. 9-1 shows the configuration of the reset circuit. Fig. 9-1 Configuration of Reset Functions RESET Internal reset signal Reset signal from basic interval timer/watchdog timer WDTM Internal bus When the RESET signal is generated, all hardware is initialized as indicated in Table 9-1. Fig. 9-2 shows the reset operation timing. Fig. 9-2 Reset Operation by Generation of RESET Signal Wait Note RESET signal is generated Operating mode or standby mode HALT mode Operating mode Internal reset operation Note Either of the following two values can be selected by a mask option: 217 /fX (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz) 215 /fX (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz) 36 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Table 9-1 Status of the Hardware after a Reset (1/2) Generation of a RESET signal in a standby mode Generation of a RESET signal during operation 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. 5 low-order bits at address 0000H in program memory are set in PC bits 12 to 8, and the data at address 0001H are set in PC bits 7 to 0. Undefined 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 Hardware Program counter (PC) µPD750004 4 low-order bits at address 0000H in program memory are set in PC bits 11 to 8, and the data at address 0001H are set in PC bits 7 to 0. 5 low-order bits at address 0000H in program memory are set in PC bits 12 to 8, and the data at address 0001H are set in PC bits 7 to 0. Held 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 µPD750006, 750008 PSW Carry flag (CY) Skip flags (SK0 to SK2) Interrupt status flags (IST0, IST1) Bank enable flags (MBE, RBE) Stack pointer (SP) Stack bank selection register (SBS) Data memory (RAM) General-purpose registers (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Basic interval timer/ watchdog timer Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Timer/event counter Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT flip-flop Timer counter Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT flip-flop Clock timer Serial interface Mode register (WM) Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) 0 FFH 0 0, 0 0 FFH 0 0, 0 0 Held 0 0 Held 0 FFH 0 0, 0 0 FFH 0 0, 0 0 Undefined 0 0 Undefined 37 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Table 9-1 Status of the Hardware after a Reset (2/2) Generation of a RESET signal in a standby mode 0 0 0 0 Reset (0) 0 0 0, 0, 0 Generation of a RESET signal during operation 0 0 0 0 Reset (0) 0 0 0, 0, 0 Hardware Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Sub-oscillator control register (SOS) Interrupt Interrupt request flag (IRQ××× ) Interrupt enable flag (IE××× ) Priority selection register (IPS) INT0, INT1, and INT2 mode registers (IM0, IM1, IM2) Digital ports Output buffer Output latch I/O mode registers (PMGA, PMGB, PMGC) Pull-up resistor specification registers (POGA, POGB) Bit sequential buffers (BSB0 to BSB3) Off Clear (0) 0 Off Clear (0) 0 0 0 Held Undefined 38 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 10. MASK OPTION The µPD750008 has the following mask options: • Mask option of P40 to P43 and P50 to P53 Can specify whether to incorporate the pull-up resistor. 1 2 The pull-up resistor is incorporated bit by bit. The pull-up resistor is not incorporated. • Mask option of standby function Can specify the wait time with the RESET signal. 1 2 17/fX (21.8 ms at fX = 6.0 MHz, 31.3 ms at fX = 4.19 MHz) 2 2 15/fX (5.46 ms at fX = 6.0 MHz, 7.81 ms at fX = 4.19 MHz) • Mask option of subsystem clock Can specify whether to enable the built-in feedback resistor. 1 2 The built-in feedback resistor is enabled (it is turned on or off by software). The built-in feedback resistor is disabled (it is cut by hardware). 39 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 11. INSTRUCTION SET (1) Operand identifier and its descriptive method The operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions. (For details, refer to RA75X Assembler Package User's Manual: Language (EEU-1363).) For descriptions in which alternatives exist, one element should be selected. Capital letters and plus and minus signs are keywords; therefore, they should be described as they are. For immediate data, the appropriate numerical values or labels should be described. The symbols of register flags can be used as a label instead of mem, fmem, pmem, and bit. (For details, refer to µPD750008 User’s Manual (U10740E).) However, there are some restrictions on usable labels for fmem and pmem. Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr X, A, B, C, D, E, H, L X, B, C, D, E, H, L Description XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H - FBFH, FF0H - FFFH immediate data or label FC0H - FFFH immediate data or label 0000H - 0FFFH immediate data or label (µPD750004) 0000H - 17FFH immediate data or label (µPD750006) 0000H - 1FFFH immediate data or label (µPD750008) 0000H - 0FFFH immediate data or label (µPD750004) 0000H - 17FFH immediate data or label (µPD750006) 0000H - 1FFFH immediate data or label (µPD750008) 12-bit immediate data or label 11-bit immediate data or label 20H - 7FH immediate data (however, bit 0 = 0) or label PORT0 - PORT8 IEBT, IET0, IET1, IE0 - IE2, IE4, IECSI, IEW RB0 - RB3 MB0, MB1, MB15 addr1(for Mk ΙΙ mode only) caddr faddr taddr PORTn IE××× RBn MBn Note Only even address can be specified for 8-bit data processing. 40 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) (2) Symbol definitions in operation description A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IE××× RBS MBS PCC . (×× ) ××H : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Extended register pair (XA') : Extended register pair (BC') : Extended register pair (DE') : Extended register pair (HL') : Program counter : Stack pointer : Carry flag; Bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority specification register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Address bit delimiter : Contents addressed by ×× : Hexadecimal data PORTn : Port n (n = 0 to 8) 41 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) (3) Symbols used for the addressing area column *1 *2 *3 MB = MBE • MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (000H - 07FH), MB = 15 (F80H - FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 *5 *6 MB = 15, fmem = FB0H - FBFH, FF0H - FFFH MB = 15, pmem = FC0H - FFFH addr = 0000H - 0FFFH (µPD750004), 0000H - 17FFH ( µPD750006) 0000H - 1FFFH (µPD750008) *7 addr, addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H - 0FFFH (µ PD750004) 0000H - 0FFFH (PC12 = 0: µPD750006, 750008) 1000H - 17FFH (PC12 = 1: µPD750006) 1000H - 1FFFH (PC12 = 1: µ PD750008) *9 * 10 * 11 faddr = 0000H - 07FFH taddr = 0020H - 007FH Mk ΙΙ mode only addr1 = 0000H - 0FFFH ( µ PD750004) 0000H - 17FFH (µPD750006) 0000H - 1FFFH ( µPD750008) Program memory addressing Data memory addressing Remarks 1. MB indicates the memory bank that can be accessed. 2. For *2, MB = 0 regardless of MBE and MBS settings. 3. For *4 and *5, MB = 15 regardless of MBE and MBS settings. 4. For *6 to *11, each addressable area is indicated. (4) Description of machine cycle column S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes as follows: • When no skip is performed • When a 3-byte instructionNote is skipped : S=0 : S=2 • When a 1-byte or 2-byte instruction is skipped : S = 1 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions. Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle (= tCY) of the CPU clock (Φ), and four types of times are available for selection according to the PCC setting. 42 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 A ← n4 reg1 ← n4 XA ← n8 HL ← n8 rp2 ← n8 A ← (HL) A ← (HL), then L ← L + 1 A ← (HL), then L ← L - 1 A ← (rpa1) XA ← (HL) (HL) ← A (HL) ← XA A ← (mem) XA ← (mem) (mem) ← A (mem) ← XA A ← reg XA ← rp' reg1 ← A rp'1 ← XA A ↔ (HL) A ↔ (HL), then L ← L + 1 A ↔ (HL), then L ← L - 1 A ↔ (rpa1) XA ↔ (HL) A ↔ (mem) XA ↔ (mem) A ↔ reg1 XA ↔ rp' • µPD750004 XA ← (PC11-8 + DE) ROM • µPD750006, 750008 XA ← (PC12-8 + DE) ROM XA, @PCXA 1 3 • µPD750004 XA ← (PC11-8 + XA) ROM • µPD750006, 750008 XA ← (PC12-8 + XA) ROM XA, @BCDE XA, @BCXA 1 1 3 3 XA ← (BCDE) ROMNote XA ← (BCXA) ROMNote *6 *6 *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String A String B Group Mnemonic MOV Operand Operation Addressing area Skip condition String A Transfer A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HLA, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA XCH A, @HL A, @HL+ A, @HLA, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' Table reference MOVT XA, @PCDE Note Set register B to 0 in the µPD750004. Only the LSB is valid in register B in the µPD750006 and µPD750008. 43 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S Addressing area *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1 Skip condition Group Mnemonic Operand Operation CY ← (fmem.bit) CY ← (pmem7-2 + L3-2.bit(L1-0)) CY ← (H + mem3-0.bit) (fmem.bit) ← CY (pmem7-2 + L3-2.bit(L1-0)) ← CY (H + mem3-0.bit) ← CY A ← A + n4 XA ← XA + n8 A ← A + (HL) XA ← XA + rp' rp'1 ← rp'1 + XA A, CY ← A + (HL) + CY XA, CY ← XA + rp' + CY rp'1, CY ← rp'1 + XA + CY A ← A - (HL) XA ← XA - rp' rp'1 ← rp'1 - XA A, CY ← A - (HL) - CY XA, CY ← XA - rp' - CY rp'1, CY ← rp'1 - XA - CY Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Arithmetic ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA *1 borrow borrow borrow SUBC A, @HL XA, rp' rp'1, XA *1 AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA ∧ n4 A ← A ∧ (HL) XA ← XA ∧ rp' rp'1 ← rp'1 ∧ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp' rp'1 ← rp'1 ∨ XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp' rp'1 ← rp'1 ∨ XA A←A CY ← A0, A3 ← CY, An-1 ← An A←A reg ← reg + 1 rp1 ← rp1 + 1 (HL) ← (HL) + 1 (mem) ← (mem) + 1 reg ← reg - 1 rp' ← rp' - 1 *1 *1 *1 Accumulator manipulation Increment/ decrement RORC NOT INCS A A reg rp1 @HL mem reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH DECS reg rp' 44 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Group Mnemonic SKE Operand Operation Addressing area Skip condition reg = n4 Comparison reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY ← 1 CY ← 0 Skip if CY = 1 CY ← CY (mem.bit) ← 1 (fmem.bit) ← 1 (pmem 7-2 + L3-2.bit(L1-0)) ← 1 (H + mem3-0.bit) ← 1 (mem.bit) ← 0 (fmem.bit) ← 0 (pmem 7-2 + L3-2.bit(L1-0)) ← 0 (H + mem3-0.bit) ← 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 Skip if (H + mem 3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit(L1-0)) = 0 Skip if (H + mem 3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear Skip if (H + mem 3-0.bit) = 1 and clear CY ← CY CY ← CY ← CY ← CY ← CY ← CY ← CY ← CY ← *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem. @L @H+mem.bit CY = 1 Memory bit manipulation SET1 CLR1 mem.bit fmem.bit pmem. @L @H+mem.bit SKT mem.bit fmem.bit pmem. @L @H+mem.bit (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 SKF mem.bit fmem.bit pmem. @L @H+mem.bit (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H + mem.bit) = 0 SKTCLR fmem.bit pmem. @L @H+mem.bit (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 AND1 CY, fmem.bit CY, pmem. @L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem. @L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit ∧ (fmem.bit) CY ∧ (pmem7-2 + L 3-2.bit(L1-0 )) CY ∧ (H + mem3-0.bit) CY ∨ (fmem.bit) CY ∨ (pmem7-2 + L 3-2.bit(L1-0 )) CY ∨ (H + mem3-0.bit) CY ∨ (fmem.bit) CY ∨ (pmem7-2 + L 3-2.bit(L1-0 )) CY ∨ (H + mem3-0.bit) 45 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle Addressing area *6 Skip condition Group Mnemonic BRNote Operand Operation • µPD750004 PC11-0 ← addr The assembler selects the most adequate instruction from BR !addr, BRCB !caddr, or BR $addr. • µPD750006, 750008 PC12-0 ← addr The assembler selects the most adequate instruction from BR !addr, BRCB !caddr, or BR $addr. Branch addr addr1 - - • µPD750004 PC 11-0 ← addr1 The assembler selects the most adequate instruction from instructions below. • • • • BR !addr BRA !addr1 BRCB !caddr BR $addr1 *11 • µPD750006, 750008 PC 12-0 ← addr1 The assembler selects the most adequate instruction from instructions below. • • • • !addr 3 3 BR !addr BRA !addr1 BRCB !caddr BR $addr1 *6 • µPD750004 PC 11-0 ← addr • µPD750006, 750008 PC 12-0 ← addr $addr 1 2 • µPD750004 PC 11-0 ← addr • µPD750006, 750008 PC 12-0 ← addr *7 $addr1 1 2 • µPD750004 PC 11-0 ← addr1 • µPD750006, 750008 PC 12-0 ← addr1 Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 46 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 2 3 Group Mnemonic BR Operand Operation • µPD750004 PC 11-0 ← PC11-8 + DE • µPD750006, 750008 PC 12-0 ← PC12-8 + DE Addressing area Skip condition Branch PCDE PCXA 2 3 • µPD750004 PC 11-0 ← PC11-8 + XA • µPD750006, 750008 PC 12-0 ← PC12-8 + XA BCDE 2 3 • µPD750004 PC 11-0 ← BCDENote 1 • µPD750006, 750008 PC 12-0 ← BCDENote 2 *6 BCXA 2 3 • µPD750004 PC 11-0 ← BCXANote 1 *6 • µPD750006, 750008 PC 12-0 ← BCXANote 2 BRANote 3 !addr1 3 3 • µPD750004 PC 11-0 ← addr1 • µPD750006, 750008 PC 12-0 ← addr1 BRCB !caddr 2 2 • µPD750004 PC 11-0 ← caddr11-0 • µPD750006, 750008 PC 12-0 ← PC12 + caddr11-0 Subroutine stack control CALLANote 3 !addr1 3 3 • µPD750004 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 PC 11-0 ← addr1, SP ← SP - 6 • µPD750006, 750008 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, PC12 PC 12-0 ← addr1, SP ← SP - 6 *11 *8 *11 Notes 1. Set register B to 0. 2. Only the LSB is valid in register B. 3. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 47 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 3 3 Addressing area *6 Skip condition Group Mnemonic CALLNote Operand Operation • µPD750004 (SP - 3) ← MBE, RBE, 0, 0 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC11-0 ← addr, SP ← SP - 4 • µPD750006, 750008 (SP - 3) ← MBE, RBE, 0, PC12 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC12-0 ← addr, SP ← SP - 4 Subroutine stack control !addr 4 • µPD750004 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 PC11-0 ← addr, SP ← SP - 6 • µPD750006, 750008 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, PC12 PC12-0 ← addr, SP ← SP - 6 CALLFNote !faddr 2 2 • µPD750004 (SP - 3) ← MBE, RBE, 0, 0 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC11-0 ← 0 + faddr, SP ← SP - 4 • µPD750006, 750008 (SP - 3) ← MBE, RBE, 0, PC12 (SP - 4) (SP - 1) (SP - 2) ← PC11-0 PC12-0 ← 00 + faddr, SP ← SP - 4 *9 3 • µPD750004 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 PC11-0 ← 0 + faddr, SP ← SP - 6 • µPD750006, 750008 (SP - 2) ← ×, ×, MBE, RBE (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, PC12 PC12-0 ← 00 + faddr, SP ← SP - 6 Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 48 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 1 3 Group Mnemonic RETNote Operand Operation • µPD750004 PC11-0 ← (SP) (SP + 3) (SP + 2) MBE, RBE, 0, 0 ← (SP + 1), SP ← SP + 4 • µPD750006, 750008 PC11-0 ← (SP) (SP + 3) (SP + 2) MBE, RBE, 0, PC12 ← (SP + 1) SP ← SP + 4 Addressing area Skip condition Subroutine stack control 3 • µPD750004 ×, ×, MBE, RBE ← (SP + 4) 0, 0, 0, 0 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 6 • µPD750006, 750008 ×, ×, MBE, RBE ← (SP + 4) MBE, 0, 0, PC12 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 6 RETSNote 1 3+S • µPD750004 MBE, RBE, 0, 0 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 then skip unconditionally • µPD750006, 750008 MBE, RBE, 0 ← PC12 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 then skip unconditionally Uncondition 3+S • µPD750004 0, 0, 0, 0 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) ×, ×, MBE, RBE ← (SP + 4) SP ← SP + 6 then skip unconditionally • µPD750006, 750008 0, 0, 0, PC12 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) ×, ×, MBE, RBE ← (SP + 4) SP ← SP + 4 then skip unconditionally Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 49 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 1 3 Addressing area Skip condition Group Mnemonic RETINote 1 Operand Operation • µPD750004 MBE, RBE, 0, 0 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 • µPD750006, 750008 MBE, RBE, 0, PC12 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 • µPD750004 0, 0, 0, 0 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 • µPD750006, 750008 0, 0, 0, PC12 ← (SP + 1) PC11-0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 Subroutine stack control PUSH rp BS 1 2 1 2 (SP - 1)(SP - 2) ← rp, SP ← SP - 2 (SP - 1) ← MBS, (SP - 2) ← RBS, SP ← SP - 2 rp ← (SP + 1)(SP), SP ← SP + 2 MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 IME (IPS.3) ← 1 IE ××× ← 1 IME (IPS.3) ← 0 IE ××× ← 0 A ← PORTn XA ← PORTn+1,PORTn PORTn ← A PORTn+1 ,PORTn ← XA Set HALT Mode Set STOP Mode No Operation (n = 0 - 8) (n = 4, 6) (n = 2 - 8) (n = 4, 6) POP rp BS 1 2 1 2 Interrupt control EI IE××× DI IE××× 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2 1 Input/ output INNote 2 A, PORTn XA, PORTn OUTNote 2 PORTn, A PORTn, XA CPU control HALT STOP NOP (PCC.2 ← 1) (PCC.3 ← 1) Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 2. When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and 15, respectively. 50 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 2 2 1 2 2 3 Group Mnemonic SEL Operand Operation RBS ← n (n = 0 - 3) MBS ← n (n = 0, 1, 15) • µPD750004 When the TBR instruction is used Addressing area Skip condition Special RBn MBn GETINotes 1, 2 taddr *10 ......................................................... When the TCALL instruction is used (SP - 4) (SP - 1) (SP - 2) ← PC11-0 (SP - 3) ← MBE, RBE, 0, 0 PC 11-0 ← (taddr)3-0 + (taddr + 1) PC 11-0 ← (taddr)3-0 + (taddr + 1) ......................................................... When an instruction other than the TBR and TCALL instructions is used Execution of (taddr)(taddr + 1) instruction • µPD750006, 750008 When the TBR instruction is used SP ← SP - 4 ...................... Depends on the referenced instruction. ......................................................... When the TCALL instruction is used (SP - 4) (SP - 1) (SP - 2) ← PC11-0 (SP - 3) ← MBE, RBE, 0, PC12 PC 12-0 ← (taddr)4-0 + (taddr + 1) PC 12-0 ← (taddr)4-0 + (taddr + 1) ......................................................... When an instruction other than the TBR and TCALL instructions is used Execution of (taddr)(taddr + 1) instruction 3 • µPD750004 When the TBR instruction is used *10 SP ← SP - 4 ...................... Depends on the referenced instruction. ........................................................................ 4 When the TCALL instruction is used (SP - 6) (SP - 3) (SP - 4) ← PC11-0 (SP - 5) ← 0, 0, 0, 0 (SP - 2) ← ×, ×, MBE, RBE PC 11-0 ← (taddr)3-0 + (taddr + 1) PC 11-0 ← (taddr)3-0 + (taddr + 1) ........................................................................ 3 When an instruction other than the TBR and TCALL instructions is used Execution of (taddr)(taddr + 1) instruction SP ← SP - 6 ...................... Depends on the referenced instruction. Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only. 2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions. 51 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MachinBytes ing cycle 1 3 Addressing area *10 Skip condition Group Mnemonic GETINotes 1, 2 Operand Operation • µPD750006, 750008 When the TBR instruction is used Special taddr ........................................................................ 4 When the TCALL instruction is used (SP - 6) (SP - 3) (SP - 4) ← PC 11-0 (SP - 5) ← 0, 0, 0, PC12 (SP - 2) ← ×, ×, MBE, RBE PC12-0 ← (taddr)4-0 + (taddr + 1) PC12-0 ← (taddr)4-0 + (taddr + 1) ........................................................................ 3 When an instruction other than the TBR and TCALL instructions is used Execution of (taddr)(taddr + 1) instruction SP ← SP - 6 ...................... Depends on the referenced instruction. Notes 1. The shaded portion is supported in Mk ΙΙ mode only. 2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions. 52 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 12. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Other than ports 4 and 5 Ports 4 and 5 Output voltage High-level output current VO IOH Each pin Total of all pins Low-level output current IOL Each pin Total of all pins Operating ambient temperature Storage temperature TA Tstg With a built-in pull-up resistor With open drain Conditions Rated value -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA °C °C Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values. CAPACITANCE (TA = 25 °C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz 0 V for pins other than pins to be measured Min. Typ. Max. 15 15 15 Unit pF pF pF 53 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C) Resonator Ceramic resonator Recommended constant Parameter Oscillator frequency (fX)Note 1 Conditions VDD = 2.2 to 5.5 V Min. 1.0 Typ. Max. Unit 6.0Note 2 MHz X1 X2 Oscillation settling time Note 3 After VDD reaches Min. of the oscillation voltage range VDD = 2.2 to 5.5 V 1.0 4 ms C1 C2 Crystal Oscillator frequency (fX )Note 1 6.0Note 2 MHz X1 X2 Oscillation settling timeNote 3 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V 10 30 1.0 6.0Note 4 ms ms MHz C1 C2 External clock X1 X2 X1 input frequency (fX )Note 1 VDD = 1.8 to 5.5 V X1 input high/low level width (tXH, tXL) VDD = 1.8 to 5.5 V 83.3 500 ns Notes 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. When the supply voltage is 2.2 V ≤ VDD < 2.7 V and the oscillator frequency is 4.7 MHz < fX ≤ 6.0 MHz, set the processor clock control register (PCC) to a value other than 0011. When the PCC is set to 0011, the time for one machine cycle cannot satisfy the defined setting of 0.85 µs. 3. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released. 4. When the supply voltage is 1.8 V ≤ V DD < 2.7 V and the X1 input frequency is 4.19 MHz < fx ≤ 6.0 MHz, set the PCC to a value other than 0011. When the PCC is set to 0011, the time for one machine cycle cannot satisfy the defined setting of 0.95 µs. Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. • It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. 54 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C) Resonator Crystal XT1 XT2 R C3 C4 Recommended constant Parameter Oscillator frequency (fXT )Note 1 Conditions VDD = 2.2 to 5.5 V Min. 32 Typ. 32.768 Max. 35 Unit kHz Oscillation settling timeNote 2 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V 1.0 2 10 s s kHz External clock XT1 XT2 XT1 input frequency (fXT)Note 1 VDD = 1.8 to 5.5 V 32 100 XT1 input high/low level width (tXTH, tXTL) VDD = 1.8 to 5.5 V 5 15 µs Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. 2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied. Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. • The wiring must be as short as possible. • Other signal lines must not run in these areas. • Any line carrying a high fluctuating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of VSS • It must not be grounded to ground patterns carrying a large current. • No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator. 55 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) RECOMMENDED PARAMETERS FOR THE OSCILLATION CIRCUIT When a ceramic resonator is used for the main system clock (TA = -40 to +85 °C) Manufacturer Product name Oscillation frequency (MHz) Oscillation circuit constant C1 (pF) Murata Mfg. CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.00MG CST4.00MGW CSA4.00MGU CST4.00MGWU CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MGU CST6.00MGWU CSA6.00MG CST6.00MGW Kyocera KBR-1000F/Y KBR-2.0MS PBRC 2.00A KBR-4.0MSA KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS PBRC6.00A PBRC6.00B TDK FCR2.0M3 FCR4.0M5 FCR4.19M5 FCR6.0M5 2.0 4.0 4.19 6.0 6.0 4.0 1.0 2.0 6.0 4.19 4.0 1.0 2.0 100 100 C2 (pF) 100 100 Oscillation voltage range Min. (V) 2.8 2.8 2.8 2.8 2.8 2.6 2.6 2.8 2.8 2.8 2.8 2.9 2.9 2.7 2.7 2.45 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.2 2.0 2.2 2.5 5.5 5.5 Max. (V) 5.5 Rd = 4.7 kΩ Remarks Incorporated Incorporated 30 30 Incorporated Incorporated 30 30 Incorporated Incorporated 30 30 Incorporated Incorporated 30 30 Incorporated Incorporated 30 30 Incorporated Incorporated 30 30 Incorporated Incorporated 220 82 82 33 220 82 82 33 Incorporated Incorporated 33 33 Incorporated Incorporated 33 33 Incorporated Incorporated 33 33 Incorporated Incorporated 33 15 15 15 33 15 15 15 Note When the CSB1000J (1.0 MHz) manufactured by Murata Mfg. is used, a limiting resistor (Rd = 4.7 kΩ) is necessary (see the following figure). When one of other resonators is used, no limiting resistor is required. 56 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg. is used X1 CSB1000J X2 Rd C1 C2 When a crystal is used for the subsystem clock (TA = -10 to +60 °C) Manufacturer Product name Oscillation frequency (kHz) Oscillation circuit constant C3 (pF) C4 (pF) R (kΩ) Daishinku DT-38 32.768 10 10 220 Oscillation voltage range Min. (V) 2.7 2.2 Max. (V) 5.5 5.5 Low-current-drain mode Low-voltage mode Remarks Caution The oscillation circuit constant and oscillation voltage range indicate the conditions to settle the oscillation, not to guarantee the accuracy of the oscillation frequency. When an accuracy oscillation frequency is needed for the implemented circuit, the oscillation frequency of the resonator should be adjusted on the circuit. Ask the manufacturer of the resonator you use. 57 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter Low-level output current High-level input voltage Symbol IOL Each pin Total of all pins VIH1 Ports 2, 3, and 8 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V VIH2 Ports 0, 1, 6, and 7 and RESET 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V VIH3 Ports 4 and With a Built-in pull-up 5 resistor 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0.7VDD 0.9VDD 0.7VDD 0.9VDD VDD - 0.1 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V VIL2 Ports 0, 1, 6, and 7 and RESET 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V VIL3 High-level output voltage Low-level output voltage VOH VOL1 X1, XT1 SCK, SO, and ports 0, 2, 3, and 6 to 8 IOH = -1.0 mA SCK, SO, and ports 2 to 8 SB0, SB1 VIN = VDD IOL = 15 mA, VDD = 4.5 to 5.5 V IOL = 1.6 mA N-ch open drain Pull-up resistor ≥ 1 kΩ 0 0 0 0 0 VDD - 0.5 0.2 2.0 0.4 0.2VDD 3 20 20 -3 -20 -3 Conditions Min. Typ. Max. 15 150 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V V V With N-ch open drain 2.7 V ≤ VDD ≤ 5.5 V 2.2 V ≤ VDD < 2.7 V VIH4 Low-level input voltage VIL1 X1, XT1 Ports 2 to 5, and 8 VOL2 High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 Other than X1 and XT1 X1, XT1 µA µA µA µA µA µA µA µA µA µA VIN = 13 V VIN = 0 V Ports 4 and 5 (With N-ch open drain) Other than X1, XT1, and ports 4 and 5 X1, XT1 Ports 4 and 5 (With N-ch open drain) At other than input instruction execution Ports 4 and 5 (With N-ch open drain) When the input instruction is executed -30 VDD = 5.0 V VDD = 3.0 V -10 -3 -27 -8 3 High-level output leakage current ILOH1 VOUT = VDD SCK, SO/SB0, SB1, and ports 2, 3, and 6 to 8 Ports 4 and 5 (With a built-in pull-up resistor) ILOH2 Low-level output leakage current Built-in pull-up resistor ILOL VOUT = 13 V Ports 4 and 5 (With N-ch open drain) VOUT = 0 V 20 -3 µA µA kΩ kΩ RL1 RL2 VIN = 0 V Ports 0 to 3 and 6 to 8 (except P00 pin) Ports 4 and 5 (mask option) 50 15 100 30 200 60 58 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter Power supply currentNote 1 Symbol IDD1 6.0 MHzNote 2 crystal Conditions VDD = 5.0 V ± 10%Note 3 VDD = 3.0 V ± 10%Note 4 V DD = 5.0 V ± 10% V DD = 3.0 V ± 10 % IDD1 4.19 MHzNote 2 crystal VDD = 5.0 V ± 10%Note 3 Min. Typ. 1.9 0.4 0.72 0.27 1.5 0.25 0.7 0.23 12 7 12 6 6 8.5 5 8.5 3.5 3.5 0.05 0.02 TA = 25 °C 0.02 Max. 6.0 1.3 2.1 0.8 4.0 0.75 2.0 0.7 35 21 24 18 12 25 15 17 12 7 10 5 3 Unit mA mA mA mA mA mA mA mA IDD2 C1 = C2 = HALT mode 22 pF VDD = 3.0 V ± 10%Note 4 V DD = 5.0 V ± 10% V DD = 3.0 V ± 10% IDD2 C1 = C2 = HALT mode 22 pF IDD3 32.768 kHzNote 5 crystal Low-voltage modeNote 6 V DD = 3.0 V ± 10% V DD = 2.5 V ± 10% V DD = 3.0 V, TA = 25 °C µA µA µA µA µA µA µA µA µA µA µA µA µA Low-currentdrain mode Note 7 IDD4 HALT mode V DD = 3.0 V ± 10% V DD = 3.0 V, TA = 25 °C Low-voltVDD = 3.0 V ± 10% age VDD = 2.5 V ± 10% modeNote 6 VDD = 3.0 V, T A = 25 °C Low-curVDD = 3.0 V ± 10% rent-drain Note 7 mode VDD = 3.0 V, T A = 25 °C IDD5 XT1 = 0 VNote 8 STOP mode VDD = 5.0 V ± 10% VDD = 3.0 V ± 10% Notes 1. This current excludes the current which flows through the built-in pull-up resistors. 2. This value applies also when the subsystem clock oscillates. 3. Value when the processor clock control register (PCC) is set to 0011 and the µPD750008 is operated in the high-speed mode. 4. Value when the PCC is set to 0000 and the µPD750008 is operated in the low-speed mode. 5. This value applies when the system clock control register (SCC) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. 6. Mode when the sub-oscillator control register (SOS) is set to 0000. 7. Mode when the SOS is set to 0010. 8. This value applies when the SOS is set to 00×1 and the sub-oscillator feedback resistor is not used (× = don’t care). 59 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter CPU clock cycle timeNote 1 (minimum instruction execution time = 1 machine cycle) Symbol tCY Operated by main system clock pulse Conditions When ceramic VDD = 2.7 to 5.5 V or crystal is used When external VDD = 2.7 to 5.5 V clock is used VDD = 1.8 to 5.5 V Min. 0.67 0.85 0.67 0.95 114 0 0 TI0 input high/low level width Interrupt input high/low level width tTIH, tTIL tINTH, tINTL VDD = 2.7 to 5.5 V 0.48 1.8 INT0 IM02 = 0 IM02 = 1 INT1, INT2, and INT4 KR0 to KR7 RESET low level width tRSL Note 2 Typ. Max. 64 64 64 64 Unit µs µs µs µs µs MHz kHz Operated by subsystem clock pulse TI0 input frequency fTI VDD = 2.7 to 5.5 V 122 125 1.0 275 µs µs µs µs µs µs µs 10 10 10 10 Notes 1. The cycle time of the CPU clock (Φ) (minimum instruction execution time) depends on the frequency of connected resonator (and external clock), the system clock control register (SCC), and the processor clock control register (PCC). The figure on the right side shows the ply voltage VDD during main system clock operation. 2. This value becomes 2tCY or 128/fX according to the setting of the interrupt mode register (IM0). Cycle time tCY [µs] 64 60 6 5 4 3 tCY vs. VDD (Main system clock in operation) cycle time tCY characteristics for the sup- Operation guaranteed range 2 1 0.95 0.85 0.67 0.5 0 1 1.8 2 3 2.2 2.7 4 5 5.5 6 Power supply voltage VDD [V] Remark The shaded portion is guaranteed only when the external clock is used. 60 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) SERIAL TRANSFER OPERATION Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V Min. 1300 3800 SCK high/low level width setup time (referred to SCK↑) SI Note 1 hold time (referred to SCK↑) Delay time from SCK↓ to SONote 1 output SI Note 1 tKL1, tKH1 tSIK1 VDD = 2.7 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 150 VDD = 2.7 to 5.5 V 150 500 tKSI1 VDD = 2.7 to 5.5 V 400 600 tKSO1 RL = 1 k Ω CL = 100 pFNote 2 VDD = 2.7 to 5.5 V 0 0 250 1000 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1. 2. RL is the resistance of the SO output line load, while CL is the capacitance. Two-wire and three-wire serial I/O modes (SCK: External clock input): (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V Min. 800 3200 SCK high/low level width SI Note 1 setup time (referred to SCK↑) SI Note 1 hold time (referred to SCK↑) Delay time from SCK↓ to SONote 1 output tKL2, tKH2 tSIK2 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 100 150 tKSI2 VDD = 2.7 to 5.5 V 400 600 tKSO2 RL = 1 k Ω CL = 100 pFNote 2 VDD = 2.7 to 5.5 V 0 0 300 1000 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1. 2. RL is the resistance of the SO output line load, while CL is the capacitance. 61 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) SBI mode (SCK: Internal clock output (master)): (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V Min. 1300 3800 SCK high/low level width SB0/SB1 setup time (referred to SCK↑) SB0/SB1 hold time (referred to SCK↑) Delay time from SCK↓ to SB0/SB1 output From SCK↑ to SB0/SB1↓ From SB0/SB1↓ to SCK↓ SB0/SB1 low level width SB0/SB1 high level width tKL3, tKH3 tSIK3 VDD = 2.7 to 5.5 V tKCY3/2 - 50 tKCY3/2 - 150 VDD = 2.7 to 5.5 V 150 500 tKSI3 tKCY3/2 Typ. Max. Unit ns ns ns ns ns ns ns tKSO3 RL = 1 k Ω CL = 100 pFNote VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance. SBI mode (SCK: External clock input (slave)): (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V Min. 800 3200 SCK high/low level width SB0/SB1 setup time (referred to SCK↑) SB0/SB1 hold time (referred to SCK↑) Delay time from SCK↓ to SB0/SB1 output From SCK↑ to SB0/SB1↓ From SB0/SB1↓ to SCK↓ SB0/SB1 low level width SB0/SB1 high level width tKL4, tKH4 tSIK4 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 100 150 tKSI4 tKCY4/2 Typ. Max. Unit ns ns ns ns ns ns ns tKSO4 RL = 1 k Ω CL = 100 pFNote VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns tKSB tSBK tSBL tSBH Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance. 62 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) AC timing measurement points (excluding X1 and XT1 inputs) VIH (Min.) VIL (Max.) VIH (Min.) VIL (Max.) VOH (Min.) VOL (Max.) VOH (Min.) VOL (Max.) Clock timing tXL 1/fX tXH VDD - 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V TI0 timing 1/fTI tTIL tTIH TI0 63 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Serial transfer timing Three-wire serial I/O mode: tKCY1 tKCY2 tKL1 tKL2 tKH1 tKH2 SCK tSIK1 tSIK2 tKSI1 tKSI2 SI tKSO1 tKSO2 Input data SO Output data Two-wire serial I/O mode: tKCY1 tKCY2 tKL1 tKL2 tKH1 tKH2 SCK tSIK1 tSIK2 tKSI1 tKSI2 SB0 and SB1 tKSO1 tKSO2 64 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Serial transfer timing Bus release signal transfer: tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4 tKSB tSBL tSBH tSBK SB0 and SB1 tKSO3 tKSO4 Command signal transfer: tKCY3 tKCY4 tKL3 tKL4 SCK tSIK3 tSIK4 tKSI3 tKSI4 tKH3 tKH4 tKSB tSBK SB0 and SB1 tKSO3 tKSO4 Interrupt input timing tINTL tINTH INT0, INT1, INT2, and INT4 KR0 - KR7 RESET input timing tRSL RESET 65 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (TA = -40 to +85 °C) Parameter Release signal setting time Oscillation settling timeNote 1 Symbol tSREL tWAIT Release by RESET Release by interrupt request Conditions Min. 0 Note 2 Note 3 Typ. Max. Unit µs ms ms Notes 1. CPU operation stop time for preventing unstable operation at the beginning of oscillation. 2. Select either 217/fX or 215/fX with the mask option. 3. This value depends on the settings of the basic interval timer mode register (BTM) shown below. BTM3 BTM2 BTM1 BTM0 Wait time At fX = 4.19 MHz 0 0 1 1 0 1 0 1 0 1 1 1 2 /fX (approx. 250 ms) 2 /fX (approx. 31.3 ms) 215/fX (approx. 7.81 ms) 213/fX (approx. 1.95 ms) 17 20 20 At fX = 6.0 MHz 2 /fX (approx. 175 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.37 ms) Data hold timing (STOP mode release by RESET) Internal reset operation HALT mode STOP mode Data hold mode Operation mode VDD tSREL STOP instruction execution RESET tWAIT Data hold timing (standby release signal: STOP mode release by interrupt signal) HALT mode STOP mode Data hold mode Operation mode VDD tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT 66 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 13. CHARACTERISTIC CURVE (REFERENCE VALUES) IDD vs. VDD (When the main system clock is operating at 6.0 MHz with a crystal) 10 (TA = 25 °C) 5.0 PCC = 0011 PCC = 0010 PCC = 0001 1.0 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply current IDD (mA) 0.1 Subsystem clock operating mode (SOS.1 = 0) 0.05 Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode (SOS.1 = 0) Subsystem clock operating mode (SOS.1 = 1) Subsystem clock HALT mode (SOS.1 = 1) 0.01 0.005 X1 X2 Crystal XT1 XT2 Crystal 32.768 kHz 330 kΩ 22 pF 22 pF 6.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 8 67 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) IDD vs. VDD (When the main system clock is operating at 4.19 MHz with a crystal) (TA = 25 °C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation 1.0 0.5 Supply current IDD (mA) 0.1 Subsystem clock operating mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation, and subsystem clock HALT mode (SOS.1 = 0) 0.05 Subsystem clock operating mode (SOS.1 = 1) Subsystem clock HALT mode (SOS.1 = 1) 0.01 0.005 X1 X2 Crystal XT1 XT2 Crystal 32.768 kHz 330 kΩ 22 pF 22 pF 4.19 MHz 22 pF 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 8 68 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) IOH vs. VDD - VOH (Ports 2, 3, 6, 7, and 8) (TA = 25 °C) 15 10 IOH [mA] VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V VDD = 2.2 V 5 VDD = 1.8 V 0 0 0.5 1.0 1.5 VDD - VOH [V] 2.0 2.5 3.0 IOL vs. VOL (Ports 2, 3, 6, 7, and 8) (TA = 25 °C) 40 30 VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V VDD = 2.2 V IOL [mA] 20 VDD = 1.8 V 10 0 0 0.5 1.0 VOL [V] 1.5 2.0 69 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 14. PACKAGE DRAWINGS Package drawings of mass-produced products (1/2) 44 PIN PLASTIC QFP ( 10) A B 33 34 23 22 detail of lead end C D S R Q 44 1 12 11 F J G H I M K P N NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition. M L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.2±0.2 10.0±0.2 10.0±0.2 13.2±0.2 1.0 1.0 0.37 +0.08 –0.07 0.16 0.8 (T.P.) 1.6±0.2 0.8±0.2 0.17 +0.06 –0.05 0.10 2.7 0.125±0.075 3 ° +7 ° –3 ° 3.0 MAX. INCHES 0.520 +0.008 –0.009 0.394 +0.008 –0.009 0.394 +0.008 –0.009 0.520 +0.008 –0.009 0.039 0.039 0.015 +0.003 –0.004 0.007 0.031 (T.P.) 0.063±0.008 0.031 +0.009 –0.008 0.007 +0.002 –0.003 0.004 0.106 0.005±0.003 3 ° +7 ° –3 ° 0.119 MAX. S44GB-80-3BS Caution The ES version is different from the corresponding mass-produced products in shape and material. See "ES package drawings." 70 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Package drawings of mass-produced products (2/2) 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 A 21 K L G J H I F C D N M B M R NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.50±0.10 0.9 MIN. 3.2±0.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 –0.05 0.17 0~15° INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 –0.005 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 –0.003 0.007 0~15° P42C-70-600A-1 Caution The shape and material of the ES version are the same as those of the corresponding massproduced products. 71 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) ES package drawing 44 PIN CERAMIC QFP FOR ES (REFERENCE) 11.43 8.0 44 1 34 33 11 12 22 23 11.43 8.0 0.15 0.8 0.32 (Bottom) Cautions 1. Find the location of pin 1 by checking the location of pin 17, which is connected to the metal cap. 2. The metal cap is connected to pin 17. The electrical level of the metal cap is VSS (GND). 3. The lead length has not been specified because leads are cut without any detailed specifications. 72 2.25 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) 15. RECOMMENDED SOLDERING CONDITIONS The µPD750004, µPD750006, and µPD750008 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document SMD Surface Mount Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Table 15-1 Surface Mounting Type Soldering Conditions µPD750004GB-×××-3BS-MTX µPD750006GB-×××-3BS-MTX µPD750008GB-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) : 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) : 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) µPD750004GB(A)-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) µPD750006GB(A)-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) µPD750008GB(A)-×××-3BS-MTX : 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) Soldering method Infrared reflow Soldering conditions Package peak temperature: 235 °C Duration: 30 seconds max. (at 210 °C or above) Maximum allowable number of reflow processes: 3 Package peak temperature: 215 °C Duration: 40 seconds max. (at 200 °C or above) Maximum allowable number of reflow processes: 3 Solder bath temperature: 260 °C max. Duration: 10 seconds max. Number of times: 1 Preliminary heat temperature: 120 °C max. (package surface temperature) Terminal temperature: 300 °C max. Duration: 3 seconds max. (per device side) Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating method - Caution Use of more than one soldering method should be avoided (except for partial heating method). Table 15-2 Insertion Type Soldering Conditions µPD750004CU-××× µPD750006CU-××× µPD750008CU-××× : 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) : 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) : 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) µPD750004CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) µPD750006CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) µPD750008CU(A)-××× : 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) Soldering method Wave soldering (terminal only) Partial heating method Soldering conditions Solder bath temperature: 260 °C max., Duration: 10 seconds max. Terminal temperature: 300 °C max., Duration: 3 seconds max. (for each pin) Caution Apply wave soldering to terminals only. See to it that the jet solder does not contact with the chip directly. 73 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 (1/2) Item Program memory µPD75008 Masked ROM 0000H - 1F7FH (8064 × 8 bits) 000H - 1FFH (512 × 4 bits) 75X standard CPU 4 bits × 8 or 8 bits × 4 • 0.95, 1.91, 15.3 µs (when operating at 4.19 MHz) µPD750008 Masked ROM 0000H - 1FFFH (8192 × 8 bits) µPD75P0016 One-time PROM 0000H - 3FFFH (16384 × 8 bits) Data memory CPU General-purpose register Instruction execution time When selecting the main system clock 75XL CPU (4 bits × 8 or 8 bit × 4) × 4 banks • 0.95, 1.91, 3.81, 15.3 µs (when operating at 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µs (when operating at 6.0 MHz) When selecting the subsystem clock SBS register 122 µs (when operating at 32.768 kHz) Not provided Provided SBS.3 = 1: Mk Ι mode selection SBS.3 = 0: Mk ΙΙ mode selection Stack Stack area Stack operation for a subroutine call instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr 000H - 0FFH 2-byte stack n00H - nFFH (n = 0, 1) Mk Ι mode: 2-byte stack Mk ΙΙ mode: 3-byte stack Mk Ι mode: Not available Mk ΙΙ mode: Available Available Not available Instruction 3 machine cycles Mk Ι mode: 3 machine cycles Mk ΙΙ mode: 4 machine cycles Mk Ι mode: 2 machine cycles Mk ΙΙ mode: 3 machine cycles 4 channels • Basic interval timer/watchdog timer: 1 channel • 8-bit timer/event counter: 1 channel • 8-bit timer counter: 1 channel • Clock timer: 1 channel • Φ, 524, 262, 65.5 kHz (when the main system clock operates at 4.19 MHz) • Φ, 750, 375, 93.8 kHz (when the main system clock operates at 6.0 MHz) • 2, 4, 32 kHz (when the main system clock operates at 4.19 MHz) • 2.93, 5.86, 46.9 kHz (when the main system clock operates at 6.0 MHz) CALLF !faddr 2 machine cycles Timer 3 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 1 channel • Clock timer: 1 channel • Φ, 524, 262, 65.5 kHz (when the main system clock operates at 4.19 MHz) • 2 kHz Clock output (PCL) BUZ output (BUZ) 74 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) (2/2) Item Serial interface µPD75008 µPD750008 µPD75P0016 3 modes are supported. • Three-wire serial I/O mode: First transferred bit switchable between the LSB and MSB • Two-wire serial I/O mode • SBI mode Can incorporate feedback resistors that are specified with the mask option. Not provided Incorporated SOS register Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1) Incorporated Register bank selection register (RBS) Standby release with INT0 Number of vectored interrupts Processor clock control register Not provided Provided Disable External: 3, internal: 3 Available when PCC is 0, 2, or 3 VDD = 2.7 to 6.0 V TA = -40 to +85 °C Enable External: 3, internal: 4 Available when PCC is 0 to 3 Power supply Operating ambient temperature Package VDD = 2.2 to 5.5 V • 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch) • 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch) 75 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD750008. In the 75XL series, use the common relocatable assembler together with a device file of each model. Language processors RA75X relocatable assembler Host machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2Note Distribution media 3.5-inch 2HD Part number µS5A13RA75X µS5A10RA75X µS7B13RA75X µS7B10RA75X 5.25-inch 2HD IBM PC/ATTM and See "OS for IBM PC." 3.5-inch 2HC compatibles 5.25-inch 2HC Device file Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note Distribution media 3.5-inch 2HD 5.25-inch 2HD Part number µS5A13DF750008 µS5A10DF750008 µS7B13DF750008 µS7B10DF750008 IBM PC/AT and compatibles See "OS for IBM PC." 3.5-inch 2HC 5.25-inch 2HC Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark The operations of the assembler and device file are guaranteed only on the above host machines and OSs. 76 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) PROM programming tools Hardware PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional program adapter. It allows the user to program a single chip microcontroller containing PROM from a standalone terminal or a host machine. The PG-1500 can be used to program typical 256K-bit to 4M-bit PROMs. The PA-75P008CU is a PROM programmer adapter provided for the µPD75P0016CU/GB. It is used in conjunction with the PG-1500. This program enables the host machine to control the PG-1500 through the serial and parallel interfaces. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note See "OS for IBM PC." Distribution media 3.5-inch 2HD Part number PA-75P008CU Software PG-1500 controller µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500 5.25-inch 2HD 3.5-inch 2HD 5.25-inch 2HC IBM PC/AT and compatibles Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. 77 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Debugging tools The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µPD750008. The system configuration is shown below. IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series. Use this emulator together with optional emulation board IE-75300-R-EM and emulation probe EP-75008CU-R or EP-75008G to develop application systems of the µPD750008 subseries. For efficient debugging, connect the emulator to the host machine and a PROM programmer. The IE-75000-R contains emulation board IE-75000-R-EM. The board is connected to the IE-75000-R. IE-75001-R The IE-75001-R is an in-circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series. Use this emulator together with optional emulation board IE-75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R to develop application systems of the µPD750008 subseries. For efficient debugging, connect the emulator to the host machine and a PROM programmer. IE-75300-R-EM The IE-75300-R-EM is an emulation board used to evaluate an application system using the µPD750008 subseries. Use this board together with the IE-75000-R or IE-75001-R. EP-75008CU-R The EP-75008CU-R is an emulation probe for the µPD750008CU. Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-REM. EP-75008GB-R The EP-75008GB-R is an emulation probe for the µPD750008GB. Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-REM. A 44-pin conversion socket, the EV-9200G-44, supplied with this probe facilitates the connection of the probe to the target system. This program enables the host machine to control the IE-75000-R or IE-75001-R through the RS-232-C and Centronics interface. Host machine Software OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note 2 Distribution media 3.5-inch 2HD Part number Hardware EV-9200G-44 IE control program µS5A13IE75X µS5A10IE75X µS7B13IE75X µS7B10IE75X 5.25-inch 2HD IBM PC/AT and compatibles See "OS for IBM PC." 3.5-inch 2HC 5.25-inch 2HC Notes 1. Maintenance service only 2. These software products cannot use the task swap function, which is available in MS DOS Ver. 5.00 or later. Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs. 2. The µPD750004, µ PD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008 subseries. 78 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) OS for IBM PC The following IBM PC OSs are supported. OS PC DOS TM Version Ver. 3.1 to Ver. 6.3 J6.1/V Note t o J6.3/VNote MS-DOS Ver. 5.0 to Ver. 6.22 5.0/V Note t o 6.2/VNote IBM DOS TM J5.02/V Note Note Only English version is supported. Caution These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.0 or later. 79 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) APPENDIX C RELATED DOCUMENTS Some documents are preliminary editions, but they are not so specified in the tables below. Documents related to devices Document name Document number Japanese English U10738E (This manual) µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Data Sheet µPD75P0016 Data Sheet µPD750008 User’s Manual µPD750008 Instruction List 75XL Series Selection Guide U10738J U10328J U10740J IEM-5593 U10453J U10328E U10740E U10453E Documents related to development tools Document name Document number Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-75008CU-R User's Manual EP-75008GB-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language EEU-846 U11354J EEU-699 EEU-698 U11940J EEU-731 EEU-730 EEU-704 EEU-5008 English EEU-1416 U11354E EEU-1317 EEU-1305 EEU-1335 EEU-1346 EEU-1363 EEU-1291 U10540E PC-9800 series (MS-DOS) base IBM PC series (PC DOS) base Other related documents Document name Document number Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices Reliability and Quality Control of NEC Semiconductor Devices Electrostatic Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Microcontroller-Related Products Guide - by third parties C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J MEI-1202 C10535E C11531E C10983E English Caution The above related documents are subject to change without notice. Be sure to use the latest edition when you design your system. 80 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 81 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 82 PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) [MEMO] 83 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS is a trademark of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5