UPD753304W

DATA SHEET MOS INTEGRATED CIRCUIT µPD753304 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753304 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. Since it inherits the 75X series CPU, it has upward compatibility. While the conventional 75X series products with an on-chip LCD controller/driver use an 80-pin package, the µPD753304 is sold as a pellet/wafer to make it possible to be built into portable devices with an LCD display function, etc. For detailed function descriptions, refer to the following user’s manual. µPD753304 User’s Manual: U12020E FEATURES • RC oscillation circuit on chip · Main system clock: fCC = 3.6 MHz (typical value with 6.8-kΩ external resistor connected. An internal 10-pF (typ.) capacitor is provided.) · Subsystem clock : fCT = 47 kHz (typ.) (Both a resistor and a capacitor are provided internally.) • Processing can be started immediately after standby mode is released. • Oscillation of the subsystem clock can be stopped in STOP mode. • Supply voltage: VDD = 2.5 to 5.5 V • On-chip memory · Program memory (ROM) : 4096 × 8 bits · Data memory (RAM) : 256 × 4 bits • Variable instruction execution time function useful for power saving · 1.1, 2.2, 4.4, 17.8 µs (in fCC = 3.6 MHz operation) · 85.1 µs (in fCT = 47 kHz operation) • Programmable LCD controller/driver on chip • Sold as a pellet/wafer to make it possible to be built into portable devices with an LCD display function APPLICATION Small LCD display device, etc. ORDERING INFORMATION Part Number µPD753304P-XXX µPD753304W-XXX Package Pellet Wafer Caution The µPD753304 is sold as a pellet/wafer. However, an ES product in 42-pin ceramic shrink DIP is also available. Remark XXX is a ROM code suffix. For the pellet/wafer, consult NEC because an agreement concerning quality must be made. The information in this document is subject to change without notice. Document No. U11874EJ1V0DS00 (1st edition) Date Published October 1997 N Printed in Japan The mark shows major revised points. © 1997 µPD753304 FUNCTIONAL OUTLINE Parameter Instruction execution time Function • 1.1, 2.2, 4.4, 17.8 µs (@ 3.6 MHz with main system clock) • 85.1 µs (@ 47 kHz with subsystem clock) 4096 × 8 bits 256 × 4 bits • 4-bit operation: 8 × 4 banks • 8-bit operation: 4 × 4 banks 12 On-chip pull-up resistors which can be specified by software: 4 Also used for segment pins: 4 On-chip memory ROM RAM General-purpose register Input/ output port CMOS input/output LCD controller/driver 20/24 segments (can be changed to CMOS input/output port in 4 time-unit; max. 4) • Display mode selection: Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) • LCD display modes can be selected by mask option • Segment selection: Timer 3 • • • channels 8-bit timer counter: 1 channel (with subclock source input function) Basic interval timer/watchdog timer: 1 channel Watch timer: 1 channel Clock output (PCL) Buzzer output (BUZ) • Φ, 3.6 MHz, 450 kHz, 225 kHz (@ 3.6 MHz with main system clock) • 2.94, 5.88, 47 kHz (@ 47 kHz with subsystem clock) • 1.76, 3.52, 28.13 kHz (@ 3.6 MHz with main system clock) External: 1, Internal: 2 Internal: 1 • Main system clock oscillation RC oscillation circuit (with external resistor and 10 pF (typ.) on-chip capacitor) • Subsystem clock oscillation RC oscillation circuit (with on-chip resistor and capacitor) STOP mode/HALT mode VDD = 2.5 to 5.5 V TA = –10 to +60 °C • Volume production product: Pellet/wafer • ES product (for evaluation): 42-pin ceramic shrink DIP (600 mil) Vectored interrupts Test input System clock oscillation circuit Standby function Supply voltage Operating ambient temperature Package 2 µPD753304 TABLE OF CONTENTS 1. PIN CONFIGURATION ............................................................................................................. 4 2. BLOCK DIAGRAM ................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTIONS ...................................................................................................................... 8 Port Pins .......................................................................................................................... 8 Non-Port Pins .................................................................................................................. 9 Pin Input/Output Circuits ............................................................................................. 10 Recommended Connections for Unused Pins ........................................................... 12 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ............................ 13 4.1 Difference between Mk I and Mk II Modes .................................................................. 13 4.2 Setting Method of Stack Bank Select Register (SBS) ............................................... 14 5. MEMORY CONFIGURATION ................................................................................................. 15 6. PERIPHERAL HARDWARE FUNCTION .............................................................................. 18 6.1 Digital I/O Port ............................................................................................................... 18 6.2 Clock Generator ............................................................................................................ 18 6.3 Clock Output Circuit ..................................................................................................... 20 6.4 Basic Interval Timer/Watchdog Timer ......................................................................... 21 6.5 Watch Timer .................................................................................................................. 22 6.6 Timer Counter ............................................................................................................... 23 6.7 LCD Controller/Driver ................................................................................................... 24 7. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................. 25 8. STANDBY FUNCTION ............................................................................................................ 26 9. RESET FUNCTION ................................................................................................................. 27 10. MASK OPTION ..................................................................................................................... 30 11. INSTRUCTION SET .............................................................................................................. 31 12. ELECTRICAL SPECIFICATIONS ........................................................................................ 41 13. CHARACTERISTIC CURVE (reference) ............................................................................ 48 APPENDIX A. µPD75308B, 753108 AND 753304 FUNCTIONAL LIST .............................. 49 APPENDIX B. DEVELOPMENT TOOLS .................................................................................. 51 APPENDIX C. RELATED DOCUMENTS .................................................................................. 53 3 µPD753304 1. PIN CONFIGURATION • Pin configuration of volume production product (Pad configuration) · Pellet µPD753304P-XXX Chip size Pad size : 3.36 × 2.86 mm 2 : 120 × 120 µm Pad intervals : 150 µm Y Axis 150 µ m 120 µ m 16 15 14 13 12 11 10 9 8 7 6 5 17 18 19 20 4 3 2 1 42 41 40 39 38 2.86 mm 120 µ m X Axis 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 3.36 mm 4 D753304 µPD753304 Pad Coordinates (unit: µm: pad center coordinates) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name CL2 CL1 V DD IC P80/S23 P81/S22 P82/S21 P83/S20 S19 S18 S17 S16 S15 514 S13 S12 S11 S10 S9 S8 S7 X Axis 1549 1549 1549 1549 1422.5 1169.5 916.5 663.5 410.5 157.5 –216.5 –469.5 –715.5 –961.5 –1207.5 –1453.5 –1549 –1549 –1549 –1549 –1549 Y Axis 311 540 769 998 1299 1299 1299 1299 1299 1299 1299 1299 1299 1299 1299 1299 992.5 746.5 500.5 254.5 –105.5 No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name S6 S5 S4 S3 S2 S1 S0 COM0 COM1 COM2 COM3 RESET P30/PCL P31/BUZ P32 P33 P100 P101 P102 P103/INT1 V SS X Axis –1549 –1549 –1549 –1549 –1301 –1055 –809 –563 –317 –71 289 518 747 976 1205 1434 1549 1549 1549 1549 1549 Y Axis –351.5 –597.5 –843.5 –1089.5 –1299 –1299 –1299 –1299 –1299 –1299 –1299 –1299 –1299 –1299 –1209 –1299 –997 –768 –539 –310 0.5 Caution Connect the rear side of the pellet to GND. 5 µPD753304 • Pin configuration of ES product (Top View) · 42-pin ceramic shrink DIP (600 mil) CL2 CL1 VDD IC P80/S23 P81/S22 P82/S21 P83/S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS P103/INT1 P102 P101 P100 P33 P32 P31/BUZ P30/PCL RESET COM3 COM2 COM1 COM0 S0 S1 S2 S3 S4 S5 S6 IC: Internally Connected (Connect directly to VDD.) Caution The µPD753304 is sold as pellet/wafer. The above pin configuration applies to an ES product. Pin Name BUZ CL1, CL2 COM0-COM3 IC INT1 P30-P33 P80-P83 : : : : : : : Buzzer Clock RC Oscillator Common Output0-3 Internally Connected External Vectored Interrupt1 Port3 Port8 P100-P103 PCL RESET S0-S23 VDD VSS : : : : : : Port10 Programmable Clock Reset Segment Output0-23 Positive Power Supply Ground 6 µPD753304 2. BLOCK DIAGRAM WATCH TIMER INTW fLCD PROGRAM COUNTER (12) CY ALU SP(8) BUZ/P31 BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT 8-BIT TIMER COUNTER #0 INTT0 INT1 BANK 4 4 PORT3 PORT8 PORT10 4 4 4 P30 to P33 P80 to P83 P100 to P103 GENERAL REG. 4 ROM PROGRAM MEMORY 4096 × 8 BITS DECODE AND CONTROL RAM DATA MEMORY 256 × 4 BITS INT1/P103 INTERRUPT CONTROL LCD CONTROLLER/ DRIVER 20 4 4 S0 to S19 S20/P83 to S23/P80 COM0 to COM3 fCC/2 N CPU CLOCK Φ fLCD CLOCK CLOCK SYSTEM CLOCK STAND BY OUTPUT DIVIDER GENERATOR CONTROL CONTROL MAIN SUB PCL/P30 CL1 CL2 IC VDD VSS RESET 7 µPD753304 3. PIN FUNCTIONS 3.1 Port Pins Pin Name P30 P31 P32 P33 P80 P81 P82 P83 P100 P101 P102 P103 Input/output Input/output S23 S22 S21 S20 — — — INT1 Programmable 4-bit input/output port (PORT10) Input/output specifiable bit-wise Connection of on-chip pull-up resistor specifiable in 4-bit units by software X Input with pull-up resistor E-B Input/output Input/output DualFunction Pin PCL BUZ — — Function Programmable 4-bit input/output port (PORT3) Input/output specifiable bit-wise Input/output mode after reset specifiable (mask option) Note 2 4-bit input/output port (PORT8) 8-Bit I/O X After Reset Input Note 2 I/O Circuit Type Note 1 E X Input H F -A Notes 1. 2. denotes Schmitt trigger input. Input/output mode after reset can be specified by mask option. For details, refer to Table 3-1. Table 3-1. State after Reset by Mask Option of Port 3 State after Reset Pin Names Mask Option P30/PCL P31/BUZ P32 P33 High-level output Input Mask Option Low-level output Mask Option Low-level output 8 µPD753304 3.2 Non-Port Pins Pin Name PCL BUZ Input/output Output DualFunction Pin P30 P31 Clock output Arbitrary frequency output (for buzzers or system clock trimming) Edge detected vectored interrupt input (detected edge is selectable) Asynchronous Input with pull-up resistor Highimpedance Input Highimpedance — F -A Function After Reset Input Note 2 I/O Circuit Type Note 1 E INT1 Input P103 S0-S19 Output — Segment signal output G-B S20-S23 COM0-COM3 Output Output P83-P80 — Segment signal output Common signal output H G-B CL1 CL2 RESET — — Input — Main system clock oscillation resistor (R) connection pin. No external clock can be input. System reset input (low level active). On-chip pull-up resistor specifiable (mask option) Internally connected. Connect directly to VDD. Positive power supply Ground potential — — — B -A IC V DD V SS — — — — — — — — — — — — Notes 1. 2. denotes Schmitt trigger input. Input/output mode after reset can be specified by mask option. For details, refer to Table 3-1. 9 µPD753304 3.3 Pin Input/Output Circuits The µPD753304 pin input/output circuits are shown schematically. (1/2) TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT CMOS specification input buffer. TYPE B Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E IN data Type D output disable IN/OUT Type A Schmitt triggered input with hysteresis characteristic. TYPE B-A TYPE E-B VDD P.U.R. VDD P.U.R. (Mask option) data Type D output disable IN Type A P.U.R. enable P-ch IN/OUT P.U.R. : Pull-Up Resistor Schmitt triggered input with hysteresis characteristic. P.U.R. : Pull-Up Resistor (At RESET active: Enable) 10 µPD753304 (2/2) TYPE F-A VDD P.U.R. P.U.R. enable data output disable Type D data output disable Type B TYPE E P-ch SEG data IN/OUT TYPE G-A TYPE H IN/OUT P.U.R. : Pull-Up Resistor TYPE G-A VLC0 VLC1 P-ch N-ch OUT SEG data VLC2 N-ch N-ch TYPE G-B VLC0 VLC1 P-ch N-ch OUT COM data N-ch VLC2 N-ch P-ch 11 µPD753304 3.4 Recommended Connections for Unused Pins Table 3-2. List of Recommended Connections for Unused Pins Pin P30/PCL P31/BUZ P32 P33 P100 P101 P102 P103/INT1 S0-S19 COM0-COM3 S20/P83-S23/P80 Input state: Connect independently to VSS or VDD via resistor Output state: Leave open Connect directly to V DD Leave open Recommended Connection Input state: Connect independently to VSS or VDD via resistor Output state: Leave open IC 12 µPD753304 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The CPU of the µPD753304 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the Stack Bank Select register (SBS). • Mk I mode: Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 2 bytes 3 bytes Mk II mode • Mk II mode: Can be used in all the 75XL CPU’s including those products whose ROM capacity is more than Not available Available 3 machine cycles 2 machine cycles 4 machine cycles 3 machine cycles Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This mode enhances the software compatibility with products which have more than 16K bytes. When Mk II mode is selected, the number of stack bytes (usable area) in the execution of a subroutine call instruction increases by 1 per stack compared to Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode. 13 µPD753304 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS SBS2 SBS1 Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be assigned to the bit 2 position. Mode switching specification 0 1 Mk II mode Mk I mode Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode. 14 µPD753304 5. MEMORY CONFIGURATION • Program Memory (ROM) .... 4096 × 8 bits • Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an any address. • Addresses 0002H to 000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can be started at an any address. • Addresses 0020H to 007FH Table area referenced by the GETI instruction Note . Note The GETI instruction realizes a 1-byte instruction on behalf of an any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. • Data Memory (RAM) • Data area ... 256 words × 4 bits (000H to 0FFH) • Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH) 15 µPD753304 Figure 5-1. Program Memory Map Address 7 6 5 0 4 0 Internal reset start address Internal reset start address 0 0 2 H MBE RBE 0 0 INTBT INTBT 0 0 6 H MBE RBE 0 0 INT1 INT1 0 0 A H MBE RBE 0 0 INTT0 INTT0 start address start address start address start address start address start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1 Note or CALLA !addr1 Note instruction 0 0 0 H MBE RBE CALL !addr instruction subroutine entry address BR $addr instruction relative branch address 020H GETI instruction reference table 07FH 080H –15 to –1, +2 to +16 Branch address of BRCB !caddr instruction Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 16 µPD753304 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H Data area static RAM (256 x 4) Stack area 0FFH 100H Not incorporated 256 x 4 1 1DFH 1E0H (24 x 4) 1F7H 1F8H 1FFH Not incorporated 0 256 x 4 (224 x 4) Memory bank (32 x 4) Display data memoryNote Not incorporated F80H Peripheral hardware area 128 x 4 15 FFFH Note Write only. 17 µPD753304 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port There are three kinds of I/O port. • CMOS input/output ports (PORT 3, 8, 10): 12 Table 6-1. Types and Features of Digital Ports Port PORT3 Function 4-bit I/O Operation & features Can be set to input mode or output mode in 1-bit unit. Remarks Also used for the PCL and BUZ pins. Also used for the S20 to S23 pins. Also used for the INT1 pin. PORT8 Can be set to input mode or output mode in 4-bit units. PORT10 Can be set to input mode or output mode in 1-bit unit. 6.2 Clock Generator The clock generator is a device that generates the clock fed to peripheral hardware on the CPU and is configured as shown in Figure 6-1. The clock generator operates according to how the processor clock control register (PCC) and system clock control register (SCC) are set. There are two kinds of clocks, main system clock and subsystem clock. The instruction execution time can also be changed. • 1.1, 2.2, 4.4, 17.8 µs (main system clock: in 3.6-MHz operation) • 85.1 µs (subsystem clock: in 47-kHz operation) 18 µPD753304 Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer counter · Watch timer · LCD controller/driver · Clock output circuit CL1 Main system clock oscillator (with RC CL2 oscillation and capacitor) fCC 1/1 to 1/4096 Divider 1/2 1/4 1/16 Subsystem clock oscillator (with RC oscillation, resistor and capacitor) fCT · Timer counter · LCD controller/driver · Watch timer WM.3 SOS SOS3 SCC SCC3 Oscillation stop Oscillation stop Selector Divider Selector 1/4 Φ · CPU · Clock output circuit Internal bus SCC0 PCC PCC0 PCC1 4 PCC2 HALT Note STOP Note PCC3 HALT F/F S R Q PCC2, PCC3 Clear STOP F/F Q S Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fCC = Main system clock frequency fXT = Subsystem clock frequency Φ = CPU clock PCC: Processor Clock Control Register SCC: System Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. 19 µPD753304 6.3 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the PCL/P30 pin to the remote control waveform outputs and peripheral LSI’s. • Clock Output (PCL): Φ, 3.6 MHz, 450 kHz, 225 kHz (in 3.6-MHz operation) Figure 6-2. Clock Output Circuit Block Diagram From clock generator Φ fCC Selector fCC/23 fCC/24 PCL/P30 Output buffer PORT3.0 CLOM3 0 CLOM1 CLOM0 CLOM P30 output latch Bit 0 of PMGA Port 3 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 20 µPD753304 6.4 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. • Interval timer operation to generate a reference time interrupt • Watchdog timer operation to detect an inadvertent program loop and reset the CPU • Reads the contents of counting Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator fCC/25 fCC/27 MPX fCC/29 fCC/212 3 BT Clear Clear Basic interval timer (8-bit frequency divider) Set BT interrupt request flag Vectored interrupt IRQBT request signal Wait release signal when standby is released. Internal reset signal WDTM SET1 Note 1 BTM3 BTM2 BTM1 BTM0 BTM SET1 Note 4 8 Internal bus Note Instruction execution 21 µPD753304 6.5 Watch Timer The µPD753304 has one watch timer channel which has the following functions. • Sets the test flag (IRQW) at fW/2 14 intervals. The standby mode can be released by the IRQW. • Convenient for program debugging and checking as interval becomes 128 times longer (fW/27) with the fast feed mode. • Outputs the frequencies (fW, fW/23, fW/2 4) to the BUZ/P31 pin, usable for buzzer and trimming of system clock frequencies. • Clears the frequency divider to make the watch start with zero seconds. Figure 6-4. Watch Timer Block Diagram fW 26 fW 27 fCC 128 From clock generator Selector fCT fW 4 kHz 2 kHz fW fW 23 24 Divider fLCD fW 214 Selector INTW IRQW set signal Clear Selector Output buffer BUZ/P31 WM Note PORT3.1 0 WM5 WM4 WM3 WM2 WM1 WM0 P31 output-latch PMGA bit 1 Port 3 input/ output mode WM7 8 Internal bus Note Set WM2 to 1 when using the LCD controller/driver. 22 µPD753304 6.6 Timer Counter The µPD753304 has one channel of timer counter. Its configuration is shown in Figure 6-5. The timer counter has the following functions. • Programmable interval timer operation • Read the count value. Figure 6-5. Timer Counter Block Diagram Internal bus 8 0 SET1 Note 8 TM0 0 0 8 TMOD0 Modulo register (8) TM06 TM05 TM04 TM03 TM02 8 Comparator (8) 8 T0 From clock generator fCC/2 fCC/26 fCC/28 fCC/210 fCT 4 Match MPX Count register (8) CP Clear INTT0 IRQT0 set signal Timer operation start RESET IRQT0 clear signal Note Instruction execution Caution When setting data to the TM0, be sure to set bits 0, 1, 7 to 0. 23 µPD753304 6.7 LCD Controller/Driver The µPD753304 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The µPD753304 LCD controller/driver has the following functions: • Display data memory is read automatically by DMA operation and segment and common signals are generated. • Display mode can be selected from among the following five: Static 1/2 duty (time multiplexing by 2), 1/2 bias 1/3 duty (time multiplexing by 3), 1/2 bias 1/3 duty (time multiplexing by 3), 1/3 bias 1/4 duty (time multiplexing by 4), 1/3 bias • A frame frequency can be selected from among four in each display mode. • A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to COM3). • The segment signal output pins (S20 to S23) can be changed to the I/O ports (PORT8). • LCD display modes can be selected (mask option). • It can also operate by using the subsystem clock. Figure 6-6. LCD Controller/Driver Block Diagram Internal bus 4 4 Port 8 output latch 3210 8 Port mode register group C 0 4 LCD/port selection register 1F7H 3210 4 1F4H 1F3H 3210 3210 1E0H 3210 8 Display mode register 4 Display control register Decoder 3210 3210 3210 3210 Timing fLCD controller Port 8 Input/Output buffer 0 1 2 3 Segment driver Segment driver Common driver LCD drive voltage control S23/P80 S20/P83 S19 S0 COM3 COM2 COM1 COM0 24 µPD753304 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD753304 has three different interrupt sources and one types of test source. The interrupt control circuit of the µPD753304 has the following functions. (1) Interrupt function • Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). • Can set any interrupt start address. • Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). • Test function of interrupt request flag (IRQxxx). An interrupt generation can be checked by software. • Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag. (2) Test function • Test request flag (IRQxxx) generation can be checked by software. • Release the standby mode. The test source to be released can be selected by the test enable flag. Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 1 IM1 Interruput enable flag (IExxx) IME IPS IST1 IST0 Decoder VRQn INTBT INT1/P103 Edge detector INTT0 INTW IRQBT IRQ1 IRQT0 IRQW Priority control circuit Vector table address generator Standby release signal 25 µPD753304 8. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD753304. Table 8-1. Operation Status in Standby Mode Item Set instruction System clock for setting Operating status Clock generator Mode STOP mode STOP instruction HALT mode HALT instruction Can be set by either main system clock or subsystem clock. Only CPU clock Φ is stopped (oscillation Oscillation of main system clock is continues.) stopped. Setting the sub oscillation circuit stop enable flag (SOS.3) to 1 also stops oscillation of the subsystem clock. Operation stopped Operates only when main system clock is oscillating BT mode : Sets IRQBT at reference time intervals WT mode : Generates reset signal when BT overflows Operation impossible only when a divided main system clock is selected as count clock when the main system clock is stopped. Operation possible Basic interval timer/ watchdog timer Timer counter Operation possible only when SOS.3 is set to 0 and f CT is selected as count clock. LCD control/driver Operation possible only when SOS.3 is set to 0 and f CT is selected as LCDCL. Operation possible only when SOS.3 is set to 0 and f CT is selected as count clock. Watch timer Operation possible External interrupt CPU Release signal Operation possible only when SOS.3 is set to 0. Operation stopped Generation of an interrupt request signal from hardware whose operation is enabled by an interrupt enable flag or RESET signal. 26 µPD753304 9. RESET FUNCTION There are two reset inputs: external RESET signal and reset signal sent from the basic interval timer/watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus Generation of the RESET signal initializes each device as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode Note 56/fCC (15.6 µs: @ 3.6-MHz operation) 27 µPD753304 Table 9-1. Status of Each Device After Reset (1/2) RESET signal generation in the standby mode Sets the low-order 4 bits of program memory’s address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Held 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 RESET signal generation in operation Sets the low-order 4 bits of program memory’s address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory’s address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) 28 µPD753304 Table 9-1. Status of Each Device After Reset (2/2) RESET signal generation in the standby mode 0 0 0 0 0 0 0 0 Reset (0) 0 0 0 On Off Cleared (0) RESET signal generation in operation 0 0 0 0 0 0 0 0 Reset (0) 0 0 0 On Off Cleared (0) Hardware Watch timer Clock generator, clock output circuit Mode register (WM) Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Subsystem clock oscillator control register (SOS) LCD controller/ driver Display mode register (LCDM) Display control register (LCDC) LCD/port selection register (LPS) Interrupt function Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt priority select register (IPS) INT1 mode registers (IM1) Digital port Output buffer (P30-P33) Output buffer (P80-P83, P100-P103) Output latch (P30-P32, P80-P83, P100-P103) Output latch (P33) I/O mode registers (PMGA) I/O mode registers (PMGC, D) Pull-up resistor setting register (POGB) Set (1) 0FH 00H 01H Set (1) 0FH 00H 01H 29 µPD753304 10. MASK OPTION The µPD753304 has the following mask options. • RESET pin mask option An on-chip pull-up resistor can be selected. Specifies an on-chip pull-up resistor. Specifies no on-chip pull-up resistor. • LCD display mode mask option LCD display modes can be selected. Static display mode (BIAS-V LC0 shorted, VLC0 – VLC1 opened) 1/2 bias mode (BIAS-VLC0 shorted, VLC1 – VLC2 shorted) 1/3 bias mode (BIAS-VLC0 shorted) • Standby function mask option Wait time can be selected after STOP mode is released. 512/fCC (142 µs: in 3.6 MHz operation) No waits • Port 3 mask option Input/output mode after reset can be specified Status after Reset Pin Names Mask Option P30/PCL P31/BUZ P32 P33 High-level output Input Mask Option Low-level output Mask Option Low-level output 30 µPD753304 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is written in the operand column of each instruction in accordance with the method of use of the instruction operand identifier. For details, refer to “RA75X ASSEMBLER PACKAGE USER’S MANUAL—LANGUAGE (U12385E) ”. If there are several elements, one of them is selected. Capital letters and the + and – symbols are key words and are written as they are. For immediate data, appropriate numbers and labels are written. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be written. However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to User’s Manual (U12020E). Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr, addr1 caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, BC, XA, BC, BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Format HL, HL+, HL–, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label Note FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-0FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit 0 = 0) or label PORT3, PORT8, PORT10 IEBT, IET0, IE1, IEW RB0-RB3 MB0, MB1, MB15 Note mem can be only used for even address in 8-bit data processing. 31 µPD753304 (2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA’ BC’ DE’ HL’ PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA’ expanded register pair : BC’ expanded register pair : DE’ expanded register pair : HL’ expanded register pair : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 3, 8, 10) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data 32 µPD753304 (3) Explanation of symbols under addressing area column *1 MB = MBE·MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 000H to FFFH addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *2 *3 Data memory addressing *4 *5 *6 *7 addr1 = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 *8 *9 *10 *11 caddr = 000H to FFFH faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 000H to FFFH Program memory addressing Remarks 1. 2. 3. 4. MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed. 33 µPD753304 (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. • When no skip is made: S = 0 • When the skipped instruction is a 1- or 2-byte instruction: S = 1 • When the skipped instruction is a 3-byte instruction Note: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 34 µPD753304 Instruction group Transfer instruction Mnemonic Operand Number of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 Machine cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A ← n4 reg1 ← n4 XA ← n8 HL ← n8 rp2 ← n8 A ← (HL) Operation Addressing area Skip condition MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA String effect A String effect A String effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH A ← (HL), then L ← L+1 A ← (HL), then L ← L–1 A ← (rpa1) XA ← (HL) (HL) ← A (HL) ← XA A ← (mem) XA ← (mem) (mem) ← A (mem) ← XA A ← reg XA ← rp' reg1 ← A rp'1 ← XA A ↔ (HL) A ↔ (HL), then L ← L+1 A ↔ (HL), then L ← L–1 A ↔ (rpa1) XA ↔ (HL) A ↔ (mem) XA ↔ (mem) A ↔ reg1 XA ↔ rp' XA ← (PC11–8+DE)ROM XA ← (PC11–8+XA)ROM XA ← (BCDE)ROM Note XA ← (BCXA)ROM Note XCH A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH Table reference MOVT XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA *6 *6 Note Be sure to assign “0” to register B. 35 µPD753304 Instruction group Bit transfer Mnemonic Operand Number of bytes 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 Machine cycles 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S CY ← (fmem.bit) Operation Addressing area *4 *5 *1 *4 *5 *1 Skip condition MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY CY ← (pmem7–2+L3–2.bit(L1–0)) CY ← (H+mem3–0.bit) (fmem.bit) ← CY (pmem7–2+L3–2.bit(L1–0)) ← CY (H+mem3–0.bit) ← CY A ← A+n4 XA ← XA+n8 A ← A+(HL) XA ← XA+rp' rp'1 ← rp'1+XA A, CY ← A+(HL)+CY XA, CY ← XA+rp'+CY rp'1, CY ← rp'1+XA+CY A ← A–(HL) XA ← XA–rp' rp'1 ← rp'1–XA A, CY ← A–(HL)–CY XA, CY ← XA–rp'–CY rp'1, CY ← rp'1–XA–CY A←A A←A Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA carry carry *1 carry carry carry *1 ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA *1 borrow borrow borrow SUBC A, @HL XA, rp' rp'1, XA *1 AND A, #n4 A, @HL XA, rp' rp'1, XA > > n4 (HL) *1 XA ← XA > rp' XA rp'1 ← rp'1 OR A, #n4 A, @HL XA, rp' rp'1, XA A ← A ∨ n4 A ← A ∨ (HL) XA ← XA ∨ rp' rp'1 ← rp'1 ∨ XA A ← A v n4 A ← A v (HL) XA ← XA v rp' rp'1 ← rp'1 v XA CY ← A0, A3 ← CY, An–1 ← An A←A reg ← reg+1 rp1 ← rp1+1 (HL) ← (HL)+1 (mem) ← (mem)+1 reg ← reg–1 rp' ← rp'–1 *1 *3 reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH *1 *1 XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation instructions Increment and Decrement instructions RORC NOT INCS A A reg rp1 @HL mem DECS reg rp' 36 > µPD753304 Instruction group Comparison instruction Mnemonic Operand Number of bytes 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Machine cycles 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY ← 1 CY ← 0 Skip if CY = 1 CY ← CY (mem.bit) ← 1 (fmem.bit) ←1 Operation Addressing area Skip condition SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' Carry flag manipulation instruction SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit CY = 1 Memory bit manipulation instructions SET1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (pmem7–2+L3–2.bit(L1–0)) ←1 (H+mem3–0.bit) ←1 (mem.bit) ←0 (fmem.bit) ←0 (pmem7–2+L3–2.bit(L1–0)) ←0 (H+mem3–0.bit) ←0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 Skip if (H+mem3–0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7–2+L3–2.bit(L1–0)) = 0 Skip if (H+mem3–0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7–2+L3–2.bit(L1–0)) = 1 and clear Skip if (H+mem3–0.bit) = 1 and clear CY ← CY CY ← CY CY ← CY CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit > > (fmem.bit) (pmem7–2+L3–2.bit(L1–0)) (H+mem3–0.bit) OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit CY ← CY ∨ (fmem.bit) CY ← CY ∨ (pmem7–2+L3–2.bit(L1–0)) CY ← CY ∨ (H+mem3–0.bit) CY ← CY v (fmem.bit) CY ← CY v (pmem7–2+L3–2.bit(L1–0)) CY ← CY v (H+mem3–0.bit) XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit > 37 µPD753304 Instruction group Branch instructions Mnemonic BR Note 1 Operand Number of bytes – Machine cycles – Operation PC11–0 ← addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. PC11-0 ← addr1 Select appropriate instruction from among BR !addr BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. PC11–0 ← addr PC11–0 ← addr Addressing area *6 Skip condition addr addr1 – – *11 !addr $addr 3 1 3 2 *6 *7 BR $addr1 1 2 PC11–0 ← addr1 PC11–0 ← PC11-8+DE PC11–0 ← PC11-8+XA PC11–0 ← BCDE Note 2 PC11–0 ← BCXA Note 2 PC11–0 ← addr1 PC11–0 ← caddr11–0 (SP–2) ← x, x, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr1, SP ← SP–6 (SP–3) ←MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← addr, SP ← SP–4 (SP–2) ←x, x, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← addr, SP ← SP–6 (SP–3) ← MBE, RBE, 0, 0 (SP–4) (SP–1) (SP–2) ← PC11–0 PC11–0 ← 0+faddr, SP ← SP–4 (SP–2) ← x, x, MBE, RBE (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 PC11–0 ← 0+faddr, SP ← SP–6 *7 PCDE PCXA BCDE BCXA 2 2 2 2 3 3 3 3 *6 *6 BRA Note 1 !addr1 3 3 *11 BRCB !caddr 2 2 *8 Subroutine stack control instructions CALLA Note 1 !addr1 3 3 *11 CALL Note 1 !addr 3 3 *6 4 CALLF Note 1 !faddr 2 2 *9 3 Notes 1. 2. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. “0” must be assigned to B register. 38 µPD753304 Instruction group Subroutine stack control instructions Mnemonic RET Note 1 Operand Number of bytes 1 Machine cycles 3 Operation PC11–0 ← (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4 x, x, MBE, RBE ← (SP+4) 0, 0, 0, 0, ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6 MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) SP ← SP+4 then skip unconditionally 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) x, x, MBE, RBE ← (SP+4) SP ← SP+6 then skip unconditionally MBE, RBE, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 0, 0, 0, 0 ← (SP+1) PC11–0 ← (SP) (SP+3) (SP+2) PSW ← (SP+4) (SP+5), SP ← SP+6 (SP–1)(SP–2) ← rp, SP ← SP–2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 rp ← (SP+1) (SP), SP ← SP+2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 IME (IPS.3) ← 1 IExxx ← 1 IME (IPS.3) ← 0 IExxx ← 0 A ← PORTn PORTn ← A Set HALT Mode (PCC.2 ← 1) Set STOP Mode (PCC.3 ← 1) No Operation RBS ← n MBS ← n (n = 0-3) (n = 0, 15) (n = 3, 8, 10) (n = 3, 8, 10) Addressing area Skip condition RETS Note 1 1 3+S Unconditional RETI Note 1 1 3 PUSH rp BS 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 2 2 POP rp BS Interrupt control instructions EI IExxx DI IExxx 2 2 2 2 2 2 2 1 Input/output instructions IN Note 2 OUT Note 2 A, PORTn PORTn, A CPU control instructions HALT STOP NOP Special instructions SEL RBn MBn 2 2 Notes 1. 2. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 39 µPD753304 Instruction group Special instructions Number of bytes 1 Machine cycles 3 Addressing area *10 ––––––––––––– Mnemonic GET Note 1, 2 Operand Operation Skip condition taddr • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) –––––––––––––––––––––––––––––––––– • When TCALL instruction (SP–4) (SP–1) (SP–2) ← PC11–0 (SP–3) ← MBE, RBE, 0, 0 PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–4 –––––––––––––––––––––––––––––––––– ––––––––––––– • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction 3 • When TBR instruction PC11–0 ← (taddr) 3–0 + (taddr+1) • When TCALL instruction (SP–6) (SP–3) (SP–4) ← PC11–0 (SP–5) ← 0, 0, 0, 0 (SP–2) ← x, x, MBE, RBE PC11–0 ← (taddr) 3–0 + (taddr+1) SP ← SP–6 *10 ––––––––––––– ––––––––––––––––––––––––––––––––––––– –––– 4 ––––––––––––––––––––––––––––––––––––– –––– ––––––––––––– 3 • When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. 2. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 40 µPD753304 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Supply voltage Input voltage Output voltage High-level output current Symbol VDD VI VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Ambient operating temperature Storage temperature TA Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –10 –30 30 220 –10 to +60 Unit V V V mA mA mA mA °C °C Tstg –65 to +150 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Capacitance (TA = 25 °C, V DD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than tested pins: 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 41 µPD753304 Main System Clock Oscillation Circuit Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Oscillator RC oscillation Recommended Constants Parameter Oscillation frequency (fCC) Note Conditions VDD = 4.5 to 5.5 V MIN. 1.0 TYP. MAX. 6.0 Unit MHz CL1 CL2 VDD = 2.5 to 4.5 V 1.0 5.0 MHz Note The oscillation frequency indicates characteristics of the oscillation circuit only. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics. Caution When using the main system clock frequency circuit, wire the portion enclosed by the dotted line in the above figure as follows to prevent adverse influence from wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. • Do not route the wiring in the vicinity of line through which a high alternating current flows. • Do not extract any signal from the oscillation circuit. Subsystem Clock Oscillation Circuit Characteristics (TA = –10 to +60 °C, V DD = 2.5 to 5.5 V) Oscillation RC oscillation Note 1 Parameter Oscillation frequency (fCT) Note 2 Conditions VDD = 5.0 V ± 10 % VDD = 3.0 V ± 10 % MIN. 27 27 TYP. 47 47 MAX. 74 74 Unit kHz kHz Notes 1. 2. The subsystem clock oscillation circuit incorporates a resistor (R) and a capacitor (C), and does not have external pins. The oscillation frequency indicates characteristics of the oscillation circuit only. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics. 42 µPD753304 DC Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Parameter Low-level output current Symbol IOL Par pin Total of all pins High-level input voltage VIH1 VIH2 Low-level input voltage VIL1 VIL2 High-level output voltage VOH1 VOH2 Low-level output voltage VOL1 VOL2 High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Internal pull-up resistor ILIH1 ILIH2 ILIL1 ILIL2 ILOH VOUT = VDD VIN = 0 V Ports 3, 8, P100-P102 P103, RESET Ports 3, 8, P100-P102 P103, RESET P31-P33, Ports 8, 10 P30 (HCLK) P31-P33, Ports 8, 10 P30 (HCLK) VIN = VDD Pins other than CL1 CL1 Pins other than CL1 CL1 IOL = 1.6 mA IOH = –1.0 mA 0.7VDD 0.8VDD 0 0 VDD – 0.5 VDD – 0.12 0.4 0.19 3 20 –3 –20 3 Conditions MIN. TYP. MAX. 15 150 VDD VDD 0.3VDD 0.2VDD Unit mA mA V V V V V V V V µA µA µA µA µA µA kΩ kΩ V kΩ V ILOL VOUT = 0 V –3 RL1 RL2 Port 10 RESET (Mask option) 50 30 2.5 50 100 60 200 120 5.5 LCD drive voltage LCD divider resistor LCD output voltage deviation Note 1 (common) LCD output voltage deviation Note 1 (segment) VLCD RLCD VODC Note 2 2.5 V ≤ VLCD ≤ VDD 100 200 ± 0.2 ± 0.2 0 VODS 0 V Notes 1. 2. “Voltage deviation” means a difference between the output voltage and the ideal value of the segment and common outputs (VLCDn: n = 0, 1, or 2). The LCD controller/driver can select the following three display modes using a mask option: (1) Static : VLCD0 = V LCD VLCD1 = V LCD × 1/2 (3) 1/3 bias: VLCD0 = V LCD VLCD1 = V LCD × 2/3 VLCD2 = V LCD × 1/3 (2) 1/2 bias: VLCD0 = V LCD 43 µPD753304 DC Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Parameter Supply current Note 1 Symbol IDD1 Note 2 Conditions Main system clock 3.6 MHz RC oscillation Operation mode VDD = 5.0 V ± 10 % VDD = 5.0 V ± 10 %, TA = 25 °C Note 3 VDD = 3.0 V ± 10 % Note 4 VDD = 3.0 V ± 10 %, TA = 25 °C Note 4 Note 3 MIN. TYP. 2.1 2.1 MAX. 5.3 4.2 Unit mA mA 0.70 0.70 1.8 1.5 mA mA IDD2 Note 2 Main system clock 3.6 MHz RC oscillation HALT mode VDD = 5.0 V ± 10 % VDD = 5.0 V ± 10 %, TA = 25 °C VDD = 3.0 V ± 10 % VDD = 3.0 V ± 10 %, TA = 25 °C 1.4 1.4 3.5 2.8 mA mA 0.65 0.65 1.6 1.3 mA mA IDD3 Note 5 Subsystem clock RC oscillation Operation mode VDD = 5.0 V ± 10 % Note 6 VDD = 5.0 V ± 10 %, TA = 25 °C Note 6 VDD = 3.0 V ± 10 % Note 7 VDD = 3.0 V ± 10 %, TA = 25 °C Note 7 65 65 163 130 µA µA µA µA µA µA µA µA µA µA µA µA 18 18 45 36 IDD4 Note 5 Subsystem clock RC oscillation HALT mode VDD = 5.0 V ± 10 % Note 6 VDD = 5.0 V ± 10 %, TA = 25 °C Note 6 VDD = 3.0 V ± 10 % Note 7 VDD = 3.0 V ± 10 %, TA = 25 °C Note 7 58 58 150 120 9.5 9.5 25 20 IDD4 Note 8 STOP mode VDD = 5.0 V ± 10 % VDD = 5.0 V ± 10 %, TA = 25 °C VDD = 3.0 V ± 10 % VDD = 3.0 V ± 10 %, TA = 25 °C 0.05 0.05 10 5 0.02 0.02 5 3 Notes 1. 2. 3. 4. 5. 6. 7. 8. The current flowing through the internal pull-up resistor and LCD divider resistor is not included. When an external 6.8-kΩ resistor is connected. However, the temperature characteristics of the resistor are not included. When the µPD753304 operates in the high-speed mode with the processor clock control resistor (PCC) set to 0011. When the µPD753304 operates in the low-speed mode with the PCC reset to 0000. When the µPD753304 operates with the subsystem clock by setting the system clock control resistor (SCC) to 1001 and stopping the main system clock oscillation. The subsystem clock oscillation frequency (fCT) is 60 kHz when V DD = 5.0 V ± 10%. The subsystem clock oscillation frequency (fCT) is 55 kHz when V DD = 3.0 V ± 10%. When both the main system clock and subsystem clock are stopped by setting the sub oscillation circuit stop enable flag (SOS.3) to 1. 44 µPD753304 AC Characteristics (TA = –10 to +60 °C, VDD = 2.5 to 5.5 V) Parameter Main system clock frequency deviation Symbol fCC Conditions VDD = 5.0 V ± 10 %, R = 6.8 kΩ VDD = 3.0 V ± 10 %, R = 6.8 kΩ Subsystem clock frequency deviation Main system clock duty factor Note 1 CPU clock cycle time (Minimum instruction execution time = 1 machine cycle) Interrupt input high-, low-level width RESET low-level width Note 2 MIN. 3.1 TYP. 3.7 3.7 3.6 3.6 47 47 MAX. 4.3 4.0 4.2 3.9 74 74 55 60 64 64 148 Unit MHz MHz MHz MHz kHz kHz % % TA = 25 °C 3.3 2.8 TA = 25 °C 3.0 27 27 45 40 fCT VDD = 5.0 V ± 10 % VDD = 3.0 V ± 10 % fduty VDD = 5.0 V ± 10 % VDD = 3.0 V ± 10 % tCY Operates with main system clock VDD = 4.5 to 5.5 V VDD = 2.5 to 4.5 V 0.67 0.80 54 10 µs µs µs µs µs Operates with subsystem clock tINTH, tINTL tRSL INT1 10 Notes 1. 2. Main system clock duty factor = highlevel width of 1 clock/1 cycle of clock The cycle time (minimum instruction execution time) of the CPU clock (Φ) when the device operates with the main system clock is determined by the time constant of the internal capacitor (C: 10-pF typ.) and an externally connected resistor (R), and by the system clock control register (SCC) and processor clock control register (PCC). The cycle time of the CPU clock (Φ) when the device operates with the subsystem clock is determined by the time constant of the internal capacitor (C) and an internal resistor (R). The figure on the right shows the dependency of the cycle time tCY on supply voltage V DD when the device operates with the main system clock. 1 0.8 0.67 0.5 0 1 6 5 64 60 tCY vs VDD (Operates with main system clock) Operation guaranteed range 4 Cycle time tCY (µs) 3 2 2 2.5 3 3.3 4 4.5 5 5.5 6 Supply voltage VDD [V] 45 µPD753304 AC timing test points VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Interrupt input timing tINTL tINTH INT1 RESET input timing tRSL RESET 46 µPD753304 Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –10 to +60 °C) Parameter Release signal setup time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 0 56/fCC Note 2 TYP. MAX. Unit µs µs µs Notes 1. 2. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. Either 29/fCC or no wait can be selected by mask option. Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD tSREL STOP instruction execution RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 47 µPD753304 13. CHARACTERISTIC CURVE (reference) IDD vs VDD (main system clock : 3.6 MHz RC oscillation (with 6.8-kΩ external resistor connected), subsystem clock : 60 kHz RC oscillation) 10 (TA = 25 °C) 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 60 kHz oscillation 1.0 0.5 Supply current IDD (mA) 0.1 0.05 Subsystem clock operation mode Subsystem clock HALT mode and main system clock STOP mode + 60 kHz oscillation 0.01 0.005 CL1 CL2 RC oscillation 6.8 kΩ 0.001 0 1 2 3 5 4 Supply voltage VDD (V) 6 7 8 48 µPD753304 APPENDIX A. µ PD75308B, 753108 AND 753304 FUNCTIONAL LIST Parameter Program memory µPD75308B Mask ROM 0000H to 1F7FH (8064 × 8 bits) 000H to 1FFH (512 × 4 bits) 75X Standard Crystal/ceramic oscillation circuit Crystal oscillation circuit 2 /fX 17 µPD753108 Mask ROM 0000H to 1FFFH (8192 × 8 bits) µPD753304 Mask ROM 0000H to 0FFFH (4096 × 8 bits) 000H to 0FFH (256 × 4 bits) Data memory CPU Main system clock oscillation circuit Subsystem clock oscillation circuit Wait time when released by RESET signal 75XL CPU RC oscillation circuit RC oscillation circuit 2 /fX, 2 /fX (Selected by mask option) 17 15 56/fCC Wait time when STOP mode is released by interrupt occurrence Clock oscillation circuit which can executes STOP instruction 220/fX, 217/fX, 215/fX, 213/fX (Selected by setting of BTM) Main system clock oscillation circuit 512/fCC, with no wait (Selected by mask option) Main system clock oscillation circuit and subsystem clock oscillation circuit 1.1, 2.2, 4.4, 17.8 µs (during 3.6-MHz operation) Instruction execution time When main system clock is selected 0.95, 1.91, 15.3 µs (during 4.19-MHz operation) • 0.95, 1.91, 3.81, 15.3 µs (during 4.19-MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (during 6.0-MHz operation) When subsystem clock is selected Stack SBS register 122 µs (during 32.768-kHz operation) 85.1 µs (during 47-kHz operation) None SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection 000H to 1FFH When Mk I mode: 2-byte stack When Mk II mode: 3-byte stack When Mk I mode: unavailable When Mk II mode: available Available 0000H to 0FFH Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr I/O port CMOS input CMOS input/output Bit port output N-ch open-drain input/output Total 000H to 0FFH 2-byte stack Unavailable 3 machine cycles 2 machine cycles 8 16 8 8 40 Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 8 20 0 4 32 0 12 0 0 12 49 µPD753304 Parameter LCD controller/driver µPD75308B Segment selection: 24/28/32 segments (can be changed to CMOS I/O port in 4 time-unit; max. 8) µPD753108 Segment selection: 16/20/24 segments (can be changed to CMOS I/O port in 4 time-unit; max. 8) µPD753304 Segment selection: 20/24 segments (can be changed to CMOS I/O port in 4-time unit; max. 4) Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD driver can be specified by using mask option LCD driving voltage can not be selected Timer 3 channels • Basic interval timer: 1 channel • 8-bit timer/event counter: 1 channel • Watch timer: 1 channel 5 channels • Basic interval timer/ watchdog timer: 1 channel • 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter) • Watch timer: 1 channel • Φ, 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation) • Φ, 750, 375, 93.8 kHz (Main system clock: during 6.0-MHz operation) • 2, 4, 32 kHz (Main system clock: during 4.19-MHz operation or subsystem clock: during 32.768-kHz operation) • 2.93, 5.86, 46.9 kHz (Main system clock: 6.0-MHz operation) 3 channels • Basic interval timer/ watchdog timer: 1 channel • 8-bit timer counter: 1 channel (with subclock source input function) • Watchtimer: 1 channel • Φ, 3.6 MHz, 450 kHz, 225 kHz (Main system clock: during 3.6-MHz operation) On-chip split resistor for LCD driver Clock output (PCL) • Φ, 524, 262, 65.5 kHz (Main system clock: during 4.19-MHz operation) BUZ output (BUZ) 2 kHz (Main system clock: during 4.19-MHz operation) • 2.94, 5.88, 47 kHz (Subsystem clock: during 47-kHz operation) • 1.76, 3.52, 28.13-kHz (Main system clock: during 3.6-MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit • 2-wire serial I/O mode • SBI mode None Contained None SOS register Feedback resistor cut flag (SOS.0) Subsystem clock oscillation circuit current cut flag (SOS.1) Sub oscillation circuit stop enable flag (SOS.3) None None Contained None None Contained Register bank selection register (RBS) Vectored interrupt Supply voltage Operating ambient temperature Package None External: 3, internal: 3 VDD = 2.0 to 6.0 V TA = –40 to +85 ˚C • 80-pin plastic QFP (14 × 20 mm) • 80-pin plastic QFP (14 × 14 mm) • 80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Yes External: 3, internal: 5 VDD = 1.8 to 5.5 V External: 1, internal: 2 VDD = 2.5 to 5.5 V TA = –10 to +60 °C • 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic QFP (12 × 12 mm) • Volume production product: Pellet/wafer • ES product (for evaluation): 42-pin ceramic shrink DIP (600 mil) 50 µPD753304 APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the µPD753304. In the 75XL series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part number (product name) Host machine OS PC-9800 series MS-DOS™ Ver. 3.30 to Ver. 6.2 IBM PC/AT™ and compatible machines Refer to “OS for IBM PC” Note Distribution media 3.5-inch 2HD 5-inch 2HD µS5A13RA75X µS5A10RA75X µS7B13RA75X µS7B10RA75X 3.5-inch 2HC 5-inch 2HC Device file Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Refer to “OS for IBM PC” Note Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name) µS5A13DF753304 µS5A10DF753304 µS7B13DF753304 µS7B10DF753304 3.5-inch 2HC 5-inch 2HC Note Ver.5.00 and later have the task swap function, but it cannot be used for this software. Remark Operation of the assembler and the device file are guaranteed only on the above host machine and OSs. 51 µPD753304 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the µPD753304. The system configurations are described as follows. Hardware IE-75000-R Note 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753304, the emulation board IE-75300-R-EM and emulation probe EP-753304DU-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a µPD753304, the emulation board IE-75300-R-EM and emulation probe EP-753304DU-R which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine. IE-75001-R IE-75300-R-EM Emulation board for evaluating the application systems that use a µPD753304. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for ES products. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT and compatible machines Note 2 EP-753304DU-R Software IE control program Distribution media 3.5-inch 2HD 5-inch 2HD Part No. (product name) µS5A13IE75X µS5A10IE75X µS7B13IE75X µS7B10IE75X Refer to “OS for IBM PC” 3.5-inch 2HC 5-inch 2HC Notes 1. 2. Remark Maintenance parts. Ver.5.00 and later have the task swap function, but it cannot be used for this software. Operation of the IE control program is guaranteed only on the above host machines and OSs. OS for IBM PC The following IBM PC OS’s are supported. OS PC DOS™ Version Ver. 5.02 to Ver. 6.3 J6.1/V Note to J6.3/V Note Ver. 5.0 to Ver. 6.22 5.0/V Note to 6.2/V Note J5.02/V Note MS-DOS IBM DOS™ Note Only the English mode is supported. Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software. 52 µPD753304 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document No. Document Name English Japanese U11874J U12020J U10453J µPD753304 Data Sheet µPD753304 User’s Manual 75XL Series Selection Guide This document U12020E U10453E Development Tool Related Documents Document No. Document Name English Hardware IE-75000-R/IE-75001-R User’s Manual IE-75300-R-EM User’s Manual EP-753304DU-R User’s Manual Software RA75X Assembler Package User’s Manual Operation Language EEU-1416 U11354E U12173E EEU-1346 EEU-1363 Japanese EEU-846 U11354J U12173J U12622J U12385J Other Related Documents Document No. Document Name English IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer related Product Guide - Other Manufacturers C10943X C10535E C11531E C10983E C11892E MEI-1202 — C10535J C11531J C10983J C11892J C11893J U11416J Japanese Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 53 µPD753304 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 54 µPD753304 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 55 µPD753304 MS-DOS is a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 46