UPD8891CY

DATA SHEET MOS INTEGRATED CIRCUIT µ PD8891 (5340 × 5340) PIXELS × 3 + 2670 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD8891 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD8891 has 3 rows of (5340+5340) staggered pixels, and each row has a dual-sided readout type of charge transfer register, and has 3 rows of 2670 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell • Photocell pitch • Photocell size • Line spacing : (5340+5340) pixels × 3 + 2670 pixels × 3 : 5.25 µ m (1200 dpi), 10.5 µ m (300 dpi) : 5.25 × 5.25 µ m (1200 dpi), 10.5 × 8 µ m (300 dpi) : [1200 dpi sensor] 52.5 µ m (10 lines) Red line - Green line, Green line - Blue line 10.5 µm (2 lines) Odd line – Even line (for each color) [300 dpi sensor] 42 µ m (4 lines) Red line - Green line, Green line - Blue line • Color filter • Resolution : • Data rate • Power supply • On-chip circuits :: : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) : 48 dot/mm A4 (210 × 297 mm) size (shorter side) 1200 dpi US letter (8.5” × 11”) size (shorter side) : 5 MHz Max. : +12 V : Reset feed-through level clamp circuits Voltage amplifiers 7 2 2 • Drive clock level : CMOS output under 5 V operation ORDERING INFORMATION Part Number Package CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) µ PD8891CY The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16039EJ2V0DS00 (2nd edition) Date Published March 2003 NS CP (K) Printed in Japan 2002 µ PD8891 BLOCK DIAGRAM VOD 22 GND GND 1 11 φ RB 4 φ 2L 3 φ 2-1200 7 φ 1-1200 8 CCD analog shift register Transfer gate S10679 D153 D155 12 D156 D162 VOUT1 20 (Blue) Transfer gate CCD analog shift register CCD analog shift register Transfer gate S10679 D153 D155 S10680 D154 S2 ···· Photocell (Blue) ··· D161 D47 φ TG1 (Blue) S1 10 D156 D162 VOUT2 21 (Green) Transfer gate CCD analog shift register CCD analog shift register Transfer gate S10679 D153 S10680 D154 S2 ···· Photocell (Green) ··· D161 D47 φ TG2 (Green) S1 9 D155 S10680 D156 D162 VOUT3 (Red) D154 2 Transfer gate CCD analog shift register S2 ···· Photocell (Red) ··· ···· Photocell (Blue) Transfer gate S2670 D13 D39 D40 D161 D47 φ TG3 (Red) S1 CCD analog shift register ···· Photocell (Green) Transfer gate S2670 D40 D40 D13 D39 CCD analog shift register ···· Photocell (Red) Transfer gate S2670 D13 D39 CCD analog shift register 5 19 17 14 16 D41 S1 S2 D41 S1 S2 D41 S1 S2 13 15 φ CLB φ SEL φ 1L φ 2-300 φ 2-300 φ 1-300 φ 1-300 2 Data Sheet S16039EJ2V0DS µ PD8891 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • µ PD8891CY Ground Output signal 3 (Red) Last stage shift register clock 2 Reset gate clock Reset feed-through level level clamp clock No connection Shift register clock 2 (for 1200 dpi) Shift register clock 1 (for 1200 dpi) Transfer gate clock 3 (for Red) Transfer gate clock 2 (for Green) Ground GND VOUT3 1 2 3 4 5 22 21 VOD VOUT2 VOUT1 Output drain voltage Output signal 2 (Green) Output signal 1 (Blue) 300/1200 dpi select input No connection Last stage shift register clock 1 Shift register clock 2 (for 300 dpi) Shift register clock 1 (for 300 dpi) Shift register clock 2 (for 300 dpi) Shift register clock 1 (for 300 dpi) Transfer gate clock 1 (for Blue) φ 2L φ RB φ CLB NC 1 1 1 1 1 1 20 19 18 φ SEL NC Red Green Blue Red Green Blue 6 7 8 9 17 16 15 14 φ 1L φ 2-300 φ 1-300 φ 2-300 φ 1-300 φ 2-1200 φ 1-1200 10680 10680 10680 φ TG3 φ TG2 GND 10 11 2670 2670 2670 13 12 φ TG1 Caution Connect the No connection pins (NC) to GND. Data Sheet S16039EJ2V0DS 3 µ PD8891 PHOTOCELL STRUCTURE DIAGRAM 1200 dpi sensor 300 dpi sensor 2.75 µ m 2.5 µ m 8.0 µ m 2.5 µ m 5.25 µ m Channel stopper 8.0 µ m Channel stopper Aluminium shield Aluminium shield PHOTOCELL ARRAY STRUCTURE DIAGRAM 1 (Line Spacing) 10.5 µ m Blue photocell array 4 lines (42 µ m) 300 dpi sensor 10.5 µ m Green photocell array 4 lines (42 µ m) 10.5 µ m Red photocell array 42 µ m 5.25 µ m 5.25 µ m 5.25 µ m Blue photocell array Blue photocell array 5.25 µ m 8 lines (42 µ m) 1200 dpi sensor 5.25 µ m 5.25 µ m 5.25 µ m Green photocell array Green photocell array 2 lines (10.5 µ m) 8 lines (42 µ m) 5.25 µ m 5.25 µ m 5.25 µ m Red photocell array Red photocell array 2 lines (10.5 µ m) 10 lines (52.5 µ m) 10 lines (52.5 µ m) 4 Data Sheet S16039EJ2V0DS µ PD8891 PHOTOCELL ARRAY STRUCTURE DIAGRAM 2 (The Relation of the Photocell Array) Dummy 46 pixels Optical black 100 pixels Invalid photocell 8 pixels Valid photocell 10680 pixels Invalid photocell 8 pixels 10831 10833 10835-10841 1-45 1200 dpi 2-46 48-146 148 150 152 154 156 158 − 10832 10834 10836-10842 47-145 147 149 151 153 155 157 − 12 pixels 25 pixels 2 pixels 2670 pixels 2 pixels 300 dpi 1-12 13-37 38, 39 40 − 2709 2710, 2711 Data Sheet S16039EJ2V0DS 5 µ PD8891 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage 300/1200 dpi select signal voltage Transfer gate clock voltage Operating ambient temperature Storage temperature Note Symbol VOD Vφ 1-300, Vφ 1-1200, Vφ 1L, Vφ 2-300, Vφ 2-1200, Vφ 2L Vφ RB Vφ CLB Vφ SEL Vφ TG1 to Vφ TG3 TA Tstg Ratings −0.3 to +15 −0.3 to +8 −0.3 to +8 −0.3 to +8 −0.3 to +8 −0.3 to +8 0 to +60 −40 to +70 Unit V V V V V V °C °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Output drain voltage Shift register clock high level Shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level 300/1200 dpi select signal high level 300/1200 dpi select signal low level Transfer gate clock high level Transfer gate clock low level Data rate VOD Vφ 1-300H, Vφ 1-1200H, Vφ 1LH, Vφ 2-300H, Vφ 2-1200H, Vφ 2LH Vφ 1-300L, Vφ 1-1200L, Vφ 1LL, Vφ 2-300L, Vφ 2-1200L, Vφ 2LL Vφ RBH Vφ RBL Vφ CLBH Vφ CLBL Vφ SELH Vφ SELL Vφ TG1H to Vφ TG3H Vφ TG1L to Vφ TG3L fφ RB 4.5 −0.3 4.5 −0.3 4.5 −0.3 4.75 −0.3 − 5.0 0 5.0 0 5.0 0 Vφ 1-300H, Vφ 1-1200H 0 2.0 Note Symbol Min. 11.4 4.75 −0.3 Typ. 12.0 5.0 0 Max. 12.6 5.25 +0.25 5.5 +0.5 5.5 +0.5 5.5 +0.5 Vφ 1-300H, Vφ 1-1200H Note Unit V V V V V V V V V V V MHz +0.15 5.0 Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than shift register clock high level (Vφ 1-300H, Vφ 1-1200H), image lag can increase. 6 Data Sheet S16039EJ2V0DS µ PD8891 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Saturation voltage Symbol Vsat 300 dpi 1200 dpi Saturation exposure Red SER 300 dpi 1200 dpi Green SEG 300 dpi 1200 dpi Blue SEB 300 dpi 1200 dpi Photo response non-uniformity Average dark signal PRNU ADS VOUT = 1.0 V Light shielding Light shielding Dark signal non-uniformity DSNU Light shielding Light shielding Power consumption Output impedance Response Red PW ZO RR 300 dpi 1200 dpi Green RG 300 dpi 1200 dpi Blue Note 1 Test Conditions Min. 2.5 2.0 − − − − − − − 300 dpi 1200 dpi 300 dpi 1200 dpi − − − − − − 11.32 3.77 10.73 3.58 6.89 2.30 4.5 Typ. 2.7 2.4 0.167 0.445 0.176 0.470 0.274 0.732 6 0.4 0.2 4.0 2.0 300 0.4 16.17 5.39 15.33 5.11 9.84 3.28 6.0 3.0 25 98 1.0 630 540 460 675 1200 2700 2400 −500 1.0 Max. − − − − − − − − 20 4.0 2.0 12.0 6.0 480 1.0 21.02 7.01 19.93 6.64 12.79 4.26 7.5 7.0 − − 4.0 − − − − − − − +1000 − Unit V V lx•s lx•s lx•s lx•s lx•s lx•s % mV mV mV mV mW kΩ V/lx•s V/lx•s V/lx•s V/lx•s V/lx•s V/lx•s V % ns % % nm nm nm times times times times mV mV RB 300 dpi 1200 dpi Offset level Image lag VOS IL Note 2 VOUT = 1.0 V VOUT = 1.0 V VOUT = 1.0 V, data rate = 5 MHz VOUT = 1.0 V (1200 dpi) − − 92 − − − − Output fall delay time td TTE RI Red Green Blue Total transfer efficiency Register imbalance Response peak Dynamic range DR1 Vsat/DSNU Vsat/DSNU Vsat/σ CDS Vsat/σ CDS Light shielding Light shielding 300 dpi 1200 dpi 300 dpi 1200 dpi − − − − −2000 − DR2 Note 1 Reset feed-through noise Random noise (CDS) RFTN σ CDS Notes 1. Refer to TIMING CHART 2−1 to 2−8. 2. W hen the fall time of φ 1L or φ 2L (t1’, t2’) is the Typ. value (refer to TIMING CHART 2−1 to 2−8). Data Sheet S16039EJ2V0DS 7 µ PD8891 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Symbol Cφ 1-300 Pin name Pin No. 13 15 Cφ 1-1200 Shift register clock pin capacitance 2 Cφ 2-300 Min. − − − − − − − − − − − − − − Typ. 250 250 850 300 300 850 15 15 15 15 15 200 200 200 Max. − − − − − − − − − − − − − − Unit pF pF pF pF pF pF pF pF pF pF pF pF pF pF φ 1-300 φ 1-1200 φ 2-300 φ 2-1200 φ 1L φ 2L φ RB φ CLB φ SEL φ TG1 φ TG2 φ TG3 8 14 16 Cφ 2-1200 Last stage sift reset gate clock pin capacitance 1 Last stage sift reset gate clock pin capacitance 2 Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance 300/1200 dpi select signal pin capacitance Transfer gate clock pin capacitance Cφ 1L Cφ 2L Cφ RB Cφ CLB Cφ SEL Cφ TG 7 17 3 4 5 19 12 10 9 300/600/1200 MODE Mode 1 2 3 Description 300 dpi only 600 dpi only Note 1 φ SEL High Low Low 300 dpi data Use Flush Flush Note 2 Note 2 φ 1-300, φ 2-300 Clocked Clocked Clocked 1200 dpi data Flush Note 2 φ 1-1200, φ 2-1200 Clocked Clocked Clocked Use 1 line Use 1200 dpi only Notes 1. For 600 dpi mode, the reset pulse is extended to allow second line’s charge to dump immediately to DC level. 2. Flush means that data is continuously sunk via reset gate. 8 Data Sheet S16039EJ2V0DS TIMING CHART 1−1 (1200 dpi, for each color) φ TG1 to φ TG3 φ 1-1200, φ 1L φ 2-1200, φ 2L φ RB Note Data Sheet S16039EJ2V0DS Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode) 10834 10835 10842 10843 146 147 154 155 VOUT1 to VOUT3 45 46 47 1 2 3 4 5 6 Optical black (100 pixels) Invalid photocell (8 pixels) Valid photocell (10680 pixels) Invalid photocell (8 pixels) µ µ µ PD8891 µ Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. 9 10832 10834 10836 VOUT1 to VOUT3 Optical black (50 pixels) Invalid photocell (4 pixels) Valid photocell (5340 pixels) Invalid photocell (4 pixels) 10842 144 146 148 154 156 158 44 46 48 50 2 4 10 Data Sheet S16039EJ2V0DS TIMING CHART 1−2 (600 dpi, even pixel, for each color) φ TG1 to φ TG3 φ 1-1200, φ 1L φ 2-1200, φ 2L φ RB Note Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode) µ µ µ PD8891 µ Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. TIMING CHART 1−3 (600 dpi, odd pixel, for each color) φ TG1 to φ TG3 φ 1-1200, φ 1L φ 2-1200, φ 2L φ RB Note Data Sheet S16039EJ2V0DS Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode) 10831 10833 10835 10841 143 145 147 153 155 157 43 45 47 VOUT1 to VOUT3 Optical black (50 pixels) Invalid photocell (4 pixels) 49 1 3 Valid photocell (5340 pixels) Invalid photocell (4 pixels) µ µ µ PD8891 µ Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. 11 VOUT1 to VOUT3 Optical black (25 pixels) Invalid photocell (2 pixels) Valid photocell (2670 pixels) Invalid photocell (2 pixel) 2708 2709 2710 2711 2712 1 2 3 4 5 6 7 8 9 10 11 12 13 14 36 37 38 39 40 41 12 Data Sheet S16039EJ2V0DS TIMING CHART 1−4 (300 dpi, for each color) φ TG1 to φ TG3 φ 1-300, φ 1L φ 2-300, φ 2L φ RB Note Note φ CLB (Bit clamp mode) φ CLB (Line clamp mode) µ µ µ PD8891 µ Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. µ PD8891 TIMING CHART 2−1 (1200 dpi, bit clamp mode, for each color) t1 90% 10% 90% 10% t1’ t2’ t2 φ 1-1200 φ 2-1200 φ 1L φ 2L t5 90% 10% t7 t9 t8 t3 t6 t4 90% 10% 90% 10% t5 t3 t6 t4 φ RB t10 t11 t7 t9 t8 t10 t11 φ CLB + 90% 10% td RFTN td VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3 t4 t5, t6 t7 t8 t9, t10 t11 Min. 0 0 20 50 0 −5 Note Typ. 25 5 50 150 5 +25 50 5 25 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns 20 0 5 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 13 µ PD8891 TIMING CHART 2−2 (1200 dpi, line clamp mode, for each color) t1 90% 10% 90% 10% t1’ t2’ t2 φ 1-1200 φ 2-1200 φ 1L φ 2L t5 90% 10% t3 t6 t4 90% 10% 90% 10% t5 t3 t6 t4 φ RB φ CLB “H” + RFTN VOUT – td td RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3 t4 t5, t6 Min. 0 0 20 50 0 Typ. 25 5 50 150 5 Max. − − − − − Unit ns ns ns ns ns 14 Data Sheet S16039EJ2V0DS µ PD8891 TIMING CHART 2−3 (600 dpi, even pixel, bit clamp mode, for each color) t1 t2 90% 10% φ 1-1200 φ 2-1200 t1’ 90% 10% t2’ 90% 10% φ 1L φ 2L t5 90% 10% t7 t9 90% 10% + t8 t10 t11 t3’ t3’ t6 t4 90% 10% φ RB φ CLB td RFTN VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3’ t4 t5, t6 t7 t8 t9, t10 t11 Min. 0 0 50 50 0 −5 Note Typ. 25 5 100 370 5 +25 200 5 100 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns 100 0 5 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 15 µ PD8891 TIMING CHART 2−4 (600 dpi, even pixel, line clamp mode, for each color) t1 t2 90% 10% φ 1-1200 φ 2-1200 t1’ 90% 10% t2’ 90% 10% φ 1L φ 2L t5 90% 10% t3’ t3’ t6 t4 90% 10% φ RB φ CLB “H” td + RFTN VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3’ t4 t5, t6 Min. 0 0 50 50 0 Typ. 25 5 100 370 5 Max. − − − − − Unit ns ns ns ns ns 16 Data Sheet S16039EJ2V0DS µ PD8891 TIMING CHART 2−5 (600 dpi, odd pixel, bit clamp mode, for each color) t2 t1 φ 1-1200 90% 10% φ 2-1200 90% 10% t2’ t1’ φ 1L 90% 10% φ 2L t5 90% 10% 90% 10% t3’ t3’ t6 t4 φ RB t9 t7 90% 10% + t8 t10 t11 φ CLB td RFTN VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3’ t4 t5, t6 t7 t8 t9, t10 t11 Min. 0 0 50 50 0 −5 Note Typ. 25 5 100 370 5 +25 200 5 100 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns 100 0 5 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 17 µ PD8891 TIMING CHART 2−6 (600 dpi, odd pixel, line clamp mode, for each color) t2 t1 φ 1-1200 90% 10% φ 2-1200 90% 10% t2’ t1’ φ 1L 90% 10% φ 2L t5 90% 10% 90% 10% t3’ t3’ t6 t4 φ RB φ CLB “H” td + RFTN VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3’ t4 t5, t6 Min. 0 0 50 50 0 Typ. 25 5 100 370 5 Max. − − − − − Unit ns ns ns ns ns 18 Data Sheet S16039EJ2V0DS µ PD8891 TIMING CHART 2−7 (300 dpi, bit clamp mode, for each color) t1 t2 φ 1-300 90% 10% φ 2-300 90% 10% t1’ t2’ φ 1L 90% 10% φ 2L t5 90% 10% t7 t9 90% 10% + t8 t10 t3 t6 t4 90% 10% φ RB t11 φ CLB td RFTN VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3 t4 t5, t6 t7 t8 t9, t10 t11 Min. 0 0 20 50 0 −5 Note Typ. 25 5 50 150 5 +25 50 5 25 Max. − − − − − − − − − Unit ns ns ns ns ns ns ns ns ns 20 0 5 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 19 µ PD8891 TIMING CHART 2−8 (300 dpi, line clamp mode, for each color) t1 t2 φ 1-300 90% 10% φ 2-300 90% 10% t1’ t2’ φ 1L 90% 10% φ 2L t5 90% 10% t3 t6 t4 90% 10% φ RB φ CLB “H” + td RFTN VOUT – RFTN VOS 10% Symbol t1, t2 t1’, t2’ t3 t4 t5, t6 Min. 0 0 20 50 0 Typ. 25 5 50 150 5 Max. − − − − − Unit ns ns ns ns ns 20 Data Sheet S16039EJ2V0DS µ PD8891 φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART t13 t12 t14 φ TG1 to φ TG3 90% 10% t15 90% t16 90% φ 1-300, φ 1-1200 φ 2-300, φ 2-1200 t17 Note 1 t18 φ RB 90% t7 t11 φ CLB (Bit clamp mode) 90% t22 t20 Note 2 t21 t23 φ CLB (Line clamp mode) 90% 10% t9 t19 t10 Symbol t7 t9, t10 t11 t12 t13, t14 t15, t16 t17, t18 t19 t20, t21 t22, t23 Min. −5 Note 3 Typ. +25 5 25 10000 50 1000 400 t12 50 350 Max. − − − 50000 − − − 50000 − − Unit ns ns ns ns ns ns ns ns ns ns 0 5 5000 0 900 200 t12 0 0 Notes 1. Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during this period. 2. Set the φ RB pulse to high level during this period. 3. Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. Data Sheet S16039EJ2V0DS 21 µ PD8891 φ 1-300, φ 2-300 cross points φ 1-300 1.0 V to 4.0 V 1.0 V to 4.0 V φ 2-300 φ 1-1200, φ 2-1200 cross points φ 1-1200 1.0 V to 4.0 V 1.0 V to 4.0 V φ 2-1200 φ 1-300, φ 1-1200, φ 2L cross points φ 1-300, φ 1-1200 2.0 V or more 0.5 V or more φ 2L φ 2-300, φ 1-1200, φ 1L cross points φ 2-300, φ 2-1200 2.0 V or more 0.5 V or more φ 1L Remark Adjust cross points (φ 1-300, φ 2-300), (φ 1-1200, φ 2-1200), (φ 1-300, φ 1-1200, φ 2L) and (φ 2-300, φ 11200, φ 1L) with input resistance of each pin. 22 Data Sheet S16039EJ2V0DS µ PD8891 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x  Valid pixels j=1 Σx j x= Valid pixels xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. Valid pixels j=1 Σd j ADS (mV) = Valid pixels dj : Dark signal of valid pixel number j Data Sheet S16039EJ2V0DS 23 µ PD8891 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to valid pixels dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = V1 × 100 VOUT 24 Data Sheet S16039EJ2V0DS µ PD8891 9. Register Imbalance : RI (1200 dpi) The rate of the difference between the averages of the output voltage of Odd and Even bits, against the average output voltage of all the valid pixels. n 2 n RI (%) = j=1 ∑ (V2j –1 – V2j) 1 n j=1 2 ∑ Vj n : Number of valid pixels Vj : Output voltage of each pixel n × 100 10. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the Video Output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = i=1 Σ (VCDS – V) i 2 , V= 1 100 100 100 i = 1 Σ VCDS i Video output Reset feed-through Data Sheet S16039EJ2V0DS 25 µ PD8891 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 2 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 4 Relative Output Voltage 2 1 0.5 Relative Output Voltage 10 20 30 40 50 1 0.25 0.2 0.1 0 0.1 1 5 Storage Time (ms) 10 Operating Ambient Temperature TA (°C) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter ) (TA = +25°C) 100 R B 80 G Response Ratio (%) 60 40 G 20 B 0 400 500 600 Wavelength (nm) 700 800 26 Data Sheet S16039EJ2V0DS µ PD8891 APPLICATION CIRCUIT EXAMPLE +5 V +12 V + + µ PD8891 10 µ F/16 V 0.1 µ F B3 0.1 µ F VOD VOUT2 VOUT1 22 21 20 19 18 17 16 15 14 13 12 150 Ω 150 Ω 4.7 Ω 4.7 Ω 4.7 Ω 4.7 Ω 10 Ω B2 B1 47 µ F/25 V +5 V 1 2 3 47 Ω 47 Ω 150 Ω 4.7 Ω 4.7 Ω 10 Ω 10 Ω 4 5 6 7 8 9 10 11 GND VOUT3 φ 2L φ RB φ CLB φ 2L φ RB φ CLB NC + φ SEL NC 0.1 µ F 10 µ F/16 V φ SEL φ 1L φ 1-300 φ 2-300 φ 1-300 φ 2-300 φ 1L φ 2-1200 φ 1-1200 φ 2-1200 φ 1-1200 φ TG3 φ TG2 GND φ 1-300 φ 2-300 φ TG1 φ TG Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 ≤ data rate < 5 MHz). 2. B1 to B3 in the application circuit example are shown in the figure blow. B1 to B3 EQUIVALENT CIRCUIT +12 V + 100 Ω CCD VOUT 100 Ω 2SC945 2 kΩ 47 µ F/25 V Data Sheet S16039EJ2V0DS 27 µ PD8891 PACKAGE DRAWING µ PD8891CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 44.0±0.3 1st valid pixel 0.5±0.3 22 1 9.25±0.3 12 1 37.5 11 2.0 10.16±0.2 1.02±0.15 4.39±0.4 (1.72) 2 2.62±0.2 0.46±0.1 2.54±0.25 (5.42) 4.21±0.5 3 0.25±0.05 10.16 + 0.7 − 0.2 Name Plastic cap Dimensions 42.9×8.35×0.7 Refractive index 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 22C-1CCD-PKG11-1 28 Data Sheet S16039EJ2V0DS µ PD8891 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD8891CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Conditions Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin) Cautions 1. 2. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S16039EJ2V0DS 29 µ PD8891 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. 30 Data Sheet S16039EJ2V0DS µ PD8891 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD o r GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16039EJ2V0DS 31 µ PD8891 • The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. • NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1