5497DMQB

5497 DM7497 Synchronous Modulo-64 Bit Rate Multiplier June 1989 5497 DM7497 Synchronous Modulo-64 Bit Rate Multiplier General Description The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency The output pulse rate relative to the clock frequency is determined by signals applied to the Select (S0–S5) inputs Both true and complement outputs are available along with an enable input for each A Count Enable input and a Terminal Count output are provided for cascading two or more packages An asynchronous Master Reset input prevents counting and resets the counter Connection Diagram Dual-In-Line Package Logic Symbol TL F 9780 – 2 TL F 9780 – 1 VCC e Pin 16 GND e Pin 8 Order Number 5497DMQB 5497FMQB or DM7497N See NS Package Number J16A N16E or W16A Pin Names S0–S5 EZ EY CE CP MR OZ Oy TC Description Rate Select Inputs OZ Enable Input (Active LOW) OY Enable Input Count Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH) Gated Clock Output (Active LOW) Complement Output (Active HIGH) Terminal Count Output (Active LOW) C1995 National Semiconductor Corporation TL F 9780 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range b 55 C to a 125 C 54 DM74 0 C to a 70 C b 65 C to a 150 C Storage Temperature Range Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Recommended Operating Conditions’’ table will define the conditions for acutual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA ts(L) th(H) th(L) tw(H) tw(L) tw(H) Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature Setup Time LOW CE to CP Rising Hold Time HIGH CE to CP Rising Hold Time LOW CE to CP Falling CP Pulse Width HIGH CP Pulse Width LOW MR Pulse Width HIGH b 55 5497 Nom 5 Max 55 Min 4 75 2 08 b0 4 DM7497 Nom 5 Max 5 25 Units V V 08 b0 4 45 2 V mA mA C ns ns ns ns ns 16 125 0 25 0 0 20 16 70 25 0 0 20 20 15 15 ns Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage Max Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VCC e Min IOL e Max VIH e Min VCC e Max VI e 5 5V VCC e Max VI e 2 4V Clock Inputs VCC e Max VI e 0 4V Clock Inputs VCC e Max (Note 2) VCC e Max DM74 54 DM74 54 54 DM74 b 20 b 18 Min Typ (Note 1) Max b1 5 Units V V 24 34 02 04 1 40 80 b1 6 b3 2 b 55 b 55 V mA mA High Level Input Current Low Level Input Current mA Short Circuit Output Current Supply Current With Outputs High mA 120 mA 2 Switching Characteristics VCC e a 5 0V TA e a 25 C (See Section 1 for waveforms and load configurations) 5497 Symbol Parameter CL e 15 pF RL e 400X Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay EZ to OZ Propagation Delay EZ to OY Propagation Delay EY to OY Propagation Delay Sn to OY Propagation Delay Sn to OZ Propagation Delay CP to OY Propagation Delay CP to OZ Propagation Delay CP to TC Propagation Delay CE to TC Propagation Delay MR to OY Propagation Delay MR to OZ 25 18 23 30 33 14 10 23 23 14 14 39 30 18 26 35 33 25 21 43 34 Max DM7497 CL e 15 pF RL e 400X Min 25 18 23 30 33 14 10 23 23 14 14 39 30 18 26 30 33 20 21 36 23 Max MHz ns ns ns ns ns ns ns ns ns ns ns Units Timing Diagrams TL F 9780 – 5 TL F 9780 – 6 3 Functional Description The ’97 contains six JK flip-flops connected as a synchronous modulo-64 binary counter A LOW signal on the Count Enable (CE) input permits counting with all state changes initiated simultaneously by the rising edge of the clock When the count reaches maximum (63) with all Qs HIGH the Terminal Count (TC) output will be LOW if CE is LOW A HIGH signal on Master Reset (MR) resets the flip-flops and prevents counting although output pulses can still occur if the clock is running EZ is LOW and S5 is HIGH The flip-flop outputs are decoded by a 6-wide AND-OR-INVERT gate Each AND gate also contains the buffered and inverted CP and Z-enable (EZ) functions as well as one of the Select (S0 – S5) inputs The Z output OZ is normally HIGH and goes LOW when CP and EZ are LOW and any of the AND gates has its other inputs HIGH The AND gates are enabled by the counter at different times and different rates relative to the clock For example the gate to which S5 is connected is enabled during every other clock period assuming S5 is HIGH Thus during one complete cycle of the counter (64 clocks) the S5 gate is enabled 32 times and can therefore gate 32 clocks per cycle to the output The S4 gate is enabled 16 times per cycle the S3 gate 8 times per cycle etc The output pulse rate thus depends on the clock rate and which of the S0–S5 inputs is HIGH fout e m  fin 64 ing pulses passed by two or more of the AND gates The Pulse Pattern Table indicates the output pattern for several values of m In each row a one means that the OZ output will be HIGH during that entire clock period while a zero means that OZ will be LOW when the clock is LOW in that period The first column in the output field coincides with the ‘‘all zeroes’’ condition of the counter while the last column represents the ‘‘all ones’’ condition The pulse pattern for any particular value of m can be deduced by factoring it into the sum of appropriate powers of two (e g 19 e 16 a 2 a 1) and combining the pulses (i e the zeroes) shown for each for the relevant powers of two (e g for m e 16 2 and 1) The Y output OY is the complement of OZ and is thus normally LOW A LOW signal on the Y-enable input EY disables Oy To expand the multiplier to 12-bit rate select two packages can be cascaded as shown in Figure A Both circuits operate from the basic clock with the TC output of the first acting to enable both counting and the output pulses of the second package Thus the second counter advances at only the rate of the first and a full cycle of the two counters combined requires 4096 clocks Each rate select input of the first package has 64 times the weight of its counterpart in the second package fout e m1 a m2  fin 64  64 Where m e S5  25 a S4  24 a S3  23 a S2  22 a S1  21 a S0  20 Thus by appropriate choice of signals applied to the S0–S5 inputs the output pulse rate can range from to of the clock rate as suggested in Rate Select Table There is no output pulse when the counter is in the ‘‘all ones’’ condition When m is 1 2 4 8 16 or 32 the output pulses are evenly spaced assuming that the clock frequency is constant For any other value of m the output pulses are not evenly spaced since the pulse train is formed by interleav- Where m1 e S5  211 a S4  210 a S3  29 a S2  28 a S1  27 a S0  26 (first package) m2 e S5  25 a S4  24 a S3  23 a S2  22 a S1  21 a S0  20 (second package) Combined output pulses are obtained in Figure A by letting the Z output of the first circuit act as the Y-enable function for the second with the interleaved pulses obtained from the Y output of the second package being opposite in phase to the clock TL F 9780 – 3 FIGURE A Cascading for 12-Bit Rate Select 4 Functional Description (Continued) Mode and Rate Select Table (Note 1) Inputs MR H L L L L L L L L L L CE X L L L L L L L L L L EZ H L L L L L L L L L L S5 X L L L L L L H H H H S4 X L L L L L H L H H L S3 X L L L L H L L H H L S2 X L L L H L L L H H L S1 X L L H L L L L H H L S0 X L H L L L L L H H L Clock Pulses X 64 64 64 64 64 64 64 64 64 64 Outputs EY H H H H H H H H H L H OY L L 1 2 4 8 16 32 63 H 40 OZ H H 1 2 4 8 16 32 62 63 40 TC H 1 1 1 1 1 1 1 1 1 1 2 3 3 3 3 3 3 3 3 4 5 Notes H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Note 1 Numerals indicate number of pulses per cycle Note 2 This is a simplified illustration of the clear function CP and EZ also affect the logic level of OY and OZ A LOW signal on EY will cause OY to remain HIGH Note 3 Each rate illustrated assumes S0–S5 are constant throughout the cycle however these illustrations in no way prohibit variablerate operation Note 4 EY is used to inhibit output Y fin (32 a 8) fin 40 fin e e e 0 625 fin Note 5 fout e m  64 64 64 Pulse Pattern Table m 1 2 3 4 5 6 8 10 12 14 16 20 24 28 32 Output Pulse Pattern at OZ 1111111111111111111111111111111011111111111111111111111111111111 1111111111111110111111111111111111111111111111101111111111111111 1111111111111110111111111111111011111111111111101111111111111111 1111111011111111111111101111111111111110111111111111111011111111 1111111011111111111111101111111011111110111111111111111011111111 1111111011111110111111101111111111111110111111101111111011111111 1110111111101111111011111110111111101111111011111110111111101111 1110111111101111111011111110111111101111111011101110111111101111 1110111011101111111011101110111111101110111011111110111011101111 1110111011101110111011101110111111101110111011101110111011101111 1011101110111011101110111011101110111011101110111011101110111011 1011101010111011101110101011101110111010101110111011101110111011 1010101110101011101010111010101110101011111010111010101110101011 1010101010101011101010101010101110101010101010111010101010101011 010101 0101 5 Logic Diagram TL F 9780 – 4 6 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 5497DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM7497N NS Package Number N16E 7 5497 DM7497 Synchronous Modulo-64 Bit Rate Multiplier Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 5497FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications