LF13508M

LF13508 8-Channel Analog Multiplexer LF13509 4-Channel Differential Analog Multiplexer January 1995 LF13508 8-Channel Analog Multiplexer LF13509 4-Channel Differential Analog Multiplexer General Description The LF13508 is an 8-channel analog multiplexer which connects the output to 1 of the 8 analog inputs depending on the state of a 3-bit binary address An enable control allows disconnecting the output thereby providing a package select function This device is fabricated with National’s BI-FET technology which provides ion-implanted JFETs for the analog switch on the same chip as the bipolar decode and switch drive circuitry This technology makes possible low constant ‘‘ON’’ resistance with analog input voltage variations This device does not suffer from latch-up problems or static charge blow-out problems associated with similar CMOS parts The digital inputs are designed to operate from both TTL and CMOS levels while always providing a definite break-before-make action The LF13509 is a 4-channel differential analog multiplexer A 2-bit binary address will connect a pair of independent analog inputs to one of any 4 pairs of independent analog outputs The device has all the features of the LF13508 series and should be used whenever differential analog inputs are required Features Y Y Y Y Y Y Y Y Y Y JFET switches rather than CMOS No static discharge blow-out problem No SCR latch-up problems Analog signal range 11V b15V Constant ‘‘ON’’ resistance for analog signals between b 11V and 11V ‘‘ON’’ resistance 380 X typ Digital inputs compatible with TTL and CMOS Output enable control Break-before-make action tOFF e 0 2 ms tON e 2 ms typ Lower leakage devices available Functional Diagrams and Truth Tables LF13508 EN H H H H H H H H L LF13509 EN L H H H H A1 X L L H H A0 X L H L H SWITCH PAIR ON None S1 S2 S3 S4 A2 L L L L H H H H X A1 L L H H L L H H X A0 L H L H L H L H X SWITCH ON S1 S2 S3 S4 S5 S6 S7 S8 NONE TL H 5668 – 1 C1995 National Semiconductor Corporation TL H 5668 RRD-B30M115 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Positive Supply b Negative Supply (VCCbVEE) 36V Positive Analog Input Voltage (Note 1) VCC b VEE Negative Analog Input Voltage (Note 1) Positive Digital Input Voltage VCC b 5V Negative Digital Input Voltage Analog Switch Current lISl k10 mA 500 mW 900 mW 500 mW 100 C Maximum Junction Temperature (TjMAX) Operating Temperature Range 0 CsTAs a 70 C b 65 C to a 150 C Storage Temperature Range Lead Temperature D Package (Soldering 10 seconds) 300 C N Package (Soldering 10 seconds) 260 C Surface Mount Package (SO) Vapor Phase (60 seconds) 215 C Infrared (15 seconds) 220 C Power Dissipation (PD at 25 C) (Notes 2 7) Molded DIP (N) PD Cavity DIP (D) PD Small Outline (SO) PD Electrical Characteristics (Note 3) Symbol RON DRON RON Match IS(OFF) ID(OFF) ID(ON) VINH VINL IINL IINL(EN) tTRAN tOPEN tON(EN) tOFF(EN) ISO(OFF) CT CS(OFF) CD(OFF) ICC IEE Parameter ‘‘ON’’ Resistance DRON with Analog Voltage Swing RON Match Between Switches Source Current in ‘‘OFF’’ Condition Drain Current in ‘‘OFF’’ Condition Leakage Current in ‘‘ON’’ Condition Digital ‘‘1’’ Input Voltage Digital ‘‘0’’ Input Voltage Digital ‘‘0’’ Input Current Digital ‘‘0’’ Enable Current Switching Time of Multiplexer Break-Before-Make Enable Delay ‘‘ON’’ Enable Delay ‘‘OFF’’ ‘‘OFF’’ Isolation Crosstalk Source Capacitance (‘‘OFF’’) Drain Capacitance (‘‘OFF’’) Positive Supply Current Negative Supply Current VIN e 0 7V VEN e 0 7V TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C TA e 25 C 15 12 18 16 16 02 b 66 b 66 Conditions Min VOUT e 0V IS e 100 mA b 10V s VOUT s a 10V IS e 100 mA LF13508 LF13509 Typ 380 500 TA e 25 C TA e 25 C TA e 25 C 0 09 TA e 25 C 06 TA e 25 C 1 20 07 30 40 30 40 0 01 20 Max 650 850 1 150 5 50 20 500 20 500 TA e 25 C Units X X % X nA nA nA nA nA nA V V mA mA mA mA ms ms ms ms dB dB pF pF 12 15 5 6 mA mA mA mA VOUT e 0V IS e 100 mA Switch ‘‘OFF’’ VS e 11 VD eb11 (Note 4) Switch ‘‘OFF’’ VS e 11 VD eb11 (Note 4) Switch ‘‘ON’’ VD e 11V (Note 4) (Figure 1) (Note 5) (Figure 3) (Figure 2) (Figure 2) (Note 6) LF13509 Series (Note 6) Switch ‘‘OFF’’ VOUT e 0V VS e 0V Switch ‘‘OFF’’ VOUT e 0V VS e 0V All Digital Inputs Grounded All Digital Inputs Grounded 22 11 4 74 79 27 28 2 Electrical Characteristics (Continued) Note 1 If the analog input voltage exceeds this limit the input current should be limited to less than 10 mA Note 2 The maximum power dissipation for these devices must be derated at elevated temperatures and is dictated by TjMAX ijA and the ambient temperature TA The maximum available power dissipation at any temperature is PD e (TjMAX b TA) ijA or the 25 C PDMAX whichever is less Note 3 These specifications apply for VS e g 15V and over the absolute maximum operating temperature range (TL s TA s TH) unless otherwise noted Note 4 Conditions applied to leakage tests insure worse case leakages Exceeding 11V on the analog input may cause an ‘‘OFF’’ channel to turn ‘‘ON’’ Note 5 Lots are sample tested to this parameter The measurement conditions of Figure 1 insure worse case transition time Note 6 ‘‘OFF’’ isolation is measured with all switches ‘‘OFF’’ and driving a source Crosstalk is measured with a pair of switches ‘‘ON’’ driving channel A and measuring channel B RL e 200 CL e 7 pF VS e 3 Vrms f e 500 kHz Note 7 Thermal Resistance ijA (Junction to Ambient) Molded DIP (N) 150 C W Cavity DIP (D) 100 C W Connection Diagrams LF13508 Dual-In-Line (N or D) or Small Outline (SO) Packages LF13509 Dual-In-Line (N or D) or Small Outline (SO) Packages TL H 5668 – 2 Order Number LF13508D See NS Package Number D16C Order Number LF13508M See NS Package Number M16A Order Number LF13508N See NS Package Number N16A Order Number LF13509D See NS Package Number D16C Order Number LF13509M See NS Package Number M16A Order Number LF13509N See NS Package Number N16A AC Test Circuits and Switching Time Waveforms TL H 5668 – 3 FIGURE 1 Transition Time 3 AC Test Circuit and Switching Time Waveforms (Continued) FIGURE 2 Enable Times TL H 5668 – 4 FIGURE 3 Break-Before-Make Transition Times and Transients TL H 5668–5 TL H 5668 – 6 TL H 5668–7 TL H 5668 – 8 Test Circuit TL H 5668–9 TL H 5668 – 10 4 Typical Performance Characteristics ‘‘ON’’ Resistance ‘‘ON’’ Resistance ‘‘ON’’ Resistance Switch Leakage Currents Switch Leakage Currents Switch Leakage Currents Switching Times (Figures 1 and 3) Enable Delay Times (Figure 2) ‘‘OFF’’ Isolation and Crosstalk Bias Currents Supply Currents Switch Capacitances TL H 5668 – 11 5 Application Hints The LF11508 series is an 8-channel analog multiplexer which allows the connection of a single load to 1 of 8 different analog inputs These multiplexers incorporate JFETs in a switch configuration which insures a constant ‘‘ON’’ resistance over the analog voltage range of the device Four TTL compatible inputs are provided a 3-bit binary decode to select a particular channel and an enable input used as a package select The switches operate with a break-beforemake action preventing the temporary connection of 2 analog inputs during switching Because these multiplexers are fabricated with the BI-FET process rather than CMOS they do not require special handling The LF11509 series is a 4-channel differential multiplexer which allows two loads to be connected to 1 of 4 different pairs of analog inputs The LF11509 series also has all the features of the LF11508 ANALOG VOLTAGE AND CURRENT The ‘‘ON’’ resistance RON of the analog switches is constant over a wide input range from positive (VCC) supply to negative (bVEE) supply The analog input should not exceed either positive or negative supply without limiting the current to less than 10 mA otherwise the multiplexer may get damaged For proper operation however the positive analog voltage should be kept equal to or less than VCC b 4V as this will increase the switch leakage in both ‘‘ON’’ and ‘‘OFF’’ state and it may also cause a false turn ‘‘ON’’ of a normally ‘‘OFF’’ switch This limit applies over the full temperature range The maximum allowable switch ‘‘ON’’ voltage (the drop across the switch in the ‘‘ON’’ condition) is g 0 4V over temperature If this number is to exceed the input current should be limited to 10 mA The ‘‘ON’’ resistance of the multiplexing switches varies slightly with analog current because they are JFETs running at 0V gate to source The JFET characteristics shown in Figure 4 indicates how RON tends to vary with current A lower RON is possible when the source voltage is negative with respect to the drain voltage because the JFET becomes enhanced Caution should be used when operating in this mode as this may forward-bias an internal transistor and cause high currents to flow in the switches Thus the drain voltage should never be greater than 0 4V positive with respect to the source voltage without limiting the drain current to less than 10 mA LEAKAGE CURRENTS Leakage currents will remain within the specified value as long as the drain and source remain within the specified analog voltage range As the switch terminals exceed the positive analog voltage range ‘‘ON’’ and ‘‘OFF’’ leakage currents increase The ‘‘ON’’ leakage increases due to an internal clamp required by the switch structure The ‘‘OFF’’ leakage increases because the gate to source reverse bias has been decreased to the point where the switch becomes active Leakage currents vary slightly with analog voltage and will approximately double for every 10 C rise in temperature SWITCHING TIMES AND TRANSIENTS These multiplexers operate with a break-before-make switch action The turn off time is much faster than the turn on time to guarantee this feature over the full range of analog input voltage and temperature Switching transients are introduced when a switch is turned ‘‘OFF’’ The amplitude of these transients may be reduced by increasing the load capacitance or decreasing the load resistance The actual charge transfer in the transient may be reduced by operating on reduced power supplies Examples of switching times and transients are shown in the typical characteristic curves The enable function switching times are specified separately from switch-to-switch transition times and may be thought of as package-to-package transition times LOGIC INPUTS AND ENABLE INPUT Switch selection in the LF11508 series is accomplished by using a 3-bit binary decode while the LF11509 series uses a 2-bit decode These binary logic inputs are compatible with both TTL and CMOS logic voltage levels The maximum positive voltage applied to these inputs may exceed VCC but should not exceed bVEE a 36V The maximum negative voltage should not be less than 4V below ground as this will cause an internal device to zener and all the switches will turn ‘‘ON’’ As shown in the schematic diagram the logic low bias current will flow until the PNP input is raised above the 3 diode reference ( 2 1V) Above this voltage the input device becomes reverse biased and the input current drops to the leakage of the reverse biased junction ( k0 1 mA) TL H 5668 – 12 FIGURE 4 JFET Characteristics 6 Typical Applications DATA ACQUISITION SYSTEM TABLE I A SIMPLIFIED SYSTEM DISCUSSION Analog multiplexers (MUX) are usually used for multi-chants(ON) nel Data Acquisition Units (DAU) Figure 5 shows a system ERROR % BITS TO 1 2 LSB in which 8 different analog inputs are sampled and converted into digital words for further processing The sample and 02 8 6 2t hold circuit is optional depending on input speed require0 05 10 7 6t ments and on A D converter speed 0 01 12 9t Parameters characterizing the system are 0 0008 16 11 8t System Channels The number of multiplexer channels Accuracy The conversion accuracy of each individual samt e CS (RON a RS) ll RIN ple with the system operating at the throughput rate Speed or Throughput Rate Number of samples second ts(OFF) is the time it takes to discharge CS within channel the system can handle a tolerable error The ‘‘OFF’’ settling time should be taken into account for bipolar inputs where its For a discussion on system structure addressing mode and effects will appear as a worse case of doubling processor interfacing see application note AN-159 of the ts(ON) A ACCURACY CONSIDERATIONS 2 Sample and Hold Influence on System Accuracy 1 Multiplexer’s Influence on System Accuracy (Figure 6) The sample and hold if used also introduces errors into a The error (E) caused by the finite ‘‘ON’’ resistthe system accuracy due to ance RON of the multiplexing switches is given  Offset voltage of sample and hold by  Droop rate in the Hold mode  TA Aperture time or time delay between the time of a digital Hold command and the actual Hold occurance 100 E(%) e where  Taq Acquisition time or time it takes to acquire an a RIN (RON a RS a DRON) 1 analog input and settle within a predetermined error band RIN e following stage input impedance  Hold step Error created during the Sample to Hold DRON e ‘‘ON’’ resistance modulation which is mode caused by an undesirable charge injected into negligible for JFET switches like the LF11508 the Hold capacitor Ch Example Let RON e 450 X DRON e 0 RS e 0 TA For more details on sample and hold errors see the e 25 C and allowable E e 0 01% which is equivalent LF198 LF298 LF398 data sheet to 1 2 LSB in a 12-bit system 3 A D Converter Influence on System Accuracy The ‘‘accuracy’’ of the A D converter is the best possible R (100 b E) system accuracy In most data acquisition systems the e ON e 4 5 MX RIN A D converter is the most expensive single component E min so its error will often dominate system error Care should be taken that MUX S H and input source errors do not Note that if temperature effects are included some exceed system error requirements when added to A D gain (or full scale) drift will occur but effects on linearity errors For instance if an 8-bit accuracy system is desired are small and an 8-bit A D converter is used the accuracy of the b Multiplexer settling time (ts) MUX and S H should be far better than 8 bits ts(ON) is the time required for the MUX output to For details on A D converter specifications see AN-156 settle within a predetermined accuracy as shown in Table I CS (Figure 6) MUX output capacitance a following stage input capacitance a any stray capacitance at this node TL H 5668 – 13 FIGURE 5 Random-Addressed Multiplexed DAU 7 FIGURE 6 8-Channel MUX Typical Applications (Continued) B SPEED CONSIDERATIONS In the system of Figure 5 with the S H omitted if n-bit accuracy is desired the change of the analog input voltage should be less than g 1 2 LSB over the A D conversion time TC In other words the analog input slew rate (rate of change of input voltage) will cause a slew-induced error and its magnitude with respect to the total system error will depend on the particular application g 1 2 LSB DVIN VFS k e Dt max TC 2n c TC where TA is the aperture time of the S H This represents an input slew rate improvement by a factor TC TA Here again the slew rate error is not affected by the acquisition time of the Sample and Hold since conversion will start after the S H has settled An important thing to notice is that the sample and hold errors will add to the total system error budget therefore the inequality of the DVIN Dt expression should become more stringent Example TC e 40 ms TA e 0 5 ms n e 8 TC TA e 80 So the use of a S H allows a speed improvement by nearly two orders of magnitude The maximum throughput rate can be calculated by 1 e Th R 8(TA a Taq a TC) max Notice that TMUX does not affect the DVIN Dt expression nor the throughput rate of the system since it may be switched and settled while the Sample and Hold is in the Hold mode This is true provided that TMUX k TA a TC C SYSTEM EXAMPLE (Figure 7) The LF398 S H with a 1000 pF hold capacitor has an acquisition time of 4 ms to 0 1% (1 4 LSB error for 8 bits) and an aperture time of less than 200 ms On the other hand after the hold command the output will settle to g 0 05 mV in 1 ms This together with the acquisition time introduces approximately a g 1 4 LSB error Allowing another 1 4 LSB error for hold step and gain non-linearity the maximum slew error (DVIN Dt) should not exceed 1 4 LSB or 1 1 DVIN 1 sc c Dt 4 256 TA where VFS is the full scale voltage of the A D Note that slew induced errors are not affected by the MUX switch time since we can let the unit settle before starting conversion Example Let TC e 40 ms (MM4357) VFS e 10V and n e8 DVIN 1mV k Dt max ms which is a very small number A 10 Vp-p sine wave of a frequency greater than 32 Hz will have higher slew rate than this The maximum throughput rate of the above 8channel system would be calculated using both the A D conversion time and the sum of MUX switch ‘‘ON’’ time and settling time i e Th R max e 1 e 3k samples sec 8(TC a TMUX) channel TMUX e TON a TS(ON) Also notice that Nyquist sampling criteria would allow each channel to have a signal bandwidth of 1 5 kHz max while the slew limit dictates a maximum frequency of 32 Hz If the input signal has a peak-to-peak voltage less than 10V the allowable maximum input frequency can be calculated by fMAX e (Slew Rate)max q Vp-p 5mV ms (which is the maximum slew rate of a 5 V peak sine wave Also notice that due to the above input slew restrictions the analog delay caused by the finite BW of the S H and the digital delay caused by the response time of the controller will be negligible The maximum throughput rate of the system is 1 e e 2800 samples sec ch Th R 8(5 a 40)10b6 max If the system speed requirements are relaxed but the A D converter is still too slow then an inexpensive S H can be built by using just a capacitor and a low cost FET input op amp as shown in Figure 8 On the other hand if the input voltage is not band-limited a low pass filter with an attenuation of 30 dB or better at 1 5 kHz should be connected in front of the MUX 1 Improving System Speed with a Sample and Hold The system speed can be improved by using the S H shown in Figure 5 This allows a much greater rate of change of VIN DVIN VFS k Dt max 2n c TA 8 Typical Applications (Continued) EOC End of Conversion SC Start Conversion FIGURE 7a Sequentially Multiplexed DAU with Sample and Hold TL H 5668 – 14 FIGURE 7b Timing Diagram 9 Typical Applications (Continued) D DOUBLING THE SYSTEM CHANNEL CAPABILITY This is done in two different ways First we can use second level multiplexing with speed benefits as shown in Figure 9 A fast 2-channel multiplexer made by the dual analog switch AM182 accepts the outputs of each 8-channel MUX LF13508 and then feeds them sequentially into an 8-bit successive approximation A D converter With this technique the throughput rate of the system can again be made independent of the LF13508 speed Looking at the timing diagram when the A D converter converts the analog value of an upper multiplexer channel we switch channels in the lower multiplexer for the next conversion This can be done provided that TMUX s TC a 1 CP The LF356 connected as unity gain buffers are used because of the low input impedance of the A D they are connected between multiplexers for speed optimization With a maximum clock frequency of 4 5 MHz Th R e 106 e 31 25k samples sec channel 16 c 2 An alternate way to increase the system channel is shown in Figure 10 where the enable pins are used to disable one MUX while the other is sampling With this method many 8channel multiplexers can be connected but the parasitic capacitance at the common output node will keep increasing and will eventually degrade the settling time ts(ON) Also the MUX speed will now affect the system throughput If for instance this method was used instead of second level multiplexing the system of Figure 9 will lose half of its speed If however speed is not the prime system requirement the approach of Figure 10 is more cost effective E DIFFERENTIAL INPUT SYSTEMS Systems operating in industrial environments may require an instrumentation amplifier to separate the desired analog signal from any common-mode signal present The LF11509 was designed to provide 4 pairs of differential input signals to the input of an instrumentation amplifier for further process and 10 1 DVIN k c e 19 5 mV ms for 10VFS Dt max 256 2ms TL H 5668 – 15  The acquisition time TA of the Sample and Hold depends upon RON IDSS of switches ZOUT of switches  IDSS j 1 5 mA ZOUT e 40 kX  VIN e 10V Ch e 1000 pF TA e 20 ms to 0 1%  Error created by charge injection during Hold mode DVE j 10 pF (14 5V b VIN) Ch FIGURE 8 Inexpensive Sample and Hold 10 Typical Applications (Continued) FIGURE 9a A Fast 16-Channel DAU with Second Level Multiplexing TL H 5668 – 16 FIGURE 9b Timing Diagram 11 Typical Applications (Continued) TL H 5668 – 17 FIGURE 10 A 16-Channel Multiplexer with Sequential Multiplexing 12 Schematic Diagrams LF13508 TL H 5668 – 19 13 Schematic Diagrams (Continued) LF13509 TL H 5668 – 20 14 Physical Dimensions inches (millimeters) Dual-In-Line Package (D) Order Number LF13508D or LF13509D NS Package D16C 16-Lead (0 150 Wide) Molded Small Outline Package JEDEC (SO) Order Number LF13508M or LF13509M NS Package Number M16A 15 LF13508 8-Channel Analog Multiplexer LF13509 4-Channel Differential Analog Multiplexer Physical Dimensions inches (millimeters) (Continued) Dual-In-Line Package (N) Order Number LF13508N or LF13509N NS Package N16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when 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