LF400AMH

LF400A LF400 Fast-Settling JFET-Input Operational Amplifier LF400A LF400 Fast-Settling JFET-Input Operational Amplifier General Description The LF400 is a fast-settling (under 400 ns to 0 01% for a 10V output step) Bi-FET operational amplifier Features include 16 MHz bandwidth 60V ms inverting slew rate low input offset voltage (0 5 mV for the LF400A at 25 C) and adjustable output current limit enabling the amplifier to drive 600X loads June 1989 Applications Y Y Y Y Y Y DAC output amplifiers High speed ramp generators Fast buffers Sample-and-holds Fast integrators Piezoelectric transducer signal conditioners Typical Connection Connection Diagram TL H 9414–1 Note Pin 4 connected to case TL H 9414–2 Top View Order Number LF400ACH LF400CH LF400AMH or LF400MH See NS Package Number H08B Simplified Schematic TL H 9414–3 BI-FETTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL H 9414 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications g 18V Supply Voltage Differential Input Voltage Input Voltage Range (Note 3) Output Short Circuit Duration (Pin 6) Power Dissipation (Note 4) H package Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering 10 sec ) ESD Susceptibility (Note 9) g 32V g 16V Continuous Operating Ratings (Notes 1 Temperature Range LF400AMH LF400MH LF400ACH LF400CH Positive Supply Voltage Negative Supply Voltage 2) TMIN s TA s TMAX b 55 C s TA s a 125 C 0 C s TA s a 70 C a 10V to a 16V b 10V to b 16V 500 mW 150 C b 65 C to a 150 C a 300 C 800V AC Electrical Characteristics (LF400ACH LF400CH) The following specifications apply for V a e a 15V and Vb e b15V unless otherwise specified Tested Limits in Boldface apply for TJ e 25 C to 95 C Design Limits in Boldface apply for TA e TMIN to TMAX other Design Limits are for TA e 25 C all other limits for TJ e 25 C LF400ACH Symbol Parameter Conditions Typical (Note 6) 365 200 16 30 60 60 23 23 0 01 10 14 27 LF400CH Units Tested Design Tested Design Typical Limit Limit Limit Limit (Note 6) (Note 7) (Note 8) (Note 7) (Note 8) 365 200 16 30 60 60 23 23 0 01 10 14 27 ts GBW SR Settling Time to 0 01% to 0 10% Minimum Gain Bandwidth Product Minimum Slew Rate See Figure 1 See Figure 1 AV e a 1 CL e 10 pF Av e a 1 CL e 10 pF AV e b1 CL e 10 pF AV e a 1 CL e 10 pF f e 1 kHz RS e 100X Broadband RS e 100X 10 Hz to 10 kHz f e 1 kHz Broadband 10 Hz to 10 kHz ns ns MHz V ms V ms Degrees nV 0Hz mV rms pA 0Hz pA rms w en Phase Margin Input Noise Voltage in Input Noise Current THD CIN Total Harmonic Distortion f e 1 kHz AV e b1 RL e 10k Input Capacitance 0 002 7 0 002 7 % pF 2 DC Electrical Characteristics (LF400ACH LF400CH) The following specifications apply for V a e a 15V and Vb e b15V unless otherwise specified Tested Limits in Boldface apply for TJ e 25 C to 95 C Design Limits in Boldface apply for TA e TMIN to TMAX other Design Limits are for TA e 25 C all other limits for TJ e 25 C LF400ACH Symbol Parameter Conditions Typical (Note 6) LF400CH Tested Design Tested Design Units Typical Limit Limit Limit Limit (Note 6) (Note 7) (Note 8) (Note 7) (Note 8) g0 5 g2 0 g 50 g 100 g2 5 g 50 g3 0 g5 0 g 100 g2 5 VOS Maximum Input Offset Voltage VCM e 0V RS e 0 RL e % TJ e 25 C TJ e 70 C mV mV pA nA pA nA X IOS IB RIN VCM AVOL Maximum Input Offset Current Maximum Input Bias Current Input Resistance Input Common-Mode Voltage Range Minimum Large Using Pin 6 Signal Voltage Using Pin 8 Gain Minimum Output Using Pin 6 Voltage Swing Using Pin 8 Output Short Circuit Current Output Resistance MIN Using Pin 6 MAX Using Pin 6 MIN Using Pin 8 Using Pin 6 Using Pin 8 VCM e 0V (Note 5) VCM e 0V (Note 5) 100 1011 b 12 to a 14 200 26 100 1011 200 26 g 11 b 12 to a 14 g 11 V V mV V mV V V mA mA mA mA X X VO e g 10V RL e 2 kX VO e g 10V RL e 600X RL e 2 kX RL e 600X Pulse Test 300 280 g 12 5 g 12 0 100 100 g 12 0 g 11 0 300 280 g 12 5 g 12 0 100 100 g 12 0 g 11 0 VO ISC 25 15 45 100 25 15 45 100 75 50 90 100 80 RO Open Loop DC Open Loop DC b 11V s VIN s a 11V a 10V s V a s a 15V b 15V s V b s b 10V VCM e 0V 75 50 100 CMRR Minimum DC Common Mode Rejection Ratio PSRR Minimum DC Power Supply Rejection Ratio Maximum Supply Current dB 100 11 0 90 13 0 100 11 0 80 13 0 dB mA IS VO e 0V RL e % 3 AC Electrical Characteristics (LF400AMH LF400MH) The following specifications apply for V a e a 15V Vb e b15V and TJ e 25 C unless otherwise specified Tested Limits in Boldface apply for TJ e b55 C to a 125 C LF400AMH Symbol Parameter Conditions Typical (Note 6) 365 200 16 30 60 60 23 23 0 01 10 14 10 27 LF400MH Units Tested Design Tested Design Typical Limit Limit Limit Limit (Note 6) (Note 7) (Note 8) (Note 7) (Note 8) 365 200 16 30 60 60 23 23 0 01 10 14 10 27 ts GBW SR Settling Time to 0 01% to 0 10% Minimum Gain Bandwidth Product Minimum Slew Rate See Figure 1 See Figure 1 AV e a 1 CL e 10 pF AV e a 1 CL e 10 pF AV e b1 CL e 10 pF AV e a 1 CL e 10 pF f e 1 kHz RS e 100X Broadband RS e 100X 10 Hz to 10 kHz f e 1 kHz Broadband 10 Hz to 10 kHz ns ns MHz MHz V ms V ms Degrees nV 0Hz mV rms pA 0Hz pA rms w en Phase Margin Input Noise Voltage in Input Noise Current THD CIN Total Harmonic Distortion f e 1 kHz AV e b1 RL e 10k Input Capacitance 0 002 7 0 002 7 % pF DC Electrical Characteristics (LF400AMH LF400MH) The following specifications apply for V a e a 15V Vb e b15V and TJ e 25 C unless otherwise specified Tested Limits in Boldface apply for TJ e b55 C to a 125 C LF400AMH Symbol Parameter Conditions Typical (Note 6) LF400MH Tested Design Tested Design Unit Typical Limit Limit Limit Limit (Note 6) (Note 7) (Note 8) (Note 7) (Note 8) g0 5 g2 0 g 50 g 100 g 15 g 50 g3 0 g5 0 g 100 g 25 VOS Maximum Input Offset Voltage VCM e 0V RS e 0 RL e % TJ e 25 C mV mV pA nA pA nA X IOS IB RIN VCM AVOL Maximum Input Offset Current Maximum Input Bias Current Input Resistance Input Common-Mode Voltage Range VCM e 0V (Note 5) VCM e 0V (Note 5) 100 1011 b 12 to a 14 200 35 100 1011 200 50 g 11 b 12 to a 14 g 11 V V mV V mV Minimum Large Using Pin 6 VO e g 10V RL e 2 kX Signal Voltage Using Pin 8 V e g 10V R e 600X O L Gain 300 280 100 100 300 280 50 50 4 DC Electrical Characteristics (LF400AMH LF400MH) The following specifications apply for V a e a 15V Vb e b15V and TJ e 25 C unless otherwise specified Tested Limits in Boldface apply for TJ e b55 C to a 125 C (Continued) LF400AMH Symbol Parameter Conditions Typical (Note 6) LF400MH Tested Design Tested Design Units Typical Limit Limit Limit Limit (Note 6) (Note 7) (Note 8) (Note 7) (Note 8) g 12 0 g 12 5 g 11 5 g 11 0 g 12 5 g 12 0 g 12 0 g 11 5 g 11 0 VO Minimum Output Using Pin 6 Voltage Swing Using Pin 8 RL e 2 kX RL e 600X Pulse Test g 12 0 V V V mA mA mA mA X X ISC Output Short Circuit Current Output Resistance 25 15 45 100 25 15 45 100 75 50 90 80 90 85 13 0 13 0 100 100 80 75 80 75 13 0 15 0 MIN Using Pin 6 MAX Using Pin 6 MIN Using Pin 8 Using Pin 6 Using Pin 8 Open Loop DC Open Loop DC b 11V s VIN s a 11V a 10V s V a s a 15V b 15V s V b s b 10V VCM e 0V RO 75 50 100 100 CMRR Minimum DC Common Mode Rejection Ratio PSRR Minimum DC Power Supply Rejection Ratio Maximum Supply Current dB dB dB dB mA mA IS VO e 0V RL e % 11 0 11 0 Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are with respect to ground Note 3 Unless otherwise specified the Absolute Minimum Input Voltage is equal to the negative power supply voltage Note 4 The maximum power dissipation must be derated at elevated temperatures as is dictated by TJMAX iJA and the ambient temperature TA iJA for the LF400H is 150 C W in free air so a heat sink will generally be required when TA is greater than about 70 C iJC for the LF400H is 17 C W which dictates the use of a heat sink with iCA less than about 35 C W when TA e a 125 C Note 5 The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature TJ Due to limited production test time input bias currents are measured at TJ e 25 C In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation PD Use of a heat sink is recommended when input bias current must be minimized Note 6 Typicals represent the most likely parametric norm Note 7 Guaranteed to National’s AOQL (Average Outgoing Quality Level) Note 8 Guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels Note 9 Human body model 100 pF discharged through a 1500X resistor 5 Typical Performance Characteristics Inverter Settling Time Bode Plot Gain Bandwidth vs Temperature Slew Rate vs Temperature Undistorted Output Voltage Swing Undistorted Output Voltage Swing Distortion vs Frequency Distortion vs Frequency Equivalent Input Noise Voltage AC Common-Mode Rejection AC Power Supply Rejection Common-Mode Input Voltage Range TL H 9414–10 6 Typical Performance Characteristics Output Voltage Swing vs Supply Voltage (Continued) Input Bias Current vs Temperature DC Gain vs Supply Voltage Power Supply Current vs Power Supply Voltage TL H 9414–11 Settling Time Positive Output Swing Settling Time Negative Output Swing TL H 9414–12 TL H 9414–13 Step Response TL H 9414–14 7 Typical Performance Characteristics Step Response (Continued) Voltage Transfer Characteristic TL H 9414–15 TL H 9414–16 Voltage Transfer Characteristic TL H 9414–17 TL H 9414–18 8 Typical Performance Characteristics Common (Continued) Mode Voltage Transfer Characteristic TL H 9414–19 TL H 9414–20 Application Hints The LF400 is a high-speed low input bias current Bi-FET operational amplifier capable of settling to 0 01% of a 10V output swing in less than 400 ns The rugged JFET inputs allow differential input voltages as high as 32V without a large increase in input current However the inputs should never be driven to voltages lower than the negative supply as this can result in input currents large enough to damage the device To prevent this from occurring when power is first applied always turn the positive and negative power supplies on simultaneously or turn the negative supply on first Exceeding the common-mode input range will not damage the device as long as the Absolute Maximum Ratings are not violated but it will result in a high output voltage Latching will not occur however and when the offending signal is removed the LF400 will recover quickly The nominal power supply voltage is g 15V but the LF400 will operate satisfactorily from g 10V to g 16V The LF400 is functional down to g 5V but performance will be degraded (See Typical Performance curves ) Settling Time Considerations The settling performance of any high-speed operational amplifier is highly dependent on the external components and circuit board layout Capacitance between the amplifier summing junction and ground affects the closed-loop transfer function and should be minimized The compensation capacitor CC between the output and the inverting input should be carefully chosen to counteract the effect of the input capacitance Since input capacitance is made up of several stray capacitances that are difficult to predict the compensation capacitor will generally have to be determined empirically for best settling time A good starting point is around 10 pF for AV e b1 Settling time may be verified using a circuit similar to the one in Figure 1 The LF400 is connected for inverting operation and the output voltage is summed with the input voltage step When the LF400’s output voltage is equal to the input voltage the voltage on the gate of Q1 will be zero Any voltage appearing at this point will represent an error The FET source follower output is observed on an oscilloscope and the settling time is equal to the time required for the error signal displayed on the oscilloscope to decay to less than one-half the necessary accuracy (see oscilloscope photos of ‘‘Settling Time Positive Output Swing’’ and ‘‘Settling Time Negative Output Swing’’) For a 10V input signal settling time to 0 01% (1 mV) will occur when the displayed error is less than mV Since settling time is strongly dependent on slew rate settling will be faster for smaller signal swings The LF400’s inverting slew rate is faster than its non-inverting slew rate so settling will be faster for inverting applications as well It is important to note that the oscilloscope input amplifier will be overdriven during a settling time measurement so the oscilloscope must be capable of recovering from overdrive very quickly Very few oscilloscopes are suitable for this sort of measurement The signal generator used for set- 9 Application Hints (Continued) CL s 49 pF TL H 9414–21 FIGURE 1 Simplified Settling Time Test Circuit (see Text) tling time testing must be able to drive 50X with a very clean g 5V square wave For more information on measuring settling time see Application Note AN-428 Output Compensation When operating at very low temperatures a compensation network should be added to the LF400’s output The 100X 22 pF network shown on the first page of this data sheet should be used when the junction temperature might reach 25 C (roughly 0 C ambient when the LF400 is ‘‘warmed up’’) In applications where the device will be operating with a junction temperature near 0 C the output RLC network in Figure 1 should be used This network will provide a small (about 20 ns) improvement in settling time at higher temperatures as well Supply Bypassing Power supply bypassing is extremely important for good high-speed performance Ideally multiple bypass capacitors as in Figure 2 should be used A 10 mF tantalum a 2 2 mF ceramic and a 0 47 mF ceramic work well All bypass capacitor leads should be very short For best results the ground leads of the capacitors should be separated to reduce the inductance to ground A ground plane layout approach will give the best results For simplicity bypass capacitors have been omitted from some of the schematics in this data sheet but they should always be used Output Drive and Current Limit The LF400 can drive heavier resistive loads than most operational amplifiers The output at pin 6 is internally currentlimited when the voltage drop across the 25X output resistor reaches about 0 55V (IOUT e 22 mA) When more output current is needed pin 8 provides a means of increasing the maximum output current up to about 100 mA A resistor may be connected from pin 8 to pin 6 paralleling the internal sense resistor and increasing the current limit threshold (Figure 3 ) Pins 6 and 8 may be shorted together to completely bypass the current limiting circuit To avoid damaging the LF400 observe the power dissipation limitations mentioned in the Absolute Maximum Ratings and in Note 4 The effective load impedance (including feedback resistance) should be kept above 500X for fastest settling Load capacitance should also be minimized if good settling time is to be optimized Large feedback resistors will make the circuit more susceptible to stray capacitance so in highspeed applications keep the feedback resistors in the 1 kX to 2 kX range wherever practical Avoid the use of inductive feedback resistors (some wirewounds for example) as these will degrade settling time ILimit 0 55V Rx 25X TL H 9414–23 FIGURE 3 Increasing the current limit using pin 8 Current limit is now determined by RX in parallel with the internal 25X sense resistor Vos Adjustment Offset voltage can be nulled using a 27k resistor and a 10k potentiometer connected to pins 1 and 5 as shown in Figure 4a Bypassing the Vos adjust pins with 0 1 mF capacitors will help to avoid noise pickup When not used for offset adjustment pins 1 and 5 can often be left open but to minimize the possibility of noise pickup the unused Vos trim pins should be connected to ground or V b TL H 9414–22 FIGURE 2 Power Supply Bypassing (see Text) 10 Application Hints (Continued) In very critical applications where a manual adjustment is impractical the LMC669 Auto Zero circuit may be used to reduce the effective input offset voltage to around 5 mV as in Figure 4b The LF400 will perform better than slower amplifiers in an auto zero loop because its fast settling capability keeps its summing node voltage more stable Therefore the LMC669 is able to more accurately sample the summing node voltage before making an offset correction Input Bias Current TL H 9414–24 FIGURE 4a Vos Adjust Circuit The JFET input stage of the LF400 ensures low input bias current (200 pA maximum) when the die is at room temperature but this current approximately doubles for every 10 C increase in temperature In applications that demand the lowest possible input bias current a heat sink should be used with the LF400 ‘‘Press on’’ heat sinks from manufacturers such as Thermalloy and AAVID can reduce junction temperature by roughly 10 C to 40 C Typical Applications High-Speed DAC with Voltage Output TL H 9414–26 TL H 9414–25 FIGURE 4b Automatic Offset Adjustment Using LMC669 11 LF400A LF400 Fast-Settling JFET-Input Operational Amplifier Physical Dimensions inches (millimeters) Lit 106144 Order Number LF400ACH LF400CH LF400AMH or LF400MH NS Package Number H08B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without 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