LM3481

LM3481 High Efficiency Low-Side N-Channel Controller for Switching Regulators November 16, 2007 LM3481 High Efficiency Low-Side N-Channel Controller for Switching Regulators General Description The LM3481 is a versatile Low-Side N-FET high performance controller for switching regulators. It is suitable for use in topologies requiring a low-side FET, such as boost, flyback, SEPIC, etc. The LM3481 can be operated at extremely high switching frequencies in order to reduce the overall solution size. The switching frequency of the LM3481 can be adjusted to any value between 100 kHz and 1 MHz by using a single external resistor or by synchronizing it to an external clock. Current mode control provides superior bandwidth and transient response in addition to cycle-by-cycle current limiting. Current limit can be programmed with a single external resistor. The LM3481 has built in protection features such as thermal shutdown, short-circuit protection and over voltage protection. Power saving shutdown mode reduces the total supply current to 5µA and allows power supply sequencing. Internal soft-start limits the inrush current at start-up. Key Specifications ■ Wide supply voltage range of 2.97V to 48V ■ 100 kHz to 1 MHz Adjustable and Synchronizable clock frequency ■ ±1.5% (over temperature) internal reference ■ 10 µA shutdown current (over temperature) Features ■ ■ ■ ■ ■ ■ ■ ■ 10-lead MSOP package Internal push-pull driver with 1A peak current capability Current limit and thermal shutdown Frequency compensation optimized with a capacitor and a resistor Internal softstart Current Mode Operation Adjustable Undervoltage Lockout with Hysteresis Pulse Skipping at Light Loads Applications ■ Distributed Power Systems ■ Notebook, PDA, Digital Camera, and other Portable Applications ■ Offline Power Supplies ■ Set-Top Boxes Typical Application Circuit 201365a5 Typical SEPIC Converter © 2007 National Semiconductor Corporation 201365 www.national.com LM3481 Connection Diagram 20136502 10-Lead Mini SOIC Package (MSOP-10 Package) Package Marking and Ordering Information Order Number LM3481MM LM3481MMX Package Type MSOP-10 MSOP-10 Package Marking SJPB SJPB Supplied As: 1000 units on Tape and Reel 3500 units on Tape and Reel Pin Description Pin Name ISEN UVLO Pin Number 1 2 Description Current sense input pin. Voltage generated across an external sense resistor is fed into this pin. Under voltage lockout pin. A resistor divider from VIN to ground is connected to the UVLO pin. The ratio of these resistances determine the input voltage which allows switching and the hysteresis to disable switching. Compensation pin. A resistor and capacitor combination connected to this pin provides compensation for the control loop. Feedback pin. Inverting input of the error amplifier. Analog ground pin. Internal bias circuitry reference. Should be connected to PGND at a single point. Frequency adjust, synchronization, and shutdown pin. A resistor connected from this pin to ground sets the oscillator frequency. An external clock signal at this pin will synchronize the controller to the frequency of the clock. A high level on this pin for ≥ 30 µs will turn the device off and the device will then draw 5 µA from the supply typically. PGND DR VCC VIN 7 8 9 10 Power ground pin. External power circuitry reference. Should be connected to AGND at a single point. Drive pin of the IC. The gate of the external MOSFET should be connected to this pin. Driver supply voltage pin. Typically a capacitor is tied from the VCC pin to ground. Power supply input pin. COMP FB AGND FA/SYNC/SD 3 4 5 6 www.national.com 2 LM3481 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN pin Voltage FB Pin Voltage FA/SYNC/SD Pin Voltage COMP Pin Voltage UVLO Pin Voltage VCC Pin Voltage DR Pin Voltage ISEN Pin Voltage Peak Driver Output Current Power Dissipation -0.4V to 50V -0.4V to 6V -0.4V to 6V -0.4V to 6V -0.4V to 6V -0.4V to 6V -0.4V to 6V –0.4V to 600 mV 1.0A Internally Limited Storage Temperature Range Junction Temperature ESD Susceptibilty  Human Body Model (Note 2) Lead Temperature MM Package Vapor Phase (60 sec.) Infared (15 sec.) −65°C to +150°C +150°C 2 kV 215°C 220°C (Note 1) 2.97V to 48V −40°C to +125°C 100 kHz to 1 MHz Operating Ratings Supply Voltage Junction Temperature Range Switching Frequency Range Electrical Characteristics VIN=12V, RFA=40 kΩ unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TJ = 25°C. Limits appearing in boldface type apply over the full Operating Temperature Range (-40°C to 125°C). Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. (Notes 3, 4) Symbol VFB ΔVLINE ΔVLOAD VUVLOSEN IUVLO VUVLOSD ICOMP VCOMP fnom Vsync-HI Nominal Switching Frequency Threshold for Synchronization on FA/SYNC/SD pin Threshold for Synchronization on FA/SYNC/SD pin Driver Switch On Resistance (top) Driver Switch On Resistance (bottom) Maximum Drive Voltage Swing(Note 6) Maximum Duty Cycle Minimum On Time Supply Current (switching) (Note 8) Quiescent Current in Shutdown Mode VFA/SYNC/SD = 3V(Note 9), VIN = 12V VFA/SYNC/SD = 3V(Note 9), VIN = 5V Parameter Feedback Voltage Feedback Voltage Line Regulation Output Voltage Load Regulation Undervoltage Lockout Reference Voltage UVLO Source Current UVLO Shutdown Voltage COMP pin Current Sink VFB = 0V VFB = 1.275V RFA = 40 kΩ Synchronization Voltage Rising Synchronization Voltage Falling IDR = 0.2A, VIN= 5V IDR = 0.2A VIN < 6V VIN ≥ 6V 406 Conditions VCOMP = 1.4V, 2.97 ≤ VIN ≤ 48V 2.97 ≤ VIN ≤ 48V IEAO Source/Sink VUVLO Ramping Down Enabled 1.345 3 Min 1.256 Typical 1.275 0.003 ±0.5 1.430 5 0.7 640 1 475 550 1.517 6 Max 1.294 Units V %/V %/V V µA V µA V kHz 1.4 V Vsync-LOW RDS1 (ON) RDS2 (ON) VDR (max) Dmax tmin (on) ISUPPLY 0.7 V Ω Ω V % ns 5.0 15 µA 10 mA 4 2 VIN 6 85 250 3.7 9 5 IQ 3 www.national.com LM3481 Symbol VSENSE VSC VSL VOVP VOVP(HYS) Gm AVOL Parameter Current Sense Threshold Voltage Over Load Current Limit Sense Voltage Internal Compensation Ramp Voltage Conditions Min 100 157 Typical 160 220 90 Max 190 275 Units mV mV mV Output Over-voltage Protection (with respect to VCOMP = 1.4V feedback voltage) (Note 7) Output Over-Voltage Protection Hysteresis Error Amplifier Transconductance Error Amplifier Voltage Gain Error Amplifier Output Current (Source/ Sink) VCOMP = 1.4V VCOMP = 1.4V VCOMP = 1.4V IEAO = 100 µA (Source/Sink) Source, VCOMP = 1.4V, VFB = 1.1V Sink, VCOMP = 1.4V, VFB = 1.4V Upper Limit VFB = 0V COMP Pin Floating Lower Limit VFB = 1.4V VFB = 1.2V, COMP Pin Floating Cgs = 3000 pf, VDR = 0V to 3V Cgs = 3000 pf, VDR = 3V to 0V 26 85 135 mV 28 216 35 475 31 2.45 70 450 60 640 65 2.70 106 690 66 837 100 2.93 mV µmho V/V µA µA V IEAO VEAO Error Amplifier Output Voltage Swing 0.32 0.60 15 25 25 1.31 0.90 V ms ns ns tSS tr tf VSD ISD TSD Tsh θJA Internal Soft-Start Delay Drive Pin Rise Time Drive Pin Fall Time Shutdown signal threshold Output = High (Shutdown) (Note 5) FA/SYNC/SD pin Output = Low (Enable) Shutdown Pin Current FA/SYNC/SD pin Thermal Shutdown Thermal Shutdown Hysteresis Thermal Resistance MM Package VSD = 5V VSD = 0V 1.40 V V µA °C °C °C/W 0.40 0.68 −1 20 165 10 200 www.national.com 4 LM3481 Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 3: All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature limits are 100% tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Note 4: Typical numbers are at 25°C and represent the most likely norm. Note 5: The FA/SYNC/SD pin should be pulled to VIN through a resistor to turn the regulator off. The voltage on the FA/SYNC/SD pin must be above the max limit for the Output = High longer than 30 µs to keep the regulator off and must be below the minimum limit for Output = Low to keep the regulator on. Note 6: The drive pin voltage, VDR, is equal to the input voltage when input voltage is less than 6V. VDR is equal to 6V when the input voltage is greater than or equal to 6V. Note 7: The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the feedback voltage. The over-voltage threshold can be calculated by adding the feedback voltage (VFB) to the over-voltage protection specification. Note 8: For this test, the FA/SYNC/SD Pin is pulled to ground using a 40 kΩ resistor . Note 9: For this test, the FA/SYNC/SD Pin is pulled to 3V using a 40 kΩ resistor. Typical Performance Characteristics Comp Pin Voltage vs. Load Current Unless otherwise specified, VIN = 12V, TJ = 25°C. Switching Frequency vs. RFA 20136546 20136547 Efficiency vs. Load Current (3.3VIN and 12VOUT) Efficiency vs. Load Current (5VIN and 12VOUT) 20136548 20136549 5 www.national.com LM3481 Efficiency vs. Load Current (9VIN and 12VOUT) Frequency vs. Temperature 20136550 201365a7 COMP Pin Source Current vs. Temperature ISupply vs. Input Voltage (Non-Switching) 20136552 20136553 ISupply vs. Input Voltage (Switching) Shutdown Threshold Hysteresis vs. Temperature 20136554 20136556 www.national.com 6 LM3481 Drive Voltage vs. Input Voltage Short Circuit Protection vs. VIN 20136557 20136558 Current Sense Threshold vs. Input Voltage Compensation Ramp Amplitude vs. Input Voltage 20136559 20136560 Minimum On-Time vs. Temperature 201365a8 7 www.national.com LM3481 Functional Block Diagram 20136506 Functional Description The LM3481 uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. In a typical application circuit, the peak current through the external MOSFET is sensed through an external sense resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the error amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM comparator. At the start of any switching cycle, the oscillator sets the RS latch using the SET/Blank-out and switch logic blocks. This forces a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the RS latch is reset and the external MOSFET turns off. The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 1. These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a short duration after the latch is set. This duration, called the blank-out time, is typically 250 ns and is specified as tmin (on) in the electrical characteristics section. Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external MOSFET is on during the blank-out time is more than what is delivered to the load. An over-voltage comparator inside the LM3481 prevents the output voltage from rising under these conditions by sensing the feedback (FB pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to the nominal value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency. www.national.com 8 LM3481 20136507 FIGURE 1. Basic Operation of the PWM comparator OVER VOLTAGE PROTECTION The LM3481 has over voltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (FB). If at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See the electrical characteristics section for limits on VFB and VOVP. OVP will cause the drive pin (DR) to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage will drop. The LM3481 will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)). See the electrical characteristics section for limits on VOVP(HYS). The internal bias of the LM3481 comes from either the internal bias voltage generator as shown in the block diagram or directly from the voltage at the VIN pin. At input voltages lower than 6V the internal IC bias is the input voltage and at voltages above 6V the internal bias voltage generator of the LM3481 provides the bias. SLOPE COMPENSATION RAMP The LM3481 uses a current mode control scheme. The main advantages of current mode control are inherent cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is easy to parallel power stages using current mode control since current sharing is automatic. However there is a natural instability that will occur for duty cycles, D, greater than 50% if additional slope compensation is not addressed as described below. The current mode control scheme samples the inductor current, IL, and compares the sampled signal, Vsamp, to a internally generated control signal, Vc. The current sense resistor, RSEN, as shown in Figure 5, converts the sampled inductor current, IL, to the voltage signal, Vsamp, that is proportional to IL such that: Vsamp = IL x RSEN The rising and falling slopes, M1 and −M2 respectively, of Vsamp are also proportional to the inductor current rising and falling slopes, Mon and −Moff respectively. Where Mon is the inductor slope during the switch on-time and −Moff is the inductor slope during the switch off-time and are related to M1 and −M2 by: M1 = Mon x RSEN −M2 = −Moff x RSEN For the boost topology: Mon = VIN / L −Moff = (VIN − VOUT) / L M1 = [VIN / L] x RSEN −M2 = [(VIN − VOUT) / L] x RSEN M2 = [(VOUT − VIN) / L] x RSEN Current mode control has an inherent instability for duty cycles greater than 50%, as shown in Figure 2, where the control signal slope, MC, equals zero. In Figure 2, a small increase in the load current causes the sampled signal to increase by ΔVsamp0. The effect of this load change, ΔVsamp1, at the end of the first switching cycle is : From the above equation, when D > 0.5, ΔVsamp1 will be greater than ΔVsamp0. In other words, the disturbance is divergent. So a very small perturbation in the load will cause the disturbance to increase. To ensure that the perturbed signal converges we must maintain: 9 www.national.com LM3481 20136509 FIGURE 2. Sub-Harmonic Oscillation for D>0.5 20136511 FIGURE 3. Compensation Ramp Avoids Sub-Harmonic Oscillation To prevent the sub-harmonic oscillations, a compensation ramp is added to the control signal, as shown in Figure 3. With the compensation ramp, ΔVsamp1 and the convergence criteria are expressed by, increases the amplitude of the compensation ramp as shown in Figure 4. 201365a1 The compensation ramp has been added internally in the LM3481. The slope of this compensation ramp has been selected to satisfy most applications, and it's value depends on the switching frequency. This slope can be calculated using the formula: MC = VSL x fS In the above equation, VSL is the amplitude of the internal compensation ramp and fS is the controller's switching frequency. Limits for VSL have been specified in the electrical characteristics section. In order to provide the user additional flexibility, a patented scheme has been implemented inside the IC to increase the slope of the compensation ramp externally, if the need arises. Adding a single external resistor, RSL(as shown in Figure 5) FIGURE 4. Additional Slope Compensation Added Using External Resistor RSL Where, ΔVSL = K x RSL K = 40 µA typically and changes slightly as the switching frequency changes. Figure 6 shows the effect the current K has on ΔVSLand different values of RSL as the switching frequency changes. A more general equation for the slope compensation ramp, MC, is shown below to include ΔVSL caused by the resistor RSL. MC = (VSL + ΔVSL) x fS www.national.com 10 LM3481 It is good design practice to only add as much slope compensation as needed to avoid subharmonic oscillation. Additional slope compensation minimizes the influence of the sensed current in the control loop. With very large slope compensation the control loop characteristics are similar to a voltage mode regulator which compares the error voltage to a saw tooth waveform rather than the inductor current. FREQUENCY ADJUST/SYNCHRONIZATION/SHUTDOWN The switching frequency of the LM3481 can be adjusted between 100 kHz and 1 MHz using a single external resistor. This resistor must be connected between the FA/SYNC/SD pin and ground, as shown in Figure 7. Please refer to the typical performance characteristics to determine the value of the resistor required for a desired switching frequency. The following equation can also be used to estimate the frequency adjust resistor. Where fS is in kHz and RFA in kΩ. 20136513 FIGURE 5. Increasing the Slope of the Compensation Ramp The LM3481 can be synchronized to an external clock. The external clock must be connected between the FA/SYNC/SD pin and ground, as shown in Figure 8. The frequency adjust resistor may remain connected while synchronizing a signal, therefore if there is a loss of signal, the switching frequency will be set by the frequency adjust resistor. It is also necessary to have the width of the synchronization pulse narrower than the duty cycle of the converter and to have the synchronization pulse width ≥ 300 ns. The FA/SYNC/SD pin also functions as a shutdown pin. If a high signal (refer to the electrical characteristics section for definition of high signal) appears on the FA/SYNC/SD pin, the LM3481 stops switching and goes into a low current mode. The total supply current of the IC reduces to 5 µA, typically, under these conditions. Figure 9 and Figure 10 shows an implementation of a shutdown function when operating in frequency adjust mode and synchronization mode respectively. In frequency adjust mode, connecting the FA/SYNC/SD pin to ground forces the clock to run at a certain frequency. Pulling this pin high shuts down the IC. In frequency adjust or synchronization mode, a high signal for more than 30 µs shuts down the IC. 20136551 FIGURE 6. ΔVSL vs RSL 11 www.national.com LM3481 20136514 FIGURE 7. Frequency Adjust 20136515 FIGURE 8. Frequency Synchronization 20136516 FIGURE 9. Shutdown Operation in Frequency Adjust Mode 20136517 FIGURE 10. Shutdown Operation in Synchronization Mode www.national.com 12 LM3481 Under Voltage Lockout (UVLO) Pin The UVLO pin provides user programmable enable and shutdown thresholds. The UVLO pin is compared to an internal reference of 1.43V (typical), and a resistor divider programs the enable threshold, VEN. When the IC is enabled, a 5 μA current is sourced out of the UVLO pin, which effectively causes a hysteresis, and the UVLO shutdown threshold, VSH, is now lower than the enable threshold. Setting these thresholds requires two resistors connected from the VIN pin to the UVLO pin and from the UVLO pin to GND (see Figure 11). Select the desired enable, VEN, and UVLO shutdown, VSH, threshold voltages and use the following equations to determine the resistance values: If the UVLO pin function is not desired, select R8 and R7 of equal magnitude greater than 100 kΩ. This will allow VIN to be in control of the UVLO thresholds. The UVLO pin may also be used to implement the enable/disable function. If a signal pulls the UVLO pin below the 1.43V (typical) threshold, the converter will be disabled. Short Circuit Protection When the voltage across the sense resistor (measured on the ISEN Pin) exceeds 220 mV, short-circuit current limit gets activated. A comparator inside the LM3481 reduces the switching frequency by a factor of 8 and maintains this condition until the short is removed. 20136596 FIGURE 11. UVLO Pin Resistor Divider Typical Applications The LM3481 may be operated in either continuous or discontinuous conduction mode. The following applications are designed for continuous conduction operation. This mode of operation has higher efficiency and lower EMI characteristics than the discontinuous mode. BOOST CONVERTER The most common topology for the LM3481 is the boost or step-up topology. The boost converter converts a low input voltage into a higher output voltage. The basic configuration for a boost regulator is shown in Figure 12. In continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator operates in two cycles. In the first cycle of operation, MOSFET Q is turned on and energy is stored in the inductor. During this cycle, diode D1 is reverse biased and load current is supplied by the output capacitor, COUT. In the second cycle, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The output voltage is defined as: (ignoring the voltage drop across the MOSFET and the diode), or where D is the duty cycle of the switch, VD1 is the forward voltage drop of the diode, and VQ is the drop across the MOSFET when it is on. The following sections describe selection of components for a boost converter. 13 www.national.com LM3481 20136522 FIGURE 12. Simplified Boost Converter Diagram (a) First cycle of operation. (b) Second cycle of operation POWER INDUCTOR SELECTION The inductor is one of the two energy storage elements in a boost converter. Figure 13 shows how the inductor current varies during a switching cycle. The current through an inductor is quantified as: the converter will operate in discontinuous conduction mode. If ΔiL is smaller than IL, the inductor current will stay above zero and the converter will operate in continuous conduction mode. All the analysis in this datasheet assumes operation in continuous conduction mode. To operate in continuous conduction mode, the following conditions must be met: IL > ΔiL Choose the minimum IOUT to determine the minimum L. A common choice is to set (2 x ΔiL) to 30% of IL. Choosing an appropriate core size for the inductor involves calculating the average and peak currents expected through the inductor. In a boost converter, IL_peak = IL(max) + ΔiL(max) 20136524 FIGURE 13. a. Inductor current b. Diode current c. Switch current If VL(t) is constant, diL(t)/dt must be constant. Hence, for a given input voltage and output voltage, the current in the inductor changes at a constant rate. The important quantities in determining a proper inductance value are IL (the average inductor current) and ΔiL (the inductor current ripple difference between the peak inductor current and the average inductor current). If ΔiL is larger than IL, the inductor current will drop to zero for a portion of the cycle and www.national.com 14 A core size with ratings higher than these values should be chosen. If the core is not properly rated, saturation will dramatically reduce overall efficiency. The LM3481 can be set to switch at very high frequencies. When the switching frequency is high, the converter can operate with very small inductor values. With a small inductor value, the peak inductor current can be extremely higher than the output currents, especially under light load conditions. The LM3481 senses the peak current through the switch. The peak current through the switch is the same as the peak current calculated above. LM3481 PROGRAMMING THE OUTPUT VOLTAGE AND OUTPUT CURRENT The output voltage can be programmed using a resistor divider between the output and the feedback pins, as shown in Figure 14. The resistors are selected such that the voltage at the feedback pin is 1.275V. RF1 and RF2 can be selected using the equation, Isw(peak) x RSEN = VSENSE The peak current through the switch is equal to the peak inductor current. Isw(peak) = IL(max) + ΔiL Therefore for a boost converter Combining the two equations yields an expression for RSEN A 100 pF capacitor may be connected between the feedback and ground pins to reduce noise. The maximum amount of current that can be delivered at the output can be controlled by the sense resistor, RSEN. Current limit occurs when the voltage that is generated across the sense resistor equals the current sense threshold voltage, VSENSE. Limits for VSENSE have been specified in the electrical characteristics section. This can be expressed as: Evaluate RSEN at the maximum and minimum VIN values and choose the smallest RSEN calculated. 20136520 FIGURE 14. Adjusting the Output Voltage CURRENT LIMIT WITH ADDITIONAL SLOPE COMPENSATION If an external slope compensation resistor is used (see Figure 5) the internal control signal will be modified and this will have an effect on the current limit. If RSL is used, then this will add to the existing slope compensation. The command voltage, VCS, will then be given by: VCS = VSENSE − ΔVSL Where VSENSE is a defined parameter in the electrical characteristics section and ΔVSL is the additional slope compensation generated as discussed in the Slope Compensation Ramp section. This changes the equation for RSEN to: Note that since ΔVSL = RSL x K as defined earlier, RSLcan be used to provide an additional method for setting the current limit. In some designs RSL can also be used to help filter noise to keep the ISEN pin quiet. POWER DIODE SELECTION Observation of the boost converter circuit shows that the average current through the diode is the average load current, and the peak current through the diode is the peak current through the inductor. The diode should be rated to handle more than the inductor peak current. The peak diode current can be calculated using the formula: ID(Peak) = [IOUT/ (1−D)] + ΔiL In the above equation, IOUT is the output current and ΔiL has been defined in Figure 13. The peak reverse voltage for a boost converter is equal to the regulator output voltage. The diode must be capable of handling this peak reverse voltage. To improve efficiency, a low forward drop Schottky diode is recommended. 15 www.national.com LM3481 POWER MOSFET SELECTION The drive pin, DR, of the LM3481 must be connected to the gate of an external MOSFET. In a boost topology, the drain of the external N-Channel MOSFET is connected to the inductor and the source is connected to the ground. The drive pin voltage, VDR, depends on the input voltage (see typical performance characteristics). In most applications, a logic level MOSFET can be used. For very low input voltages, a sub-logic level MOSFET should be used. The selected MOSFET directly controls the efficiency. The critical parameters for selection of a MOSFET are: 1. Minimum threshold voltage, VTH(MIN) 2. On-resistance, RDS(ON) 3. Total gate charge, Qg 4. Reverse transfer capacitance, CRSS 5. Maximum drain to source voltage, VDS(MAX) The off-state voltage of the MOSFET is approximately equal to the output voltage. VDS(MAX) of the MOSFET must be greater than the output voltage. The power losses in the MOSFET can be categorized into conduction losses and ac switching or transition losses. RDS(ON) is needed to estimate the conduction losses. The conduction loss, PCOND, is the I2R loss across the MOSFET. The maximum conduction loss is given by: boost application, low values can cause impedance interactions. Therefore a good quality capacitor should be chosen in the range of 100 µF to 200 µF. If a value lower than 100 µF is used, then problems with impedance interactions or switching noise can affect the LM3481. To improve performance, especially with VIN below 8V, it is recommended to use a 20Ω resistor at the input to provide a RC filter. This resistor is placed in series with the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 15). A 0.1 µF or 1 µF ceramic capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side of the resistor with the input power supply. 20136593 FIGURE 15. Reducing IC Input Noise OUTPUT CAPACITOR SELECTION The output capacitor in a boost converter provides all the output current when the inductor is charging. As a result it sees very large ripple currents. The output capacitor should be capable of handling the maximum rms current. The rms current in the output capacitor is: where DMAX is the maximum duty cycle. Where At high switching frequencies the switching losses may be the largest portion of the total losses. The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation. Often, the individual MOSFET datasheet does not give enough information to yield a useful result. The following formulas give a rough idea how the switching losses are calculated: and D, the duty cycle is equal to (VOUT − VIN)/VOUT. The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the output. LAYOUT GUIDELINES Good board layout is critical for switching controllers such as the LM3481. First the ground plane area must be sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with the parasitic trace inductance generates unwanted Ldi/ dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current mode devices can be easily effected by switching noise. This noise can cause duty cycle jitter which leads to increased spectral noise. Although the LM3481 has 250 ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time. 16 INPUT CAPACITOR SELECTION Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous and triangular, as shown in Figure 13. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the input capacitor gets smaller, the input ripple goes up. The rms current in the input capacitor is given by: The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical in a www.national.com LM3481 The most important layout rule is to keep the AC current loops as small as possible. Figure 16 shows the current flow of a boost converter. The top schematic shows a dotted line which represents the current flow during on-state and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents we refer to as AC currents. They are the most critical ones since current is changing in very short time periods. The dotted lined traces of the bottom schematic are the once to make as short as possible. The PGND and AGND pins have to be connected to the same ground very close to the IC. To avoid ground loop currents attach all the grounds of the system only at one point. A ceramic input capacitor should be connected as close as possible to the Vin pin and grounded close to the GND pin. For a layout example please see Application Note 1204. For more information about layout in switch mode power supplies please refer to Application Note 1229. COMPENSATION For detailed explanation on how to select the right compensation components to attach to the compensation pin for a boost topology please see Application Note 1286. When calculating the Error Amplifier DC gain, AEA, ROUT = 152 kΩ for the LM3481. 20136597 FIGURE 16. Current Flow In A Boost Application 17 www.national.com LM3481 Designing SEPIC Using LM3481 Since the LM3481 controls a low-side N-Channel MOSFET, it can also be used in SEPIC (Single Ended Primary Inductance Converter) applications. An example of SEPIC using the LM3481 is shown in Figure 17. As shown in Figure 17, the output voltage can be higher or lower than the input voltage. The SEPIC uses two inductors to step-up or step-down the input voltage. The inductors L1 and L2 can be two discrete inductors or two windings of a coupled transformer since equal voltages are applied across the inductor throughout the switching cycle. Using two discrete inductors allows use of catalog magnetics, as opposed to a custom transformer. The input ripple can be reduced along with size by using the coupled windings of transformer for L1 and L2. Due to the presence of the inductor L1 at the input, the SEPIC inherits all the benefits of a boost converter. One main advantage of SEPIC over a boost converter is the inherent input to output isolation. The capacitor CS isolates the input from the output and provides protection against shorted or malfunctioning load. Hence, the SEPIC is useful for replacing boost circuits when true shutdown is required. This means that the output voltage falls to 0V when the switch is turned off. In a boost converter, the output can only fall to the input voltage minus a diode drop. The duty cycle of a SEPIC is given by: (MIN), the on-resistance, RDS(ON), the total gate charge, Qg, the reverse transfer capacitance, CRSS, and the maximum drain to source voltage, VDS(MAX). The peak switch voltage in a SEPIC is given by: VSW(PEAK) = VIN + VOUT + VDIODE The selected MOSFET should satisfy the condition: VDS(MAX) > VSW(PEAK) The peak switch current is given by: Where ΔIL1 and ΔIL2 are the peak-to-peak inductor ripple currents of inductors L1 and L2 respectively. The rms current through the switch is given by: POWER DIODE SELECTION The Power diode must be selected to handle the peak current and the peak reverse voltage. In a SEPIC, the diode peak current is the same as the switch peak current. The off-state voltage or peak reverse voltage of the diode is VIN + VOUT. Similar to the boost converter, the average diode current is equal to the output current. Schottky diodes are recommended. In the above equation, VQ is the on-state voltage of the MOSFET, Q1, and VDIODE is the forward voltage drop of the diode. POWER MOSFET SELECTION As in a boost converter, the parameters governing the selection of the MOSFET are the minimum threshold voltage, VTH 20136544 FIGURE 17. Typical SEPIC Converter www.national.com 18 LM3481 SELECTION OF INDUCTORS L1 AND L2 Proper selection of the inductors L1 and L2 to maintain constant current mode requires calculations of the following parameters. Average current in the inductors: If L1 and L2 are wound on the same core, then L1 = L2 = L. All the equations above will hold true if the inductance is replaced by 2L. A good choice for transformer with equal turns is Coiltronics CTX series Octopack. SENSE RESISTOR SELECTION The peak current through the switch, ISWPEAK, can be adjusted using the current sense resistor, RSEN, to provide a certain output current. Resistor RSEN can be selected using the formula: IL2AVE = IOUT Peak to peak ripple current, to calculate core loss if necessary: Sepic Capacitor Selection The selection of SEPIC capacitor, CS, depends on the rms current. The rms current of the SEPIC capacitor is given by: Maintaining the condition IL > ΔIL/2 to ensure continuous conduction mode yields the following minimum values for L1 and L2: Peak current in the inductor, to ensure the inductor does not saturate: The SEPIC capacitor must be rated for a large ACrms current relative to the output power. This property makes the SEPIC much better suited to lower power applications where the rms current through the capacitor is small (relative to capacitor technology). The voltage rating of the SEPIC capacitor must be greater than the maximum input voltage. Tantalum capacitors are the best choice for SMT, having high rms current ratings relative to size. Ceramic capacitors could be used, but the low C values will tend to cause larger changes in voltage across the capacitor due to the large currents, and high C value ceramics are expensive. Electrolytics work well for through hole applications where the size required to meet the rms current rating can be accommodated. There is an energy balance between CS and L1, which can be used to determine the value of the capacitor. The basic energy balance equation is: Where IL1PK must be lower than the maximum current rating set by the current sense resistor. The value of L1 can be increased above the minimum recommended value to reduce input ripple and output ripple. However, once ΔIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal. By increasing the value of L2 above the minimum recommendation, ΔIL2 can be reduced, which in turn will reduce the output ripple voltage: is the ripple voltage across the SEPIC capacitor, and is the ripple current through the inductor L1. The energy balance equation can be solved to provide a minimum value for CS: where ESR is the effective series resistance of the output capacitor. 19 www.national.com LM3481 Input Capacitor Selection Similar to a boost converter, the SEPIC has an inductor at the input. Hence, the input current waveform is continuous and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the input capacitor gets smaller, the input ripple goes up. The rms current in the input capacitor is given by: placed in series with the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 15). A 0.1 µF or 1 µF ceramic capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side of the resistor with the input power supply. Output Capacitor Selection The output capacitor of the SEPIC sees very large ripple currents similar to the output capacitor of a boost converter. The rms current through the output capacitor is given by: The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical in a SEPIC application, low values can cause impedance interactions. Therefore a good quality capacitor should be chosen in the range of 100 µF to 200 µF. If a value lower than 100 µF is used, then problems with impedance interactions or switching noise can affect the LM3481. To improve performance, especially with VIN below 8V, it is recommended to use a 20Ω resistor at the input to provide a RC filter. This resistor is The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the output for low ripple. Other Application Circuits 20136543 FIGURE 18. Typical High Efficiency Step-Up (Boost) Converter www.national.com 20 LM3481 Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Package NS Package Number MUB10A 21 www.national.com LM3481 High Efficiency Low-Side N-Channel Controller for Switching Regulators Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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