LP3931ISQ

LP3931 Dual RGB LED Driver with High Current Boost DC-DC Converter August 2004 LP3931 Dual RGB LED Driver with High Current Boost DC-DC Converter General Description The LP3931 is a RGB LED driver with high current boost DC-DC converter designed for portable wireless applications. It contains 2 sets of RGB LED drivers that are PWMdriven with programmable color, intensity and blinking patterns. They additionally feature a FLASH function to support picture taking with camera-enabled cellular phones. An efficient magnetic boost DC/DC converter provides the required bias, operating from a single Li-Ion battery. The DC/DC converter output voltage is user programmable for adapting to different LED types and for efficiency optimization. All functions are software controllable through the SPI interface and internal registers. Features n High Efficiency Programmable 300 mA Magnetic Boost DC-DC converter n 2 separately controlled PWM RGB LED drivers with programmable color, brightness, turn on/off slopes and blinking patterns n FLASH function with up to 6 outputs, each up to 120 mA n Functions software controlled through SPI interface n Additional LED on/off and dimming hardware control n Programmable low current Standby mode n Low voltage digital interface down to 1.8V n Space efficient 24-pin LLP package Applications n GSM Cellular Phones n WCDMA, CDMA and CDMA2000 Phones n PHS and PDC Cellular Phone Typical Application 20117301 © 2004 National Semiconductor Corporation DS201173 www.national.com LP3931 Connection Diagrams and Package Mark Information 24-Lead LLP Package, 4 x 4 x 0.8 mm NS Package Number NSQAL024 20117303 20117302 Bottom View Top View 20117304 Package Mark — Top View Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates the date code. “UZ” and “TT” are NSC internal codes for die manufacturing and assembly traceability. Both will vary considerably. Ordering Information Order Number LP3931ISQ LP3931ISQX Package Marking LP3931ISQ LP3931ISQ Supplied As 1000 units, Tape-and-Reel 2500 units, Tape-and-Reel www.national.com 2 LP3931 Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name G2 R2 GND_RGB R1 G1 B1 GND_BOOST SW VDD2 GND2 FB VREF SO SI SS SCK PWM_LED NRST VDDIO RT GND3 VDD1 GND1 B2 Type Output Output Ground Output Output Output Ground Output Power Ground Input Output Logic Output Logic Input Logic Input Logic Input Input Logic Input Power Input Ground Power Ground Output Open Drain, Green LED2 Open Drain, Red LED2 RGB Driver Ground Open Drain, Red LED1 Open Drain, Green LED1 Open Drain, Blue LED1 Power Switch Ground Open Drain, Boost Converter Power Switch Supply Voltage for Internal Digital Circuits Ground Boost Converter Feedback Internal Reference Bypass Capacitor SPI Serial Data Out SPI Serial Data Input SPI Slave Select SPI Clock LED Control for On/Off or PWM Dimming Low Active Reset Input Supply Voltage for Logic IO Signals Oscillator Resistor Ground Supply Voltage for Internal Analog Circuits Ground Open Drain, Blue LED2 Description 3 www.national.com LP3931 Absolute Maximum Ratings 2) (Notes 1, ESD Rating (Note 8) Human Body Model: Machine Model: 2 kV 200V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V (SW, FB, R1- 2, G1-2, B1-2) pins: Voltage to GND (Notes 3, 4) VDD1, VDD2, VDD_IO Voltage on Logic Pins I (R1, G1, B1, R2, G2, B2) (Note 5) I (VREF) Continuous Power Dissipation (Note 6) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Reflow soldering, 3 times) (Note 7) Operating Ratings (Notes 1, 2) V (SW, FB, R1-2, G1-2, B1-2) 3.0V to 6.0V 2.65V to 2.9V 1.8V to VDD1,2 0 mA to 300 mA −40˚C to +125˚C −40˚C to +85˚C VDD1, VDD2 (Note 4) VDD_IO Recommended Load Current Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 9) −0.3V to +7.2V −0.3V to +6.0V –0.3V to VDD_IO +0.3V, with 6.0V max 150 mA 10 µA Thermal Properties Internally Limited 125˚C −65˚C to +150˚C Junction-to-Ambient Thermal Resistance (θJA), SQA24A Package (Note 10) 39˚C/W 240˚C Electrical Characteristics (Notes 2, 11) Limits in standard typeface are for TJ = 25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ TJ ≤ +85˚C). Unless otherwise noted, specifications apply to the LP3931 Typical Application Circuit (pg. 1) with: VDD1 = VDD2 = VDDIO = 2.775V, CVDD1 = CVDD2 = CVDDIO = 0.1 µF, COUT = CIN = 10 µF, CVREF = 0.1 µF, L1 = 10 µH, RT = 82k (Note 12). Symbol IDD Parameter Standby Supply Current (VDD1 and VDD2 current) No-Load Supply Current (VDD1 and VDD2 current, boost off) Full Load Supply Current (VDD1 and VDD2 current, boost on) Condition NSTBY = L (register) SCK, SS, SI, NRST = H NSTBY = H (reg.) EN_BOOST = L (reg.) SCK, SS, SI, NRST = H NSTBY = H (reg.) EN_BOOST = H (reg.) SCK, SS, SI, NRST = H All Outputs Active NSTBY = L (reg.) SCK, SS, SI, NRST = H 1 MHz SCK Frequency CL = 50 pF at SO Pin I (VREF) ≤ 1 nA, Test Purposes Only 1.205 −2 Min Typ 1 Max 5 Units µA 170 250 µA 1 mA IDD_IO VDD_IO Standby Supply Current VDD_IO Supply Current 1 20 1.23 1.255 +2 µA µA V % VREF Reference Voltage (Note 13) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins (GND1-3, GND_BOOST, GND_RGB). Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime. Note 4: Voltage tolerance of LP3931 above 6.0V relies on fact that VDD1 and VDD2 (2.775V) are available (ON) at all conditions. If VDD1 and VDD2 are not available (ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device. Note 5: The total load current of the boost converter should be limited to 300 mA. Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160˚C (typ.) and disengages at TJ = 140˚C (typ.). Note 7: For detailed package and soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP). Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7. www.national.com 4 LP3931 Electrical Characteristics (Notes 2, 11) (Continued) Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX). Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 12: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics. Note 13: VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1. Block Diagram 20117305 LP3931 Block Diagram 5 www.national.com LP3931 Modes of Operation RESET: In the RESET mode all the internal registers are reset to the default values (Boost output register 3Fh (5.0V), all other registers 00h). Reset is entered always if input NRST is LOW or internal Power On Reset is active. The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after power up. STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Bias, Oscillator etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be written in any sequence and any number of bits can be altered in a register in one write. STANDBY: 20117306 www.national.com 6 LP3931 Logic Interface Characteristics (1.8V ≤ VDD_IO ≤ VDD1,2) Symbol VIL VIH II fSCK VIL VIH II tNRST VOL VOH Parameter Input Low Level Input High Level Logic Input Current Clock Frequency Input Low Level Input High Level Logic Input Current Reset Pulse Width Output Low Level Output High Level ISO = 3 mA ISO = − 3 mA VDD_IO − 0.5 1.5 −1.0 10 0.3 VDD_IO − 0.3 0.5 1.0 VDD_IO = 2.775V VDD_IO − 0.5 −1.0 1.0 13 0.5 Conditions Min Typ Max 0.5 Units V V µA MHz V V µA µs V V LOGIC INPUTS SS, SI, SCK, PWM_LED LOGIC INPUT NRST LOGIC OUTPUT SO SPI Interface LP3931 is compatible with the SPI serial bus specification and it operates as a slave. The transmission consists of 16-bit Write and Read Cycles. One cycle consists of 7 Address bits, 1 Read/Write (R/W) bit and 8 Data bits. R/W bit high state defines a Write Cycle and low defines a Read Cycle. SO output is normally in high-impedance state and it is active only when Data is sent out during a Read Cycle. A pull-up or pull-down resistor may be needed in SO line if a floating logic signal can cause unintended current consumption in the input where SO is connected. The Address and Data are transmitted MSB first. The Slave Select signal SS must be low during the Cycle transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK. 20117307 SPI Write Cycle 20117308 SPI Read Cycle 7 www.national.com LP3931 SPI Interface (Continued) 20117309 SPI Timing Diagram SPI Timing Parameters VDD1,2 = VDD_IO = 2.775V Symbol 1 2 3 4 5 6 7 8 9 10 11 12 Parameter Cycle Time Enable Lead Time Enable Lag Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Data Access Time Disable Time Data Valid Data Hold Time SS Inactive Time 0 10 Limit Min 70 35 35 35 35 0 20 0 20 10 20 Max Units ns ns ns ns ns ns ns ns ns ns ns ns Note: Data guaranteed by simulation. Magnetic Boost DC/DC Converter The LP3931 Boost DC/DC Converter generates a 4.1V–5.3V supply voltage for the LEDs from single Li-Ion battery (3V…4.5V). The output voltage is controlled with an 8-bit register in 9 steps. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The converter switching frequency is 1 MHz when timing resistor RT is 82 kΩ. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The user can program the output voltage of the boost converter. The control changes the resistor divider in the feedback loop. The following figure shows the boost topology with the protection circuitry. Three different protection schemes are implemented: 1. Over voltage protection, limits the maximum output voltage — Keeps the output below breakdown voltage. — Prevents boost operation if battery voltage is much higher than desired output. 2. Over current protection, limits the maximum inductor current — Voltage over switching NMOS is monitored; too high voltages turn the switch off. 3. Duty cycle limiting, done with digital control. www.national.com 8 LP3931 Magnetic Boost DC/DC Converter (Continued) Boost Converter Topology 20117310 Magnetic Boost DC/DC Converter Electrical Characteristics Symbol ILOAD VFB Parameter Load Current Voltage Accuracy at FB Pin (Boost Converter Output Voltage Accuracy) Voltage at FB Pin (Boost Converter Output Voltage) Conditions 3.0V ≤ VIN ≤ 4.5V VOUT (FB) = 5V 1 mA ≤ ISW ≤ 300 mA 3.0V ≤ VIN ≤ V (FB) – 0.5 V (FB) = 5V 1 mA ≤ ISW ≤ 300 mA 3.0V < VIN < 5V + V(SCHOTTKY) 1 mA ≤ ISW ≤ 300 mA VIN > 5V + V(SCHOTTKY) RDSON fPWF Switch ON Resistance PWM Mode Switching Frequency Frequency Accuracy tSTARTUP Startup Time VDD1,2 = 2.775V, ISW = 0.5A RT = 82 kΩ 2.65 ≤ VDD1,2 ≤ 2.9 RT = 82 kΩ From NSTBY and EN_BOOST 0 - > 1 transition 670 530 −6 −9 25 800 915 995 Min 0 Typ Max 300 Units mA −5 +5 % 5 V VIN – V(SCHOTTKY) 0.4 1 0.7 V Ω MHz +6 +9 % ±3 ms ICL_OUT SW Pin Current Limit mA Boost Standby Mode User can set the Boost Converter to STANDBY mode by writing the register bit EN_BOOST low. When EN_BOOST is written high, the converter waits for 10 ms for the internal voltages and currents to stabilize and then starts for 10 ms in PFM mode and then goes to PWM mode. 9 www.national.com LP3931 Boost Output Voltage Control User can control the boost output voltage by 8-bit boost output register as follows: Register 0DH Boost Output [7:0] 0000 0000 0000 0001 0000 0011 0000 0111 0000 1111 0001 1111 0011 1111 0111 1111 1111 1111 BOOST Output Voltage (typical) 4.15 4.30 4.40 4.55 4.70 4.85 5.00 Default 5.15 5.30 Boost Output Voltage Control 20117311 Boost Converter Typical Performance Characteristics otherwise stated. VIN = 3.6V, VOUT = 5.0V if not 20117313 20117312 Boost Converter Efficiency Boost Frequency vs RT Resistor 20117314 20117320 Battery Current vs Voltage Battery Current vs Voltage www.national.com 10 LP3931 Boost Converter Typical Performance Characteristics VIN = 3.6V, VOUT = 5.0V if not otherwise stated. (Continued) 20117321 20117317 Boost Typical Waveforms at 100 mA Load Boost Startup with No Load 20117318 20117319 Boost Line Regulation Boost Load Regulation, 50 mA-100 mA 11 www.national.com LP3931 Multiple RGB LED Drivers The RGB driver has six outputs that can independently drive 2 separate RGB LEDs or six LEDs of any kind. User has control over the following parameters separately for each LED: • ON and OFF (start and stop time in blinking cycle) (PWM brightness control) • DUTY (dimming slope) • SLOPE (output enable control) • ENABLE The main blinking cycle is controlled with 2-bit CYCLE control (0.25 / 0.5 / 1.0 / 2.0s). In the FLASH mode all the outputs are controlled in one phase and the PWM period is 50 µs. The time averaged FLASH mode current is three times the normal mode current at the same DUTY value. Blinking can be controlled separately for each output. ON and OFF times define, when a LED turns on and off within the blinking cycle. When both ON and OFF are 0, the LED is on and doesn’t blink. If ON equals OFF but is not 0, the LED is turned off. 20117324 Example Blinking Waveforms 20117322 RGB PWM Operating Principle RGB_START is the master enable control for the whole RGB function. The internal PWM and blinking control can be disabled by setting the RGB_PWM control LOW. In this case the individual enable controls can be used to switch outputs on and off. PWM_LED input can be used for external hardware PWM control. In the normal PWM mode the R, G and B switches are controlled in 3 phases (one phase per driver). During each phase the peak current set by the external ballast resistor is driven through the LED for the time defined by DUTY setting (0 µs–50 µs). As a time averaged current this means 0%–33% of the peak current. The PWM period is 150 µs and the pulse frequency is 6.67 kHz in normal mode. Application Note AN1291 describes in detail the RGB driver functionality of LP3933. The RGB driver in LP3931 is identical with LP3933. 20117323 Normal Mode PWM Waveforms at Different Duty Settings www.national.com 12 LP3931 RGB Driver Electrical Characteristics (R1, G1, B1, R2, G2, B2 outputs) Symbol RDS-ON ILEAKAGE IMAX TSMAX TSMIN TSRES TSTART/STOP Duty TBLINK DCYCF DCYC DRESF DRES FPWMF FPWM Parameter ON Resistance Off State Leakage Current Maximum Sink Current Maximum Slope Period Minimum Slope Period Slope Resolution Start/Stop Resolution Duty Step Size Blinking Cycle Accuracy Duty Cycle Range Duty Cycle Range Duty Resolution Duty Resolution PWM Frequency PWM Frequency EN_FLASH = 1 EN_FLASH = 0 EN_FLASH = 1 (4-bit) EN_FLASH = 0 (4-bit) EN_FLASH = 1 EN_FLASH = 0 −6 0 0 6.64 2.21 20 6.67 VFB = 5V, LED driver off (Note 5) At Maximum Duty Setting At Maximum Duty Setting At Maximum Duty Setting Cycle 1s 0.93 31 62 1/16 1/16 Conditions Min Typ 3.5 0.03 Max 6 1 120 Units Ω µA mA s ms ms s +6 99.6 33.2 % % % % % kHz kHz ±3 RGB LED PWM Control R1DUTY[3:0] G1DUTY[3:0] B1DUTY[3:0] R2DUTY[3:0] G2DUTY[3:0] B2DUTY[3:0] R1SLOPE[3:0] G1SLOPE[3:0] B1SLOPE[3:0] R2SLOPE[3:0] G2SLOPE[3:0] B2SLOPE[3:0] R1ON[3:0] G1ON[3:0] B1ON[3:0] R2ON[3:0] G2ON[3:0] B2ON[3:0] R1OFF[3:0] G1OFF[3:0] B1OFF[3:0] R2OFF[3:0] G2OFF[3:0] B2OFF[3:0] (Note 14) DUTY sets the brightness of the LED by adjusting the duty cycle of the PWM driver. The minimum DUTY cycle is 0% [0000] and the maximum in the Flash mode is ∼ 100% [1111] of peak pulse current. The peak pulse current is determined by the external resistor, LED forward voltage drop and the boost voltage. In normal mode the maximum duty cycle is 33%. SLOPE sets the turn-on and turn-off slopes. Fastest slope is set by [0000] and slowest by [1111]. SLOPE changes the duty cycle at constant, programmable rate. For each slope setting the maximum slope time appears at maximum DUTY setting. When DUTY is reduced, the slope time decreases proportionally. For example, in case of maximum DUTY, the sloping time can be adjusted from 31 ms [0000] to 930 ms [1111]. For 50% DUTY [0111] the sloping time is 14 ms [0000] to 434 ms [1111]. The blinking cycle has no effect on SLOPE. ON sets the beginning time of the turn-on slope. The on-time is relative to the selected blinking cycle length. On-setting N (N = 0 – 15) sets the on-time to N/16 * cycle length. OFF sets the beginning time of the turn-off slope. Off-time is relative to the blinking cycle length in the same way as the on-time. If ON = 0, OFF = 0 and RGB_PWM = 1, then the RGB outputs are continuously on (no blinking), the DUTY setting controls the brightness and the SLOPE control is ignored. If ON and OFF are the same, but not 0, the RGB outputs are turned off. CYCLE[1:0] CYCLE sets the blinking cycle: [00] for 0.25s, [01] for 0.5s, [10] for 1s and [11] for 2s. CYCLE effects to all RGB LEDs. 13 www.national.com LP3931 RGB LED PWM Control RSW1 GSW1 BSW1 RSW2 GSW2 BSW2 RGB_START Enable Enable Enable Enable Enable Enable for for for for for for (Note 14) (Continued) R1 switch G1 switch B1 switch R2 switch G2 switch B2 switch RGB_PWM EN_FLASH1 EN_FLASH2 R1_PWM G1_PWM B1_PWM R2_PWM G2_PWM B2_PWM Master Switch: RGB_START = 0 → RGB OFF RGB_START = 1 → RGB ON, starts the new cycle from t = 0 RGB_PWM = 0 → RSW, GWS and BSW control directly the RGB outputs (on/off control only) RGB_PWM = 1 → Normal PWM RGB functionality (duty, slope, on/off times, cycle) Flash Mode enable controls for RGB1 and RGB2. In Flash mode (EN_FLASH = 1) RGB outputs are PWM controlled simultaneously, not in 3-phase system as in the Normal Mode. XX_PWM = 0 → External PWM control from PWM_LED pin is disabled XX_PWM = 1 → External PWM control from PWM_LED pin is enabled Internal PWM control (DUTY) can be used independently of external PWM control. External PWM has the same effect on all enabled outputs. PWM_LED input can be used as a direct on/off or PWM brightness control for selected White LED or RGB outputs. For example it can trigger the Flash using a Flash signal from the camera. If PWM_LED input is not used, it must be tied to VDD_IO. Note 14: Application Note 1291, “Driving RGB LEDs Using LP3933 Lighting Management System” contains a thorough description of the RGB driver functionality including programming examples. It applies to LP3931, too. Recommended External Components OUTPUT CAPACITOR, COUT The output capacitor COUT directly affects the magnitude of the output ripple voltage so COUT should be carefully selected. In general, the higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple than the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower than the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V or greater is recommended. INPUT CAPACITOR, CIN The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is recommended. OUTPUT DIODE, DOUT A Schottky diode should be used for the output diode. To maintain high efficiency the average current rating of the schottky diode should be larger than the peak inductor cur- rent (1A). Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. INDUCTOR, L The LP3931’s high switching frequency enables the use of the small surface mount inductor. A 10 µH shielded inductor is suggested. The inductor should have a saturation current rating higher than the peak current it will experience during circuit operation (∼1A). Less than 100 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the OUT pin as close to the IC as possible. Examples of suitable inductors are TDK types LLF4017T-100MR90C and VLF4012AT-100MR79 and Coilcraft type DO3314T-103 (unshielded). www.national.com 14 LP3931 Recommended External Components Symbol CVDD1 CVDD2 COUT CIN CVDDIO RT RSO CVREF LBOOST DOUT RGB1 RGB2 Symbol Explanation VDD1 Bypass Capacitor VDD2 Bypass Capacitor Output Capacitor from FB to GND Input Capacitor from Battery Voltage to GND VDD_IO Bypass Capacitor Oscillator Frequency Bias Resistor SO Output Pull-up Resistor (Continued) List of External Components Value 100 100 10 10 100 82 100 100 10 0.3 Unit nF nF µF µF nF kΩ kΩ nF µH V Ceramic, X7R Shielded, Low ESR, ISAT ∼1A Schottky Diode Recommended Type Ceramic, X7R Ceramic, X7R Ceramic, X7R/Y5V Ceramic, X7R/Y5V Ceramic, X7R 1% (Note 15) Reference Voltage Capacitor, between VREF and GND Boost Converter Inductor Rectifying Diode, VF @ Maxload RGB LED1 RGB LED2 RR1, RG1, RB1 Current Limit Resistor RR2, RG2, RB2 Current Limit Resistor LEDs White LEDs User Defined (See Application Note AN-1291 for resistor size calculation) Note 15: Resistor RT accuracy specification change from 1% → 5% will be seen on timing accuracy of RGB block. Also the boost converter’s switching frequency will be affected. Control Registers Control registers and register bits are shown in the following table. ADDR 00H 01H 02H 03H 04H 05H 06H 07H 0BH 0DH 2AH 2BH 2CH 2DH 2EH 2FH REGISTER RGB Control register1 red1_on_off green1_on_off blue1_on_off r1slope, r1duty g1slope, g1duty b1slope, b1duty RGB Control register2 enables boost output red2_on_off green2_on_off blue2_on_off r2slope, r2duty g2slope, g2duty b2slope, b2duty boost[7] r2_on[3] g2_on[3] b2_on[3] r2slope[3] g2slope[3] b2slope[3] D7 rgb pwm r1_on[3] g1_on[3] b1_on[3] r1slope[3] g1slope[3] b1slope[3] cycle[1] D6 rgb start r1_on[2] g1_on[2] b1_on[2] r1slope[2] g1slope[2] b1slope[2] cycle[0] nstby boost[6] r2_on[2] g2_on[2] b2_on[2] r2slope[2] g2slope[2] b2slope[2] D5 rsw1 r1_on[1] g1_on[1] b1_on[1] r1slope[1] g1slope[1] b1slope[1] r1_pwm en_boost boost[5] r2_on[1] g2_on[1] b2_on[1] r2slope[1] g2slope[1] b2slope[1] D4 gsw1 r1_on[0] g1_on[0] b1_on[0] r1slope[0] g1slope[0] b1slope[0] g1_pwm en_flash1 boost[4] r2_on[0] g2_on[0] b2_on[0] r2slope[0] g2slope[0] b2slope[0] D3 bsw1 r1_off[3] g1_off[3] b1_off[3] r1duty[3] g1duty[3] b1duty[3] b1_pwm en_flash2 boost[3] r2_off[3] g2_off[3] b2_off[3] r2duty[3] g2duty[3] b2duty[3] boost[2] r2_off[2] g2_off[2] b2_off[2] r2duty[2] g2duty[2] b2duty[2] boost[1] r2_off[1] g2_off[1] b2_off[1] r2duty[1] g2duty[1] b2duty[1] boost[0] r2_off[0] g2_off[0] b2_off[0] r2duty[0] g2duty[0] b2duty[0] D2 rsw2 r1_off[2] g1_off[2] b1_off[2] r1duty[2] g1duty[2] b1duty[2] r2_pwm D1 gsw2 r1_off[1] g1_off[1] b1_off[1] r1duty[1] g1duty[1] b1duty[1] g2_pwm D0 bsw2 r1_off[0] g1_off[0] b1_off[0] r1duty[0] g1duty[0] b1duty[0] b2_pwm Default value of each register is 0000 0000 except boost output which is 0011 1111 (5V). 15 www.national.com LP3931 Application Examples 20117315 LP3931 with One RGB and One FLASH LED 20117316 LP3931 with Two RGB and One FLASH LED www.national.com 16 LP3931 Dual RGB LED Driver with High Current Boost DC-DC Converter Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead LLP Package, 4 x 4 x 0.8 mm NS Package Number NSQAL024 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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