LP5521YQX

LP5521 Programmable Three Channel LED Driver June 2007 LP5521 Programmable Three Channel LED Driver General Description The LP5521 is a three channel LED driver designed to produce variety of lighting effects for mobile devices. High efficiency charge pump enables LED driving over full Li-Ion battery voltage range. The device has a program memory for creating variety of lighting sequences. When program memory has been loaded, LP5521 can operate independently without processor control. LP5521 maintains excellent efficiency over a wide operating range by automatically selecting proper charge pump gain based on LED forward voltage requirements. LP5521 is able to automatically enter power-save mode, when LED outputs are not active and thus lowering current consumption. Three independent LED channels have accurate programmable current sources and PWM control. Each channel has program memory for creating desired lighting sequences with PWM control. LP5521 has a flexible digital interface. Trigger I/O and 32 kHz clock input allow synchronization between multiple devices. Interrupt output can be used to notify processor, when LED sequence has ended. LP5521 has four pin selectable I2C addresses. This allows connecting up to four parallel devices in one I2C bus. GPO and INT pins can be used as a digital control pin for other devices. LP5521 requires only four small and low cost ceramic capacitors. LP5521 is available in tiny 2.1x1.7x0.6 mm microSMD-20 package and in 4.0x5.0x0.8 mm bumped LLP-24 package. Comprehensive application tools are available, including command compiler for easy LED sequence programming. Features ■ Adaptive charge pump with 1x and 1.5x gain provides up to 95% LED drive efficiency ■ Charge pump with soft start and overcurrent/short circuit ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ protection Low input ripple and EMI Very small solution size, no inductor or resistors required 200 nA typical shutdown current Automatic power save mode I2C compatible interface Independently programmable constant current outputs with 8-bit current setting and 8-bit PWM control Typical LED output saturation voltage 50 mV and current matching 1% Three program execution engines with flexible instruction set Autonomous operation without external control Large SRAM program memory Two general purpose digital outputs microSMD-20 package, 0.4 mm pitch Bumped LLP-24 package, 0.5 mm pitch Applications ■ ■ ■ ■ Fun / indicator lights LCD sub-display backlighting Keypad RGB backlighting and phone cosmetics Vibra, speakers, waveform generator Typical Application 20186270 © 2007 National Semiconductor Corporation 201862 www.national.com LP5521 Connection Diagrams and Package Mark Information Thin microSMD-20 Package (2.1 x 1.7 x 0.6 mm, 0.4 mm pitch) NS Package Number TMD20ECA 20186271 Top View 20186272 Bottom View Package Mark 20186296 Package Mark - Top View www.national.com 2 LP5521 Connection Diagrams and Package Mark Information Bumped LLP-24 Package (5 x 4 x 0.8 mm, 0.5 mm pitch) NS Package Number YQA24A 20186202 20186201 Bottom View Package Mark - Top View U = Fab Z = Assembly XY = 2 Digit Date Code TT = Die Traceability L5521YQ = Product Identification Ordering Information Order Number LP5521TM LP5521TM X LP5521YQ LP5521YQ X Package µSMD µSMD bumped LLP bumped LLP Package Marking 5521 5521 L5521YQ L5521YQ Supplied As 250 units, Tape-and-Reel 3000 units, Tape-and-Reel 1000 units, Tape-and-Reel 4500 units, Tape-and-Reel Spec/Flow NoPb NoPb NoPb NoPb 3 www.national.com LP5521 Pin Descriptions LP5521TM Pin # 1A 1B 1C 1D 1E 2A 2B 2C 2D 2E 3A 3B 3C 3D 3E 4A 4B 4C 4D 4E Name B G R SCL SDA VOUT ADDR_SEL1 ADDR_SEL0 GPO EN CFLY2N CFLY1N GND CLK_32K INT CFLY2P CFLY1P VDD GND TRIG Type A A A I I/OD A I I O I A A G I OD/O A A P G I/OD Current source output Current source output Current source output I2C Serial interface clock input I2C Serial interface data input/output Charge pump output I2C address select input I2C address select input General purpose output Chip enable Negative terminal of charge pump fly capacitor 2 Negative terminal of charge pump fly capacitor 1 Ground 32 kHz clock input Interrupt output / General Purpose Output Positive terminal of charge pump fly capacitor 2 Positive terminal of charge pump fly capacitor 1 Power supply pin Ground Trigger input/output Description A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin www.national.com 4 LP5521 Pin Descriptions LP5521YQ Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDA EN SCL GPO R G B ADDR_SEL0 ADDR_SEL1 VOUT CFLY2N CFLY1N Name CFLY2P CFLY1P VDD GND CLK_32K INT TRIG Type A A P G I OD/O I/OD N/C N/C N/C N/C N/C I/OD I I O A A A I I A A A I2C Serial interface data input/output Chip enable I2C Serial interface clock input General purpose output Current source output Current source output Current source output I2C address select input I2C address select input Charge pump output Negative terminal of charge pump fly capacitor 2 Negative terminal of charge pump fly capacitor 1 Description Positive terminal of charge pump fly capacitor 2 Positive terminal of charge pump fly capacitor 1 Power supply pin Ground 32 kHz clock input Interrupt output / General purpose output Trigger input/output A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O: Input/Output Pin, O: Output Pin, OD: Open Drain Pin, N/C: Not Connected 5 www.national.com LP5521 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V(VDD , VOUT, R, G, B) Voltage on Logic Pins Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering) ESD Rating (Note 5) Human Body Model: Machine Model: -0.3V to +6.0V -0.3V to VDD +0.3V with 6.0V max Internally Limited 125°C -65°C to +150°C (Note 4) Operating Ratings (Notes 1, 2) VDD 2.7 to 5.5V Recommended Charge Pump Load Current IOUT 0 to 100 mA Junction Temperature (TJ) Range -30°C to +125°C Ambient Temperature (TA) Range (Note 6) -30°C to +85°C Thermal Properties Junction-to-Ambient Thermal Resistance (θJA), TMD20 Package (Note 7) Junction-to-Ambient Thermal Resistance (θJA), YQA24A Package (Note 7) 50 - 90°C/W 2 kV 200V 37 - 90°C/W (Notes 2, 8) Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range (-30°C < TA < +85°C). Unless otherwise noted, specifications apply to the LP5521 Block Diagram with: 2.7V ≤ VDD ≤ 5.5V, COUT= CIN = 1 μF, CFLY1 = CFLY2 = 0.47 μF. (Note 9). Symbol IVDD Parameter Standby supply current Condition EN = 0 (pin), CHIP_EN = 0 (bit), external 32 kHz clock running or not running EN = 1 (pin), CHIP_EN = 0 (bit), external 32 kHz clock not running EN = 1 (pin), CHIP_EN = 0 (bit), external 32 kHz clock running Normal mode supply current Charge pump and LED drivers disabled Charge pump in 1x mode, no load, LED drivers disabled Charge pump in 1.5x mode, no load, LED drivers disabled Charge pump in 1x mode, no load, LED drivers enabled Powersave mode supply current fOSC Internal oscillator frequency accuracy (Note 10) Condition Gain = 1.5x Gain = 1x fSW IGND Switching frequency -7 Ground current Gain = 1.5x Gain = 1x tON VOUT VOUT turn-on time from charge pump VDD = 3.6V, CHIP_EN = H off to 1.5x mode IOUT = 60 mA Charge pump output voltage VDD = 3.6V, no load, Gain = 1.5x 1.2 0.5 100 4.55 Min Typ 3.5 1 1.25 7 Max Units Ω Ω MHz % mA mA μs V External 32 kHz clock running Internal oscillator running -4 -7 Min Typ 0.2 1.0 1.4 0.25 0.70 1.5 1.2 10 0.25 4 7 Max 2 Units μA μA μA mA mA mA mA μA mA % Electrical Characteristics Charge Pump Electrical Characteristics Symbol ROUT Parameter Charge pump output resistance www.national.com 6 LP5521 LED Driver Electrical Characteristics (R, G, B Outputs) Symbol ILEAKAGE IMAX IOUT IMATCH fLED Parameter R, G, B pin leakage current Maximum Source Current Accuracy of output current Matching (Note 11) LED PWM switching frequency Outputs R, G, B Output current set to 17.5 mA, VDD = 3.6V IOUT = 17.5 mA, VDD = 3.6V PWM_HF = 1 Frequency defined by internal oscillator PWM_HF = 0 Frequency defined by 32 kHz clock (internal or external) VSAT Saturation voltage (Note 12) IOUT set to 17.5 mA -4 -5 1 558 Condition Min Typ 0.1 25.5 4 5 2 Max 1 Units µA mA % % Hz 256 50 100 Hz mV Logic Interface Characteristics (V(EN) = 1.65V...VDD unless otherwise noted) Symbol LOGIC INPUT EN VIL VIH II tDELAY VIL VIH II fCLK_32K fSCL VOL IL VIL VIH II VOL VOH IL Input Low Level Input High Level Logic Input Current Input delay Input Low Level Input High Level Input Current Clock frequency Clock frequency Output Low Level Output Leakage Current Input Low Level Input High Level Input Current Output Low Level Output High Level Output leakage current IOUT = 3 mA IOUT = -2 mA VDD - 0.5 0.8xVDD –1.0 0.3 VDD - 0.3 1.0 1.0 0.5 IOUT = 3 mA (pull-up current) 0.3 0.8xV(EN) -1.0 32 400 0.5 1.0 0.2xVDD 1.0 1.2 −1.0 2 0.2xV(EN) 1.0 0.5 V V µA µs V V µA kHz kHz V µA V V µA V V µA Parameter Conditions Min Typ Max Units LOGIC INPUT SCL, SDA, TRIG, CLK_32K LOGIC OUTPUT SDA, TRIG, INT LOGIC INPUT ADDR_SEL0, ADDR_SEL1 LOGIC OUTPUT GPO, INT (in GPO state) 7 www.national.com LP5521 I2C Timing Parameters (SDA, SCL) Symbol fSCL 1 2 3 4 5 6 7 8 9 10 Cb Clock Frequency Hold Time (repeated) START Condition Clock Low Time Clock High Time Parameter (Note 13) Limit Min 0.6 1.3 600 600 50 100 20+0.1Cb 15+0.1Cb 600 1.3 10 200 300 300 Max 400 Units kHz µs µs ns ns ns ns ns ns ns µs pF Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time of SDA and SCL Fall Time of SDA and SCL Set-up Time for STOP condition Bus Free Time between a STOP and a START Condition Capacitive Load for Each Bus Line 20186298 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale Package or AN1187 : Leadless Leadframe Package (LLP). Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 10: Input, output, and fly capacitors should be of the type X5R or X7R low ESR ceramic capacitor. Note 11: Matching is the maximum difference from the average of the three output's currents. Note 12: Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT - 1V. Note 13: Guaranteed by design. www.national.com 8 LP5521 Typical Performance Characteristics Unless otherwise specified: VDD = 3.6V LED Drive Efficiency vs. Input Voltage Automatic Gain Change LED Current vs. Output Pin Headroom Voltage 20186222 20186221 LED Current vs. Current Register Code LED Current vs. Supply Voltage 20186223 20186207 Charge Pump Efficiency vs. Load Current Charge Pump Efficiency vs. Input Voltage 1.5x Mode 20186208 20186209 9 www.national.com LP5521 Charge Pump Output Voltage vs. Load Current Charge Pump Output Voltage vs. Input Voltage Automatic Gain Change from 1x to 1.5x 20186210 20186211 Charge Pump Automatic Gain Change Hysteresis Charge Pump Startup in 1.5x Mode No Load 20186212 20186213 Charge Pump Load Transient Response in 1.5x Mode (0 to 25.5 mA) Charge Pump Line Transient Response 1.5x Mode (VIN 3.5V to 4.0V) 20186214 20186215 www.national.com 10 LP5521 Charge Pump Automatic Gain Change (LED VF = 3.6V) Standby Current vs. Input Voltage 20186216 20186217 For full LP5521 datasheet please contact nearest National Semiconductor sales office. 11 www.national.com LP5521 Physical Dimensions inches (millimeters) unless otherwise noted The dimension for X1 ,X2 and X3 are as given: X1=1.717 mm ± 0.03 mm X2=2.066 mm ± 0.03 mm X3=0.600 mm ± 0.075 mm TMD20ECA: Thin microSMD-20, Small Bump YQA24A: Bumped LLP-24 www.national.com 12 LP5521 Notes 13 www.national.com LP5521 Programmable Three Channel LED Driver Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com