MM74HC595

MM54HC595 MM74HC595 8-Bit Shift Registers with Output Latches January 1988 MM54HC595 MM74HC595 8-Bit Shift Registers with Output Latches General Description This high speed shift register utilizes advanced silicon-gate CMOS technology This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads This device contains an 8-bit serial-in parallel-out shift register that feeds an 8-bit D-type storage register The storage register has 8 TRI-STATE outputs Separate clocks are provided for both the shift register and the storage register The shift register has a direct-overriding clear serial input and serial output (standard) pins for cascading Both the shift register and storage register use positive-edge triggered clocks If both clocks are connected together the shift register state will always be one clock pulse ahead of the storage register The 54HC 74HC logic family is speed function and pin-out compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Y Y Y Low quiescent current 80 mA maximum (74HC Series) Low input current 1 mA maximum 8-bit serial-in parallel-out shift register with storage Wide operating voltage range 2V – 6V Cascadable Shift register has direct clear Guaranteed shift frequency DC to 30 MHz Connection Diagram Dual-In-Line Package Truth Table RCK X X X SCK X X SCLR X L H H G H L L L Function QA thru QH e TRI STATE Shift Register cleared Q He Shift Register clocked QN e Qn Q e SER Contents of Shift Register transferred to output latches u X u TL F 5342 – 1 Top View Order Number MM54HC595 or MM74HC595 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 5342 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Min Supply Voltage VCC DC Input or Output Voltage VIN VOUT Operating Temp Range (TA) MM HC MM HC Input Rise or Fall Times VCC e V tr tf VCC e V VCC e V b b If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 35 mA DC Output Current per pin (IOUT) g 70 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C Max VCC Units V V a a C C ns ns ns DC Electrical Characteristics (Note 4) Symbol VIH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s mA Conditions VCC V V V V V V V V V V V V V V V V V V V V V V V g g g TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units V V V V V V V V V V V V V V V V V V V V mA mA mA Guaranteed Limits VIL VOH QH VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VIN e VIH or VIL lIOUTl s mA QA thru QH VOL Maximum Low Level Output Voltage QH VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VIN e VCC or GND VOUT e VCC or GND G e VIH VIN e VCC or GND IOUT e mA QA thru QH IIN IOZ ICC Maximum Input Current Maximum TRI STATE Output Leakage Maximum Quiescent Supply Current g g g Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics VCC e 5V Symbol fMAX tPHL tPLH tPHL tPLH tPZH tPZL tPHZ tPLZ tS tS tS Parameter Maximum Operating Frequency of SCK Maximum Propagation Delay SCK to QH TA e 25 C tr e tf e 6 ns Conditions Typ Guaranteed Limit Units MHz CL e CL e pF pF ns ns Maximum Propagation Delay RCK to QA thru QH Maximum Output Enable Time from G to QA thru QH Maximum Output Disable Time from G to QA thru QH Minimum Setup Time from SER to SCK Minimum Setup Time from SCLR to SCK Minimum Setup Time from SCK to RCK See Note Minimum Hold Time from SER to SCK Minimum Pulse Width of SCK or RCK RL e kX CL e pF RL e kX CL e pF ns ns ns ns ns tH tW ns ns Note 5 This setup time ensures the register will see stable data from the shift-register outputs The clocks may be connected together in which case the storage register state will be one clock pulse behind the shift register AC Electrical Characteristics VCC e 2 0 – 6 0V Symbol fMAX Parameter Maximum Operating Frequency Maximum Propagation Delay from SCK to Q H Conditions CL e pF VCC V V V V V V V V V V V V V V V CL e 50 pF tr e tf e 6 ns (unless otherwise specified) TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns Guaranteed Limits tPHL tPLH CL e CL e CL e CL e CL e CL e pF pF pF pF pF pF pF pF pF pF pF pF tPHL tPLH Maximum Propagation Delay from RCK to QA thru QH CL e CL e CL e CL e CL e CL e 3 AC Electrical Characteristics VCC e 2 0 – 6 0V CL e 50 pF tr e tf e 6 ns (unless otherwise specified) (Continued) Symbol tPHL tPLH Parameter Maximum Propagation Delay from SCLR to Q H Maximum Output Enable from G to QA thru QH RL e kX CL e pF pF CL e CL e CL e CL e CL e tPHZ tPLZ Maximum Output Disable Time from G to QA thru QH Minimum Setup Time from SER to SCK Minimum Removal Time from SCLR to SCK Minimum Setup Time from SCK to RCK Minimum Hold Time SER to SCK Minimum Pulse Width of SCK or SCLR Maximum Input Rise and Fall Time Clock Maximum Output Rise and Fall Time QA QH Maximum Output Rise Fall Time QH Power Dissipation Capacitance Outputs Enabled Note Maximum Input Capacitance Maximum Output Capacitance G e VCC G e GND pF pF pF pF Conditions VCC V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF pF Guaranteed Limits tPZH tPZL RL e kX CL e pF tS tR tS tH tW tr tf tTHL tTLH tTHL tTLH CPD CIN COUT Note 6 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 4 Logic Diagram (positive logic) TL F 5342 – 3 5 Timing Diagram MM54HC595 MM74HC595 TL F 5342 – 2 6 Physical Dimensions inches (millimeters) Order Number MM54HC595J or MM54HC595J NS Package J16A 7 MM54HC595 MM74HC595 8-Bit Shift Registers with Output Latches Physical Dimensions inches (millimeters) (Continued) Order Number MM54HC595N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and 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