NTE6664

NTE6664 Integrated Circuit 64K–Bit Dynamic RAM Description: The NTE6664 is a 65,536 Bit, high–speed, dynamic Random Access Memory. Organized as 65,536 one–bit words and fabricated using HMOS high–performance N–Channel silicon–gate technology, this 5V only dynamic RAM combines high performance with low cost and improved reliability. By multiplying row– and column– address inputs, the NTE6664 requires only eight address lines and permits packaging in a standard 16–Lead DIP package. Complete address decoding is done on chip with address latches incorporated. Data out is controlled by CAS allowing for greater system flexibility. All inputs and outputs, including clocks, are fully TTL compatible. The NTE6664 incorporates a one– transistor cell design and dynamic storage techniques. In addition to the RAS–only refresh mode, the refresh control function available on Pin1 provides two additional modes of refresh, automatic and self refresh. Features: D Single +5V Operation (±10%) D Maximum Access Time: 150ns D Low Power Dissipation: 302.5mW Max (Active) 22mW Max (Standby) D Three State Data Output D Early–Write Common I/O Capability D D D D D D 128 Cycle, 2ms Refresh Control on Pin1 for Automatic or Self Refresh RAS–Only Refresh Mode CAS Controlled Output Fast Page Mode Cycle Time Low Soft Error Rate: < 0.1% per 1000 Hrs Absolute Maximum Ratings: (Note 1) Voltage on VCC Supply Relative to VSS, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 to +7V Voltage Relative to VSS for Any Pin Except VCC, Vin, Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 to +7V Data Out Current (Short Circuit), Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect the device reliability. Recommended Operating Conditions: (Note 2, TA = 0 to +70°C unless otherwise specified) Parameter Supply Voltage (Operating Voltage Range) Logic 1 Voltage, All Inputs Logic 0 Voltage, All Inputs (Note 3) Symbol VCC VSS VIH VIL Min 4.5 0 2.4 –1.0 Typ 5.0 0 – – Max 5.5 0 6.5 0.8 Unit V V V V Note 2. All voltages referenced to VSS. Note 3. The device will withstand undershoots to the –2V level with a maximum pulse width 0f 20ns at the –1.5V level. This is periodically sampled rather than 100% tested. DC Characteristics: (VCC = 5V ±10%, TA = 0 to +70°C unless otherwise specified) Parameter VCC Power Supply Current VCC Power Supply Current (Standby) VCC Power Supply Current During RAS only Refresh Cycles Input Leakage Current Any Input Except REFRESH REFRESH Input Current Output Leakage Current Output Logic 1 Voltage Output Logic 0 Voltage Symbol ICC1 ICC2 ICC3 Ilkg(L) Ilkg(F) Ilkg(O) VOH VOL Test Conditions tRC = 270ns, Note 4 RAS = CAS = VIH tRC = 270ns, Note 4 VSS < Vin < VCC VSS < Vin < VCC CAS at Logic 1, 0 ≤ Vout ≤ 5.5V Iout = –4mA Iout = 4mA Min – – – – – – 2.4 – Typ – – – – – – – – Max 55 4 45 10 20 10 – 0.4 Unit mA mA mA µA µA µA V V Note 4. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. Capacitance: (VCC = 5V ±10%, f = 1MHz, TA = +25°C, Note 5, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance A0 – A7, D RAS, CAS, WRITE, REFRESH Output Capacitance Q Symbol Cin Cout CAS = VIH to Disable Output Test Conditions Min – – – Typ 3 6 5 Max 5 8 7 Unit pF pF Note 5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I∆t/∆V. Read, Write, and Read–Modify–Write Cycles: (VCC = 5V ±10%, TA = 0 to +70°C unless other– wise specified, Notes 6, 7, and 8) Parameter Random Read or Write Cycle Time Read–Write Cycle Time Access Time from RAS Access Time from CAS Output Buffer and Turn–Off Delay RAS Precharge Time RAS Pulse Width CAS Pulse Width Symbol tRC tRWC tRAC tCAC tOFF tRP tRAS tCAS Test Conditions Note 9, Note 10 Note 9, Note 10 Note 11, Note 13 Note 12, Note 13 Note 19 Min 270 280 – – 0 100 150 75 Typ – – – – – – – – Max – – 150 75 30 – 10000 10000 Unit ns ns ns ns ns ns ns ns Read, Write, and Read–Modify–Write Cycles (Cont’d): (VCC = 5V ±10%, TA = 0 to +70°C unless otherwise specified, Notes 6, 7, and 8) Parameter RAS to CAS Delay Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address Hold Time Referenced to RAS Transition Time (Rise and Fall) Read Command Setup Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS Write Command Hold Time Write Command Hold Time Referenced to RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data in Setup Time Data in Hold Time Data in Hold Time Referenced to RAS CAS to RAS Precharge Time RAS Hold Time Refresh Period Write Command Setup Time CAS to Write Delay RAS to Write Delay CAS Hold Time CAS Precharge Time (Page Mode Cycle Only) Page Mode Cycle Time RAS to REFRESH Delay REFRESH Period (Battery Backup Mode) REFRESH to RAS Precharge Time (Battery Backup Mode) REFRESH Cycle Time (Auto Pulse Mode) REFRESH Pulse Period (Auto Period Mode) REFRESH to RAS Setup Time (Auto Pulse Mode) REFRESH to RAS Delay Time (Auto Pulse Mode) REFRESH Inactive Time RAS to REFRESH Lead Time RAS Inactive Time During REFRESH Symbol tRCD tASR tRAH tASC tCAH tAR tT tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tCRP tRSH tRFSH tWCS tCWD tRWD tCSH tCP tPC tRFD tFBP tFBR tFC tFP tFSR tFRD tFI tFRL tFRI Note 17 Note 17 Note 17 Note 16 Note 16 Note 18 Note 18 Note 15 Note 15 Note 18 Test Conditions Note 14 Min 25 0 20 0 35 95 3 0 0 0 35 95 35 45 45 0 35 95 –10 75 – –10 45 120 150 60 145 –10 2000 320 270 60 –30 320 60 370 370 Typ – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Max 75 – – – – – 50 – – – – – – – – – – – – – 2 – – – – – – – – – – 2000 – – – – – Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 6. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Note 7. An initial pause of 100µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed. Note 8. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transmit between VIH and VIL (or between VIL and VIH) in a monotonic manner. Note 9. The specification for tRC(min) and tRMW(min) are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is assured. Note10. AC measurements tT = 5ns. Note 11. Assumes that tRCD ≤ tRCD(max). Note12. Assumes that tRCD ≥ tRCD(max). Note13. Measured with a current load equivalent to 2 TTL (–200µA, +4mA) loads and 100pF with the data output trip points set at VOH = 2V and VOL = 0.8V. Note14. Operation within the tRCD(max) limit ensures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Note15. Either tRRH or tRCH must be satisfied for a read cycle. Note16. These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed write or read–modify–write cycles. Note17. tWCS, tCWD, and tRWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS ≥ tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD ≥ tCWD(min) and tRWD ≥ tRWD(min), the cycle is read–write cycle and the data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. Note19. tOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. Block Diagram VCC VSS Column Decoder Precharge Clock Address Buffer/Counters/Multiplexers A0 A1 A2 A3 A4 A5 A6 A7 Memory Array Row Decoder Memory Array Memory Array Row Decoder Memory Array I/O Timing Control and Refresh Control RAS CAS Write, W REFRESH Data In, D Row Decoder Memory Array Column Decoder Memory Array Memory Array Row Decoder Memory Array Output Data, Q Precharge Clock Pin Connection Diagram * REFRESH 1 D2 W3 RAS 4 A0 5 A1 6 A2 7 VCC 8 16 VSS 15 CAS 14 Q 13 A6 12 A3 11 A4 10 A5 9 A7 * If pin is not used, it should be connected to VCC through a 10k resistor. 16 9 1 8 .870 (22.0) Max .200 (5.08) Max .260 (6.6) Max .100 (2.54) .700 (17.78) .099 (2.5) Min