74ABT657
Octal transceiver with parity generator/checker; 3-state
Rev. 03 — 15 March 2010
Product data sheet
1. General description
The 74ABT657 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers with 3-state outputs
and an 8-bit parity generator/checker, and is intended for bus-oriented applications. The
buffers have a guaranteed current sinking capability of 64 mA. The Transmit/Receive input
(pin T/R) determines the direction of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from A ports to B ports; Receive (active LOW)
enables data from B ports to A ports.
When Output Enable input (pin OE) is HIGH, both A and B ports are high-impedance. The
parity select input (pin ODD/EVEN) allows the user to generate either an odd or even
parity output, depending on the system. Pin PARITY is an output from the
generator/checker when transmitting from port A to port B (pin T/R = HIGH) and an input
when receiving from port B to port A port (pin T/R = LOW).
In transmit mode (pin T/R = HIGH) port A is polled to determine the number of HIGH
inputs on port A. Pin PARITY output goes to the logic state determined by the setting of
pin ODD/EVEN and by the number of HIGH inputs on port A. For example, if pin
ODD/EVEN is set LOW (even parity) and the number of HIGH inputs on port A is odd, pin
PARITY output goes HIGH, transmitting even parity. If the number of HIGH inputs on port
A is even, pin PARITY output goes LOW, keeping even parity.
In receive mode (pin T/R = LOW) port B is polled to determine the number of HIGH inputs
on port B. If pin ODD/EVEN is LOW (even parity) and the number of HIGH inputs on port
B is:
• Odd and pin PARITY input is HIGH, pin ERROR is HIGH, indicating no error
• Even and pin PARITY input is HIGH, pin ERROR goes LOW, indicating an error
2. Features and benefits
n
n
n
n
n
n
Combinational functions in one package
Low static and dynamic power dissipation with high speed and high output drive
Output capability: +64 mA and −32 mA
Power-up 3-state
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
u HBM JESD22-A114F exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
74ABT657D
−40 °C to +85 °C
SO24
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
74ABT657DB
−40 °C to +85 °C
SSOP24
plastic shrink small outline package; 24 leads; body width
5.3 mm
74ABT657PW −40 °C to +85 °C
Version
TSSOP24 plastic thin shrink small outline package; 24 leads; body
width 4.4 mm
SOT340-1
SOT355-1
4. Functional diagram
2
3
4
5
6
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
1
T/R
24
OE
11
ODD/EVEN
B0 B1 B2
23
22
21
PARITY
13
ERROR
12
B3
B4
B5
B6
B7
20
17
16
15
14
001aae826
Fig 1.
Logic symbol
1
24
0
M
1
0 0 BUS B TO A
1 BUS A TO B
2
2 HIGH Z
11
G3[EVEN]
G4[ODD]
2K
2
0
=
1,3[EVEN]
1,4[ODD]
0,3[EVEN
0,4]ODD
13
12
23
2
3
22
4
21
5
20
6
17
8
16
9
15
10
14
001aae827
Fig 2.
IEC logic symbol
74ABT657_3
Product data sheet
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Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
2 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
T/R
OE
A0
A1
A2
A3
A4
A5
A6
A7
ODD/EVEN
1
24
2
23
3
22
4
21
5
20
6
17
8
16
9
15
10
14
B0
B1
B2
B3
B4
B5
B6
B7
13
11
12
PARITY
ERROR
001aae828
Fig 3.
Logic diagram
74ABT657_3
Product data sheet
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Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
3 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
5. Pinning information
5.1 Pinning
74ABT657
T/R
1
24 OE
A0
2
23 B0
A1
3
22 B1
A2
4
21 B2
A3
5
20 B3
A4
6
19 GND
VCC
7
18 GND
A5
8
17 B4
A6
9
16 B5
A7 10
15 B6
ODD/EVEN 11
14 B7
13 PARITY
ERROR 12
001aae825
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
T/R
1
transmit/receive input
A0 to A7
2, 3, 4, 5, 6, 8, 9, 10
A port input/3-state output
VCC
7
positive supply voltage
ODD/EVEN
11
parity select input
ERROR
12
error output in receive mode
PARITY
13
parity output in transmit mode/input in
receive mode
B0 to B7
23, 22, 21, 20, 17, 16, 15, 14
B port input/3-state output
GND
18, 19
ground (0 V)
OE
24
output enable input (active LOW)
74ABT657_3
Product data sheet
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Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
4 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
6. Functional description
6.1 Function selection
Table 3.
Function selection[1]
Number of
inputs HIGH
Inputs
OE
T/R
0, 2, 4, 6 and 8
(even)
L
L
1, 3, 5 and 7
(odd)
Don’t care
[1]
Data I/O
Output
ODD/EVEN
PARITY
ERROR
Mode
H
H
H
Z
transmit
H
L
L
Z
transmit
L
L
H
H
H
receive
L
L
H
L
L
receive
L
L
L
H
L
receive
L
L
L
L
H
receive
L
H
H
L
Z
transmit
L
H
L
H
Z
transmit
L
L
H
H
L
receive
L
L
H
L
H
receive
L
L
L
H
H
receive
L
L
L
L
L
receive
H
X
X
Z
Z
3-state
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
5 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
−0.5
+7.0
V
[1]
−1.2
+7.0
V
[1]
−0.5
+5.5
V
VI
input voltage
VO
output voltage
output in OFF-state or HIGH-state
IIK
input clamping current
VI < 0 V
−18
-
mA
IOK
output clamping current
VO < 0 V
−50
-
mA
IO
output current
output in LOW-state
Tj
junction temperature
Tstg
storage temperature
[2]
-
128
mA
-
150
°C
−65
+150
°C
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
VI
input voltage
0
-
VCC
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IOH
HIGH-level output current
−32
-
-
mA
IOL
LOW-level output current
-
-
64
mA
∆t/∆V
input transition rise and fall rate
0
-
5
ns/V
Tamb
ambient temperature
−40
-
+85
°C
74ABT657_3
Product data sheet
in free air
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Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
6 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
25 °C
Conditions
Min
Typ
Max
Min
Max
−1.2
−0.9
-
−1.2
-
V
VCC = 4.5 V; IOH = −3 mA
2.5
3.5
-
2.5
-
V
VCC = 5.0 V; IOH = −3 mA
3.0
4.0
-
3.0
-
V
VCC = 4.5 V; IOH = −32 mA
2.0
2.6
-
2.0
-
V
-
0.42
0.55
-
0.55
V
control pins
-
±0.01
±1.0
-
±1.0
µA
data pins
-
±5
±100
-
±100
µA
-
±5.0
±100
-
±100
µA
-
±5.0
±50
-
±50
µA
VO = 2.7 V
-
5.0
50
-
50
µA
VO = 0.5 V
-
−5.0
−50
-
−50
µA
-
5.0
50
-
50
µA
−180
−100
−50
−180
−50
mA
outputs HIGH-state
-
0.5
250
-
250
µA
outputs LOW-state
-
20
30
-
30
mA
-
0.5
250
-
250
µA
outputs enabled
-
0.5
1.5
-
1.5
mA
outputs 3-state, one data input
-
50
250
-
250
µA
VIK
input clamping voltage
VCC = 4.5 V; IIK = −18 mA
VOH
HIGH-level output
voltage
VI = VIL or VIH
VOL
LOW-level output voltage VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
II
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
IOFF
power-off leakage
current
VCC = 0 V; VI or VO ≤ 4.5 V
IO(pu/pd)
power-up/power-down
output current
VCC = 2.0 V; VO = 0.5 V;
VI = GND or VCC; OE HIGH
IOZ
OFF-state output current VCC = 5.5 V; VI = VIL or VIH
ILO
output leakage current
HIGH-state; VO = 5.5 V;
VCC = 5.5 V; VI = GND or VCC
IO
output current
VCC = 5.5 V; VO = 2.5 V
ICC
supply current
VCC = 5.5 V; VI = GND or VCC
[1]
[2]
outputs disabled
∆ICC
−40 °C to +85 °C Unit
additional supply current per input pin; VCC = 5.5 V; one
input at 3.4 V; other inputs at VCC
or GND
outputs 3-state; one enable input
CI
input capacitance
VI = 0 V or VCC
CI/O
input/output capacitance outputs disabled; VO = 0 V or VCC
[3]
-
0.5
1.5
-
1.5
mA
-
4
-
-
-
pF
-
7
-
-
-
pF
[1]
This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 ms. For VCC = 2.1 V to VCC = 5 V ± 10 %, a
transition time of up to 100 µs is permitted.
[2]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3]
This is the increase in supply current for each input at 3.4 V.
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
7 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter
LOW to HIGH
propagation delay
tPLH
HIGH to LOW
propagation delay
tPHL
25 °C; VCC = 5.0 V
Conditions
−40 °C to +85 °C; Unit
VCC = 5.0 V ± 0.5 V
Min
Typ
Max
Min
Max
An to Bn or Bn to An; see Figure 6
1.1
2.5
4.1
1.1
4.6
ns
An to PARITY; see Figure 5 and 6
2.5
5.1
6.7
2.5
8.1
ns
ODD/EVEN to PARITY and ERROR;
see Figure 5 and 6
1.7
3.5
4.6
1.7
5.3
ns
Bn to ERROR; see Figure 5 and 6
3.9
7.3
10.2
3.9
12.3
ns
PARITY to ERROR; see Figure 5 and 6
2.7
4.5
5.9
2.7
7.7
ns
An to Bn or Bn to An; see Figure 6
1.2
3.0
3.9
1.2
4.3
ns
An to PARITY; see Figure 5 and 6
2.8
5.0
7.4
2.8
8.9
ns
ODD/EVEN to PARITY and ERROR;
see Figure 5 and 6
1.9
3.7
5.1
1.9
5.8
ns
Bn to ERROR; see Figure 5 and 6
4.0
7.9
10.5
4.0
12.9
ns
3.2
5.2
6.7
3.2
8.1
ns
tPZH
OFF-state to HIGH
propagation delay
see Figure 7 and 8
PARITY to ERROR; see Figure 5 and 6
[1]
1.3
3.6
5.5
1.3
6.5
ns
tPZL
OFF-state to LOW
propagation delay
see Figure 7 and 8
[1]
1.9
4.2
5.3
1.9
6.5
ns
tPHZ
HIGH to OFF-state
propagation delay
see Figure 7 and 8
2.4
3.6
5.6
2.4
6.2
ns
tPLZ
LOW to OFF-state
propagation delay
see Figure 7 and 8
2.2
3.4
7.3
2.2
7.8
ns
[1]
These delay times reflect the 3-state recovery time only and do not include the delay through the buffers and the parity check circuitry
which affect the ERROR output. To ensure valid information at the ERROR pin, time must be allowed for the signal to propagate
through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output. Valid data at the
ERROR pin ≥ (B to A) + (A to PARITY).
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
8 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
11. Waveforms
VI
An, Bn,
ODD/EVEN
PARITY
VM
VM
GND
tPHL
tPLH
VOH
PARITY,
ERROR
VM
VM
VOL
001aae829
VM = 1.5 V
Fig 5.
Propagation delay for inverting output
VI
An, Bn,
ODD/EVEN
PARITY
VM
VM
GND
tPLH
tPHL
VOH
An, Bn,
PARITY,
ERROR
VM
VM
VOL
001aae830
VM = 1.5 V
Fig 6.
Propagation delay for non-inverting output
VI
VM
OE
VM
GND
tPZH
tPHZ
VOH
An, Bn,
PARITY,
ERROR
GND
VOH − 0.3 V
VM
001aae831
VM = 1.5 V
Fig 7.
74ABT657_3
Product data sheet
3-state output enable time to HIGH-level and output disable time from HIGH-level
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Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
9 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
VI
VM
OE
VM
GND
tPZL
tPLZ
3.5 V
An, Bn,
PARITY,
ERROR
VM
VOL + 0.3 V
VOL
001aae832
VM = 1.5 V
Fig 8.
VI
tW
90 %
90 %
negative
pulse
VM
VEXT
VM
10 %
0V
VCC
10 %
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
3-state output enable time to LOW-level and output disable time from LOW-level
VI
DUT
RT
90 %
RL
VO
G
CL
RL
VM
VM
10 %
10 %
mna616
tW
001aai298
a. Input pulse definition
b. Test circuit
Test data and VEXT levels are given in Table 8.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 9.
Table 8.
Test circuit for measuring switching times
Test data
Input
Load
VEXT
VI
fI
tW
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
3.0 V
1 MHz
500 ns
≤ 2.5 ns
50 pF
500 Ω
open
open
7.0 V
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
10 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 10. Package outline SOT137-1 (SO24)
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
11 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 11. Package outline SOT340-1 (SSOP24)
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
12 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT355-1 (TSSOP24)
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
13 of 17
74ABT657
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Octal transceiver with parity generator/checker; 3-state
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ABT657_3
20100315
Product data sheet
-
74ABT657_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
DIP 24 (SOT222-1) package removed from Section 3 “Ordering information” and Section 12
“Package outline”.
74ABT657_2
20041027
Product specification
-
74ABT657
74ABT657
19951211
Product specification
-
-
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
14 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74ABT657_3
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
15 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT657_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 15 March 2010
© NXP B.V. 2010. All rights reserved.
16 of 17
74ABT657
NXP Semiconductors
Octal transceiver with parity generator/checker; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
6.1
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function selection. . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 March 2010
Document identifier: 74ABT657_3
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