74ALVT162823DL,512

74ALVT162823 18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state Rev. 02 — 11 August 2005 Product data sheet 1. General description The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop. The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers or transmitters. 2. Features ■ Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops ■ 5 V I/O compatible ■ Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors ■ Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion and extraction permitted ■ Power-up 3-state ■ Power-up reset ■ Output capability: +12 mA to −12 mA ■ Outputs include series resistance of 30 Ω making external termination resistors unnecessary ■ Latch-up protection: ◆ JESD78: exceeds 500 mA ■ ESD protection: ◆ MIL STD 883, method 3015: exceeds 2000 V ◆ Machine Model: exceeds 200 V 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 3. Quick reference data Table 1: Quick reference data Tamb = 25 °C. Symbol Parameter tPLH propagation delay nCP to nQx tPHL propagation delay nCP to nQx Conditions Min Typ Max Unit CL = 50 pF; VCC = 2.5 V - 3.7 - ns CL = 50 pF; VCC = 3.3 V - 2.9 - ns CL = 50 pF; VCC = 2.5 V - 2.8 - ns CL = 50 pF; VCC = 3.3 V - 2.3 - ns VI = 0 V or VCC - 3 - pF Ci input capacitance Co output capacitance VI/O = 0 V or 3.0 V - 9 - pF ICC quiescent supply current outputs disabled; VCC = 2.5 V - 40 - µA outputs disabled; VCC = 3.3 V - 70 - µA 4. Ordering information Table 2: Ordering information Type number 74ALVT162823DL Package Temperature range Name Description Version −40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVT162823DGG −40 °C to +85 °C 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 2 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 5. Functional diagram 1OE 1MR 1CE 1CP 2OE 2MR 2CE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2 1 55 56 27 28 30 29 54 EN1 R2 G3 3C4 EN5 R6 G7 7C8 4D 1,2 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 8D 5,6 15 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 001aad242 Fig 1. IEC logic symbol VCC VCC VCC 27 Ω output data input to internal circuit 27 Ω 001aad244 Fig 2. Schematic of each output 74ALVT162823_2 Product data sheet 001aad245 Fig 3. Bus hold circuit © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 3 of 20 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 74ALVT162823_2 Product data sheet nCE nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nCP CP nD R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R CP nD Q R Q nMR nOE nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 001aad243 Fig 4. Logic diagram 74ALVT162823 4 of 20 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Rev. 02 — 11 August 2005 nQ0 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 6. Pinning information 6.1 Pinning 1MR 1 56 1CP 1OE 2 55 1CE 1Q0 3 54 1D0 GND 4 53 GND 1Q1 5 52 1D1 1Q2 6 51 1D2 VCC 7 1Q3 8 50 VCC 49 1D3 1Q4 9 48 1D4 1Q5 10 47 1D5 GND 11 46 GND 1Q6 12 45 1D6 1Q7 13 44 1D7 1Q8 14 2Q0 15 43 1D8 74ALVT162823 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 2Q6 23 35 VCC 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2OE 27 30 2CE 2MR 28 29 2CP 001aab433 Fig 5. Pin configuration 6.2 Pin description Table 3: Pin description Symbol Pin Description 1MR 1 1 master reset input (active LOW) 1OE 2 1 output enable input (active LOW) 1Q0 3 1 data output 0 GND 4 ground (0 V) 1Q1 5 1 data output 1 1Q2 6 1 data output 2 VCC 7 supply voltage 1Q3 8 1 data output 3 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 5 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Table 3: Pin description …continued Symbol Pin Description 1Q4 9 1 data output 4 1Q5 10 1 data output 5 GND 11 ground (0 V) 1Q6 12 1 data output 6 1Q7 13 1 data output 7 1Q8 14 1 data output 8 2Q0 15 2 data output 0 2Q1 16 2 data output 1 2Q2 17 2 data output 2 GND 18 ground (0 V) 2Q3 19 2 data output 3 2Q4 20 2 data output 4 2Q5 21 2 data output 5 VCC 22 supply voltage 2Q6 23 2 data output 6 2Q7 24 2 data output 7 GND 25 ground (0 V) 2Q8 26 2 data output 8 2OE 27 2 output enable input (active LOW) 2MR 28 2 master reset input (active LOW) 2CP 29 2 clock pulse input (active rising edge) 2CE 30 2 clock enable input (active LOW) 2D8 31 2 data input 8 GND 32 ground (0 V) 2D7 33 2 data input 7 2D6 34 2 data input 6 VCC 35 supply voltage 2D5 36 2 data input 5 2D4 37 2 data input 4 2D3 38 2 data input 3 GND 39 ground (0 V) 2D2 40 2 data input 2 2D1 41 2 data input 1 2D0 42 2 data input 0 1D8 43 1 data input 8 1D7 44 1 data input 7 1D6 45 1 data input 6 GND 46 ground (0 V) 1D5 47 1 data input 5 1D4 48 1 data input 4 1D3 49 1 data input 3 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 6 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Table 3: Pin description …continued Symbol Pin Description VCC 50 supply voltage 1D2 51 1 data input 2 1D1 52 1 data input 1 GND 53 ground (0 V) 1D0 54 1 data input 0 1CE 55 1 clock enable input (active LOW) 1CP 56 1 clock pulse input (active rising edge) 7. Functional description 7.1 Function table Table 4: Function table [1] Operating mode Input Output nOE nMR nCE nCP nDx nQx Clear L L X X X L Load and read data L H L ↑ h H l L Hold L H H NC X NC High-impedance H X X X X Z [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition; 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions Max Unit −0.5 +4.6 V [1] −0.5 +7.0 V [1] −0.5 +7.0 V VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input diode current VI < 0 V - −50 mA IOK output diode current VO < 0 V - −50 mA 74ALVT162823_2 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 7 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Table 5: Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C Tstg storage temperature Tj junction temperature [2] [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC = 2.5 V VCC supply voltage 2.3 - 2.7 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 1.7 - - V VIL LOW-level input voltage - - 0.7 V IOH HIGH-level output current - - −8 mA IOL LOW-level output current - - 12 mA ∆t/∆V input transition rise or fall rate outputs enabled - - 10 ns/V Tamb ambient temperature in free air −40 - +85 °C VCC = 3.3 V VCC supply voltage 3.0 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current - - −12 mA IOL LOW-level output current - - 12 mA ∆t/∆V input transition rise or fall rate outputs enabled - - 10 ns/V Tamb ambient temperature in free air −40 - +85 °C 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 8 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C. Symbol Parameter VCC = 2.5 V ± 0.2 Conditions Min Typ Max Unit V [1] VIK input diode voltage VCC = 2.3 V; IIK = −18 mA - −0.85 −1.2 V VOH HIGH-level output voltage VCC = 2.3 V; IOH = −8 mA 1.7 2.5 - V VOL LOW-level output voltage VCC = 2.3 V; IOL = 12 mA - 0.3 0.5 V - 0.2 0.55 V - 0.1 ±1 µA VRST power-up LOW-state output voltage ILI input leakage current control pins VCC = 2.7 V; IO = 1 mA; VI = VCC or GND [2] VCC = 2.7 V; VI = GND - 0.1 10 µA VCC = 2.7 V; VI = 5.5 V [3] - 0.1 10 µA VCC = 2.7 V; VI = VCC [3] - 0.5 1 µA VCC = 2.7 V; VI = 0 V [3] - +0.1 −5 µA VCC = 2.7 V; VI = 5.5 V data pins IOFF IHOLD power-down output current bus hold current data inputs - +0.1 ±100 µA VCC = 2.5 V; VI = 0.7 V [4] - 100 - µA VCC = 2.5 V; VI = 1.7 V [4] - −70 - µA - 10 125 µA VCC = 0 V; VI or VO = 0 V to 4.5 V IEX external current into output output HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.5 V IPU power-up 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC [5] - 1 ±100 µA IPD power-down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC [5] - 1 ±100 µA IOZ 3-state output current VCC = 2.7 V; VI = VIL or VIH output HIGH-state; VO = 2.3 V - 0.5 5 µA output LOW-state; VO = 0.5 V - +0.5 −5 µA ICC quiescent supply current VCC = 2.7 V; VI = GND or VCC; IO = 0 A outputs HIGH-state - 0.04 0.1 mA outputs LOW-state - 2.7 4.5 mA [6] - 0.04 0.1 mA [7] - 0.04 0.4 mA outputs disabled ∆ICC additional quiescent supply current per input pin VCC = 2.3 V to 2.7 V; one input at VCC − 0.6 V, other inputs at VCC or GND Ci input capacitance VI = 0 V or VCC - 3 - pF Co output capacitance VI/O = 0 V or 3.0 V - 9 - pF VCC = 3.3 V ± 0.3 V [8] VIK input diode voltage VCC = 3.0 V; IIK = −18 mA - −0.85 −1.2 V VOH HIGH-level output voltage VCC = 3.0 V; IOH = −12 mA 2.0 2.3 - V VOL LOW-level output voltage VCC = 3.0 V; IOL = 12 mA - 0.5 0.8 V - - 0.55 V VRST power-up LOW-state output voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND 74ALVT162823_2 Product data sheet [2] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 9 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C. Symbol Parameter ILI Conditions Min Typ Max Unit VCC = 3.6 V; VI = VCC or GND - 0.1 ±1 µA input leakage current control pins - 0.1 10 µA VCC = 3.6 V; VI = 5.5 V [3] - 0.1 10 µA VCC = 3.6 V; VI = VCC [3] - 0.5 1 µA VCC = 3.6 V; VI = 0 V [3] - +0.1 −5 µA VCC = 0 V or 3.6 V; VI = 5.5 V data pins IOFF power-down output current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 µA IHOLD bus hold current data inputs VCC = 3 V; VI = 0.8 V [9] 75 130 - µA VCC = 3 V; VI = 2.0 V [9] −75 −140 - µA VCC = 3.6 V; VI = 0V to 3.6 V [9] ±500 - - µA - 10 125 µA IEX external current into output output HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IPU power-up 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC [10] - 1 ±100 µA IPD power-down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC [10] - 1 ±100 µA IOZ 3-state output current VCC = 3.6 V; VI = VIL or VIH output HIGH-state; VO = 3.0 V - 0.5 5 µA output LOW-state; VO = 0.5 V - +0.5 −5 µA - 0.05 0.1 mA quiescent supply current ICC VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH-state outputs LOW-state outputs disabled - 3.9 5.5 mA [6] - 0.06 0.1 mA [7] - 0.04 0.4 mA ∆ICC additional quiescent supply current per input pin VCC = 3 V to 3.6 V; one input at VCC − 0.6 V, other inputs at VCC or GND Ci input capacitance VI = 0 V or VCC - 3 - pF Co output capacitance VI/O = 0 V or 3.0 V - 9 - pF [1] All typical values are at VCC = 2.5 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] Not guaranteed. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [6] ICC is measured with outputs pulled up to VCC or pulled down to ground. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. [8] All typical values are at VCC = 3.3 V and Tamb = 25 °C. [9] This is the bus hold overdrive current required to force the input to the opposite logic state. [10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 10 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 11. Dynamic characteristics Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11; Tamb = −40 °C to +85 °C. Symbol Parameter Conditions Min Typ Max Unit see Figure 6 2.1 3.7 5.8 ns nCP to nQx see Figure 6 2.0 2.8 4.6 ns nMR to nQx VCC = 2.5 V ± 0.2 V [1] tPLH propagation delay nCP to nQx tPHL propagation delay see Figure 8 2.0 3.0 4.6 ns tPZH output enable time to HIGH-level see Figure 9 2.8 4.4 6.6 ns tPZL output enable time to LOW-level see Figure 10 2.0 3.4 5.2 ns tPHZ output disable time from HIGH-level see Figure 9 2.3 3.2 4.6 ns tPLZ output disable time from LOW-level see Figure 10 2.0 2.5 3.5 ns tsu(H) set-up time HIGH tsu(L) th(H) th(L) nDx to nCP see Figure 7 1.0 0.5 - ns nCE to nCP see Figure 7 1.0 0.2 - ns nDx to nCP see Figure 7 2.0 1.3 - ns nCE to nCP see Figure 7 +0.5 −0.1 - ns nDx to nCP see Figure 7 +0.1 −1.4 - ns nCE to nCP see Figure 7 1.0 0.2 - ns nDx to nCP see Figure 7 +0.1 −0.5 - ns nCE to nCP see Figure 7 +1.0 −0.1 - ns see Figure 6 2.0 0.8 - ns see Figure 6 3.0 2.1 - ns set-up time LOW hold time HIGH hold time LOW tWH pulse width HIGH nCP tWL pulse width LOW nCP see Figure 8 2.0 0.8 - ns see Figure 8 2.3 1.3 - ns see Figure 6 1.8 2.9 4.4 ns nCP to nQx see Figure 6 1.6 2.3 3.6 ns nMR to nQx see Figure 8 1.8 2.5 3.7 ns nMR trec recovery time nMR to nCP VCC = 3.3 V ± 0.3 V [2] tPLH propagation delay nCP to nQx tPHL propagation delay tPZH output enable time to HIGH-level see Figure 9 2.0 3.5 5.2 ns tPZL output enable time to LOW-level see Figure 10 1.7 2.8 3.8 ns tPHZ output disable time from HIGH-level see Figure 9 2.4 3.5 4.7 ns tPLZ output disable time from LOW-level see Figure 10 1.9 2.8 3.8 ns 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 11 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11; Tamb = −40 °C to +85 °C. Symbol Parameter tsu(H) tsu(L) th(H) th(L) Conditions Min Typ Max Unit nDx to nCP see Figure 7 1.0 0.5 - ns nCE to nCP see Figure 7 1.0 0.1 - ns nDx to nCP see Figure 7 1.6 1.1 - ns nCE to nCP see Figure 7 +0.5 −0.5 - ns nDx to nCP see Figure 7 +0.1 −0.5 - ns nCE to nCP see Figure 7 1.0 −0.1 - ns nDx to nCP see Figure 7 +0.1 −0.7 - ns nCE to nCP see Figure 7 1.0 0.5 - ns see Figure 6 1.5 0.7 - ns nCP see Figure 6 2.5 1.4 - ns nMR see Figure 8 2.0 1.5 - ns see Figure 8 2.0 1.1 - ns set-up time HIGH set-up time LOW hold time HIGH hold time LOW tWH pulse width HIGH nCP tWL pulse width LOW trec recovery time nMR to nCP [1] All typical values are measured at VCC = 2.5 V and Tamb = 25 °C. [2] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 12. Waveforms 1/f max VI VM input nCP VM 0V t WH t WL t PHL t PLH VOH VM output nQx VM 0V 001aad399 Measurement points are given in Table 9. VOH is a typical voltage output drop that occur with the output load. Fig 6. Propagation delay clock input (nCP) to output (nQx), clock pulse width and maximum clock frequency (nCP) 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 12 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state VI input nCP VM VM 0V t su(H) t h(H) t su(L) t h(L) VI input nDx, nCE VM VM VM VM 0V 001aad448 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Data set-up and hold times VI VM input nMR VM 0V t WL t rec VI input nCP VM 0V t PHL VOH VM output nQx 0V 001aad400 Measurement points are given in Table 9. VOH is a typical voltage output drop that occur with the output load. Fig 8. Master reset (MR) pulse width, propagation delay master reset (MR) to output (nQx) and master reset (MR) to clock (nCP) recovery time VI input nOE VM VM 0V t PZH t PHZ VOH output nQx VM VY 0V 001aad402 Measurement points are given in Table 9. VOH is a typical voltage output drop that occur with the output load. Fig 9. 3-state output enable time to HIGH-level and output disable time from HIGH-level 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 13 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state VI input nOE VM VM 0V t PZL t PLZ VI output nQx VM VX VOL 001aad404 Measurement points are given in Table 9. VOL is a typical voltage output drop that occur with the output load. Fig 10. 3-state output enable time to LOW-level and output disable time from LOW-level Table 9: Measurement points Supply voltage Input Output VM VM VX VY ≥3V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V ≤ 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.3 V VOH − 0.3 V 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 14 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state tW VI 90 % negative pulse 90 % VM VM 10 % 0V VI tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) 90 % positive pulse VM VM 10 % 0V 10 % tW 001aac221 Measurement points are given in Table 9. a. Input pulse definition VEXT VCC PULSE GENERATOR VI RL VO DUT CL RT RL mna616 Test data is given in Table 10. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. b. Test circuit Fig 11. Load circuitry for switching times Table 10: Test data Input Load VI fi tW tr, tf CL RL 3.0 V or VCC whichever is less ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω 6 V or 2 × VCC 74ALVT162823_2 Product data sheet VEXT tPLZ, tPZL tPLH, tPHL tPHZ, tPZH open GND © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 15 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 13. Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE v M A Z 29 56 Q A2 A1 A (A 3) θ pin 1 index Lp L 28 1 bp e 0 detail X w M 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-118 Fig 12. Package outline SOT371-1 (SSOP56) 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 16 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT364-1 (TSSOP56) 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 17 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 14. Revision history Table 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74ALVT162823_2 20050811 Product data sheet - - 74ALVT162823_1 Modifications: 74ALVT162823_1 • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • Section 2 “Features”: modified ‘Jedec Std 17’ into ‘JESD78’ Table 1 and Table 8: changed propagation delays. 19980827 Product specification - 74ALVT162823_2 Product data sheet 9397 750 03577 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 18 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Trademarks 17. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74ALVT162823_2 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 11 August 2005 19 of 20 74ALVT162823 Philips Semiconductors 18-bit bus-interface D-type flip-flop with reset and enable; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 11 August 2005 Document number: 74ALVT162823_2 Published in The Netherlands