74ALVT16601DGG,118

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74ALVT16601 18-bit universal bus transceiver; 3-state Rev. 03 — 5 July 2005 Product data sheet 1. General description The 74ALVT16601 is a high-performance Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) product designed for VCC operation at 2.5 V and 3.3 V with I/O compatibility up to 5 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock enable inputs (CEAB and CEBA). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 18-bit bidirectional bus interface 5 V I/O compatible 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Positive-edge triggered clock inputs Latch-up protection: ◆ JESD78: exceeds 500 mA ESD protection: ◆ MIL STD 883, method 3015: exceeds 2000 V ◆ Machine model: exceeds 200 V 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.5 V tPLH propagation delay An to Bn or Bn to An CL = 30 pF - 1.8 - ns tPHL propagation delay An to Bn or Bn to An CL = 30 pF - 2.2 - ns Ci input capacitance of control pins VI = 0 V or VCC 4 - pF Cio input/output capacitance of I/O pins VI/O = 0 V or VCC; outputs disabled 8 - pF ICC supply current outputs disabled - 40 - µA VCC = 3.3 V tPLH propagation delay An to Bn or Bn to An CL = 50 pF - 1.9 - ns tPHL propagation delay An to Bn or Bn to An CL = 50 pF - 2 - ns Ci input capacitance of control pins VI = 0 V or VCC 4 - pF Cio input/output capacitance of I/O pins VI/O = 0 V or VCC; outputs disabled 8 - pF ICC supply current outputs disabled 60 - µA - 4. Ordering information Table 2: Ordering information Type number 74ALVT16601DL Package Temperature range Name Description Version −40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 74ALVT16601DGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm 74ALVT16601_3 Product data sheet SOT364-1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 2 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 5. Functional diagram OEAB CEAB CPAB LEAB A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 3 54 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 OEAB LEAB CPAB 1 CEAB 2 55 56 29 30 28 27 1 56 55 2 EN1 G2 2C3 C3 G2 B0 OEBA B1 CEBA B2 CPBA B3 LEBA B4 27 29 30 28 EN4 G5 5C6 C6 G5 B5 B6 A0 3 3D 1 4 6D B7 B8 A1 B9 A2 B10 B11 A3 B12 A4 B13 A5 B14 A6 B15 A7 B16 A8 B17 A9 A10 OEBA LEBA CPBA A11 A12 CEBA A13 001aad316 A14 A15 A16 A17 54 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 001aad317 Fig 1. Logic symbol Fig 2. IEC logic symbol 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 3 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state OEAB CEAB CPAB LEAB LEBA CPBA CEBA OEBA A0 1 56 55 2 28 30 29 27 CE ID C1 CLK 3 54 B0 CE ID C1 CLK to 17 other channels 001aad249 Fig 3. Logic diagram 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 4 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 6. Pinning information 6.1 Pinning OEAB 1 56 CEAB LEAB 2 55 CPAB A0 3 54 B0 GND 4 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 A3 8 50 VCC 49 B3 A4 9 48 B4 A5 10 47 B5 GND 11 46 GND A6 12 45 B6 A7 13 44 B7 A8 14 43 B8 16601 A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 A15 23 35 VCC 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CPBA LEBA 28 29 CEBA 001aad247 Fig 4. Pin configuration 6.2 Pin description Table 3: Pin description Symbol Pin Description OEAB 1 A-to-B output enable input (active LOW) LEAB 2 A-to-B latch enable input A0 3 data input or output (A side) GND 4 ground (0 V) A1 5 data input or output (A side) A2 6 data input or output (A side) VCC 7 voltage supply A3 8 data input or output (A side) 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 5 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state Table 3: Pin description …continued Symbol Pin Description A4 9 data input or output (A side) A5 10 data input or output (A side) GND 11 ground (0 V) A6 12 data input or output (A side) A7 13 data input or output (A side) A8 14 data input or output (A side) A9 15 data input or output (A side) A10 16 data input or output (A side) A11 17 data input or output (A side) GND 18 ground (0 V) A12 19 data input or output (A side) A13 20 data input or output (A side) A14 21 data input or output (A side) VCC 22 voltage supply A15 23 data input or output (A side) A16 24 data input or output (A side) GND 25 ground (0 V) A17 26 data input or output (A side) OEBA 27 B-to-A output enable input (active LOW) LEBA 28 B-to-A latch enable input CEBA 29 B-to-A clock enable (active LOW) CPBA 30 B-to-A clock input (active rising edge) B17 31 data input or output (B side) GND 32 ground (0 V) B16 33 data input or output (B side) B15 34 data input or output (B side) VCC 35 voltage supply B14 36 data input or output (B side) B13 37 data input or output (B side) B12 38 data input or output (B side) GND 39 ground (0 V) B11 40 data input or output (B side) B10 41 data input or output (B side) B9 42 data input or output (B side) B8 43 data input or output (B side) B7 44 data input or output (B side) B6 45 data input or output (B side) GND 46 ground (0 V) B5 47 data input or output (B side) B4 48 data input or output (B side) B3 49 data input or output (B side) 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 6 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state Table 3: Pin description …continued Symbol Pin Description VCC 50 voltage supply B2 51 data input or output (B side) B1 52 data input or output (B side) GND 53 ground (0 V) B0 54 data input or output (B side) CPAB 55 A-to-B clock input (active rising edge) CEAB 56 A-to-B clock enable (active LOW) 7. Functional description 7.1 Function table Table 4: Function table [1] Control Input Output CEAB OEAB LEAB CPAB An Bn CEBA OEBA LEBA CPBA Bn An X H X X X Z X L H X L L H H L L L L L ↑ H H L L L H X Y [2] L X Y [3] X X Y [2] H L L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition [2] Output level before the indicated steady-state input conditions were established. [3] Output level before the indicated steady-state input conditions were established, provided that CPAB or CPBA was LOW before LEAB or LEBA went LOW. 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Conditions Max Unit −0.5 +4.6 V input voltage [1] −0.5 +7.0 V output voltage [1] −0.5 +7.0 V supply voltage output in OFF-state or HIGH-state 74ALVT16601_3 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 7 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state Table 5: Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit IIK input diode current VI < 0 V - −50 mA IOK output diode current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C storage temperature Tstg [2] junction temperature Tj [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC = 2.5 V ± 0.2 V VCC supply voltage 2.3 - 2.7 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 1.7 - - V VIL LOW-level input voltage - - 0.7 V IOH HIGH-level output current IOL LOW-level output current ∆t/∆V input transition rise or fall rate Tamb ambient temperature - - −8 mA none - - 8 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 24 mA outputs enabled - - 10 ns/V −40 - +85 °C VCC = 3.3 V ± 0.3 V VCC supply voltage 3.0 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current IOL LOW-level output current - - −32 mA none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA ∆t/∆V input transition rise or fall rate outputs enabled - - 10 ns/V Tamb ambient temperature in free air −40 - +85 °C 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 8 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C . Symbol Parameter VCC = 2.5 V ± 0.2 Conditions Min Typ Max Unit −0.85 −1.2 V - V V [1] VIK input diode voltage VCC = 2.3 V; IIK = −18 mA - VOH HIGH-level output voltage VCC = 2.3 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC = 2.3 V; IOH = −8 mA 1.8 - V VOL LOW-level output voltage VCC = 2.3 V; IOL = 100 µA - 0.07 0.2 V VCC = 2.3 V; IOL = 24 mA - 0.3 0.5 V - - 0.4 V - - 0.55 V - 0.1 ±1 µA VCC = 2.3 V; IOL = 8 mA VRST power-up LOW-state output voltage VCC = 2.7 V; IO = 1 mA; VI = VCC or GND ILI input leakage current control pins [2] VCC = 2.7 V; VI = VCC or GND 0.1 10 µA VCC = 0 V or 2.7 V; VI = 5.5 V [3] - 0.1 20 µA VCC = 2.7 V; VI = VCC [3] - 0.1 10 µA VCC = 2.7 V; VI = 0 V [3] - +0.1 −5 µA VCC = 0 V or 2.7 V; VI = 5.5 V I/O data pins IOFF power-down leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 µA IHOLD bus hold current data inputs VCC = 2.3 V; VI = 0.7 V [4] - 90 - µA VCC = 2.3 V; VI = 1.7 V [4] - −75 - µA - 10 125 µA - 1 100 µA - 0.04 0.1 mA IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V IPU, IPD power-up/down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEAB or OEAB don’t care ICC supply current VCC = 2.7 V; VI = GND or VCC; IO = 0 A [5] outputs HIGH-state outputs LOW-state outputs disabled ∆ICC additional supply current per input pin VCC = 2.3 V to 2.7 V; one input at VCC − 0.6 V, other inputs at VCC or GND Ci input capacitance of control pins VI = 0 V or VCC Cio input/output capacitance of I/O pins VI/O = 0 V or VCC; outputs disabled - 2.5 4.5 mA [6] - 0.04 0.1 mA [7] - 0.01 0.4 mA 4 - pF 8 - pF −0.85 −1.2 V VCC = 3.3 V ± 0.3 V [8] VIK input diode voltage VCC = 3.0 V; IIK = −18 mA - VOH HIGH-level output voltage VCC = 3.0 V to 3.6 V; IOH = −100 µA VCC − VCC 0.2 - V VCC = 3.0 V; IOH = −32 mA 2.0 - V 74ALVT16601_3 Product data sheet 2.3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 9 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °C to +85 °C . Symbol Parameter Conditions Min Typ Max Unit VOL VCC = 3.0 V; IOL = 100 µA - 0.07 0.2 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V - 0.4 0.55 V - - 0.55 V - 0.1 ±1 µA LOW-level output voltage VCC = 3.0 V; IOL = 64 mA VRST power-up LOW-state output voltage VCC = 2.7 V; IO = 1 mA; VI = VCC or GND ILI input leakage current control pins [2] VCC = 3.6 V; VI = VCC or GND - 0.1 10 µA VCC = 3.6 V; VI = 5.5 V [3] - 0.1 20 µA VCC = 3.6 V; VI = VCC [3] - 0.5 10 µA VCC = 3.6 V; VI = 0 V [3] - +0.1 −5 µA - 0.1 ±100 µA VCC = 0 V or 3.6 V; VI = 5.5 V I/O data pins power-down leakage current IOFF IHOLD bus hold current data inputs VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3 V; VI = 0.8 V [9] 75 130 - µA VCC = 3 V; VI = 2.0 V [9] −75 −140 - µA VCC = 0 V to 3.6 V; VCC = 3.6 V [9] ±500 - - µA - 10 125 µA - 1 ±100 µA - 0.06 0.1 mA IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 2.3 V IPU, IPD power-up/down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEAB or OEAB don’t care ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A [10] outputs HIGH-state outputs LOW-state outputs disabled ∆ICC additional supply current per input pin VCC = 3 V to 3.6 V; one input at VCC − 0.6 V, other inputs at VCC or GND Ci input capacitance of control pins VI = 0 V or VCC Cio input/output capacitance of I/O pins VI/O = 0 V or VCC; outputs disabled - 3.5 5 mA [6] - 0.06 0.1 mA [7] - 0.04 0.4 mA 4 - pF 8 - pF [1] All typical values are at VCC = 2.5 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] Not guaranteed. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 2.5 V ± 0.2 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [6] ICC is measured with outputs pulled up to VCC or pulled down to ground. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. [8] All typical values are at VCC = 3.3 V and Tamb = 25 °C. [9] This is the bus hold overdrive current required to force the input to the opposite logic state. [10] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 10 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 11. Dynamic characteristics Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Tamb = −40 °C to +85 °C. Symbol Parameter Conditions Min Typ Max Unit An to Bn or Bn to An see Figure 5 1.4 2.2 3.5 ns LEAB to Bn or LEBA to An see Figure 6 1.5 2.5 4.0 ns CPAB to Bn or CPBA to An see Figure 7 1.9 3.2 5.2 ns An to Bn or Bn to An see Figure 5 1.0 1.8 3.0 ns LEAB to Bn or LEBA to An see Figure 6 1.5 2.5 4.0 ns VCC = 2.5 V ± 0.2 tPHL tPLH V [1]; CL = 30 pF propagation delay propagation delay see Figure 7 2.2 3.5 5.0 ns tPHZ output disable time from HIGH-level see Figure 9 2.2 3.1 4.4 ns tPLZ output disable time from LOW-level see Figure 10 1.6 2.3 3.4 ns tPZH output enable time to HIGH-level see Figure 9 2.3 3.6 4.8 ns tPZL output enable time to LOW-level see Figure 10 1.9 2.9 4.4 ns th(H) hold time HIGH An to CPAB or Bn to CPBA see Figure 8 0.0 −1.1 - ns An to LEAB or Bn to LEAB see Figure 8 1.5 0.4 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 2.0 0.4 - ns An to CPAB or Bn to CPBA see Figure 8 0.0 −0.3 - ns An to LEAB or Bn to LEAB see Figure 8 1.9 1.0 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 +0.8 −0.1 - ns An to CPAB or Bn to CPBA see Figure 8 2.0 0.4 - ns An to LEAB or Bn to LEBA see Figure 8 0.0 −1.0 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 0.7 0.3 - ns An to CPAB or Bn to CPBA see Figure 8 2.0 1.2 - ns An to LEAB or Bn to LEBA see Figure 8 1.5 0.4 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 +0.3 −0.4 - ns CPAB or CPBA see Figure 7 3.0 - - ns LEAB or LEBA see Figure 6 1.5 - - ns see Figure 7 3.0 - - ns CPAB to Bn or CPBA to An th(L) tsu(H) tsu(L) tWH tWL hold time LOW set-up time HIGH set-up time LOW pulse width HIGH pulse width LOW CPAB or CPBA 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 11 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Tamb = −40 °C to +85 °C. Symbol Parameter Conditions Min Typ Max Unit An to Bn or Bn to An see Figure 5 1.1 2.0 2.8 ns LEAB to Bn or LEBA to An see Figure 6 1.4 2.3 3.6 ns CPAB to Bn or CPBA to An see Figure 7 1.7 2.7 4.1 ns An to Bn or Bn to An see Figure 5 1.2 1.9 2.9 ns LEAB to Bn or LEBA to An see Figure 6 1.5 2.5 3.8 ns CPAB to Bn or CPBA to An see Figure 7 2.1 3.1 4.5 ns VCC = 3.3 V ± 0.3 V [2]; CL = 50 pF propagation delay tPHL propagation delay tPLH tPHZ output disable time from HIGH-level see Figure 9 2.7 3.6 4.9 ns tPLZ output disable time from LOW-level see Figure 10 2.1 2.8 4 ns tPZH output enable time to HIGH-level see Figure 9 2.2 3.2 4.2 ns tPZL output enable time to LOW-level see Figure 10 1.6 2.5 3.8 ns th(H) hold time HIGH An to CPAB or Bn to CPBA see Figure 8 +1.0 −0.5 - ns An to LEAB or Bn to LEAB see Figure 8 1.5 0.1 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 1.5 0.7 - ns An to CPAB or Bn to CPBA see Figure 8 +1.0 −0.3 - ns An to LEAB or Bn to LEAB see Figure 8 1.5 0.5 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 +1.0 −0.3 - ns An to CPAB or Bn to CPBA see Figure 8 1.5 0.4 - ns An to LEAB or Bn to LEBA see Figure 8 +1.0 −0.5 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 1.5 0.3 - ns An to CPAB or Bn to CPBA see Figure 8 1.5 0.6 - ns An to LEAB or Bn to LEBA see Figure 8 +1.0 −0.1 - ns CEAB to CPAB or CEBA to CPBA see Figure 8 1.0 −0.4 - ns CPAB or CPBA see Figure 7 2.0 - - ns LEAB or LEBA see Figure 6 1.5 - - ns see Figure 7 2.0 - - ns hold time LOW th(L) tsu(H) tsu(L) set-up time HIGH set-up time LOW pulse width HIGH tWH pulse width LOW tWL CPAB or CPBA [1] All typical values are measured at VCC = 2.5 V and Tamb = 25 °C. [2] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 12 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 12. Waveforms VI input An or Bn VM VM 0V t PLH t PHL VOH output Bn or An VM VM VOL 001aad308 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode VI input LEAB or LEBA VM VM VM 0V t WH t PHL t PLH VOH output An or Bn VM VM VOL 001aad310 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable (LEAB, LEBA) pulse width 1/f max VI input CPBA or CPAB VM VM VM 0V t WH t WL t PHL t PLH VOH output An or Bn VM VOL VM 001aad254 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Propagation delay clock input (CPAB, CPBA) to output (An, Bn), clock pulse width (CPAB, CPBA) and maximum clock frequency (CPAB, CPBA) 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 13 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state input LEAB or LEBA, CPAB or CPBA VI VM VM 0V t su(H) t h(H) t su(L) t h(L) VI input An, Bn, VM CEAB, CEBA VM VM VM 0V 001aad255 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 8. Data set-up and hold times VI input OEBA or OEAB VM VM 0V t PZH t PHZ VOH output An or Bn VY VM 0V 001aad309 Measurement points are given in Table 9. VOH is typical voltage output drop that occur with the output load. Fig 9. 3-state output enable time to HIGH-level and output disable time from HIGH-level VI input OEBA or OEAB VM VM 0V t PZL t PLZ 3.0 V or VCC output An or Bn VM VX VOL 001aad311 Measurement points are given in Table 9. VOL is typical voltage output drop that occur with the output load. Fig 10. 3-state output enable time to LOW-level and output disable time from LOW-level 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 14 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state Table 9: Measurement points Supply voltage Input Output VM VM VX VY ≥3V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V ≤ 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V tW VI 90 % negative pulse 90 % VM VM 10 % 0V VI tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) 90 % positive pulse VM VM 10 % 0V 10 % tW 001aac221 Measurement points are given in Table 9. a. Input pulse definition VEXT VCC PULSE GENERATOR VI RL VO DUT CL RT RL mna616 Test data is given in Table 10. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. b. Test circuit Fig 11. Load circuitry for switching times Table 10: Test data Input Load VI fi tW tr, tf CL RL 3.0 V or VCC whichever is less ≤ 10 MHz 500 ns ≤ 2.5 ns 30 pF or 50 pF 500 Ω 6 V or 2 × VCC 74ALVT16601_3 Product data sheet VEXT tPLZ, tPZL tPLH, tPHL tPHZ, tPZH open GND © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 15 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 13. Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE v M A Z 29 56 Q A2 A1 A (A 3) θ pin 1 index Lp L 28 1 bp e 0 detail X w M 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-118 Fig 12. Package outline SOT371-1 (SSOP56) 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 16 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT364-1 (TSSOP56) 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 17 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 14. Revision history Table 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74ALVT16601_3 20050705 Product data sheet - - 74ALVT16601_2 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • Section 2 “Features”: modified ‘JEDEC Std 17’ into ‘JESD78’. Table 8 “Dynamic characteristics”: changed values of propagation delay, output enable and output disable time. 74ALVT16601_2 19980213 Product specification - 9397 750 03571 74ALVT16601_1 74ALVT16601_1 - - - - - 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 18 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. Trademarks 17. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74ALVT16601_3 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 03 — 5 July 2005 19 of 20 74ALVT16601 Philips Semiconductors 18-bit universal bus transceiver; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 5 July 2005 Document number: 74ALVT16601_3 Published in The Netherlands