74AUP1G02GS,132

74AUP1G02 Low-power 2-input NOR gate Rev. 7 — 21 January 2015 Product data sheet 1. General description The 74AUP1G02 provides the single 2-input NOR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 0.8 V to 3.6 V  High noise immunity  Complies with JEDEC standards:  JESD8-12 (0.8 V to 1.3 V)  JESD8-11 (0.9 V to 1.65 V)  JESD8-7 (1.2 V to 1.95 V)  JESD8-5 (1.8 V to 2.7 V)  JESD8-B (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F Class 3A exceeds 5000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Low static power consumption; ICC = 0.9 A (maximum)  Latch-up performance exceeds 100 mA per JESD 78 Class II  Inputs accept voltages up to 3.6 V  Low noise overshoot and undershoot < 10 % of VCC  IOFF circuitry provides partial Power-down mode operation  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G02GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G02GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74AUP1G02GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1  1  0.5 mm 74AUP1G02GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74AUP1G02GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74AUP1G02GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8  0.8  0.35 mm SOT1226 4. Marking Table 2. Marking Marking code[1] Type number 74AUP1G02GW pB 74AUP1G02GM pB 74AUP1G02GF pB 74AUP1G02GN pB 74AUP1G02GS pB 74AUP1G02GX pB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram %  %  $ <   •  <  $ Fig 1. Logic symbol 74AUP1G02 Product data sheet PQD PQD PQD Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 Fig 3. Logic diagram © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate 6. Pinning information 6.1 Pinning $83* $83* %  $  *1'   9&&  < %   9&& $   QF *1'   < DDI 7UDQVSDUHQWWRSYLHZ DDI Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886 $83* $83*  % %   9&& $   QF *1'   < 9&&  <  *1'  $ DDI DDD 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ Fig 6.  Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Symbol Pin description Pin Description TSSOP5 and X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74AUP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate 7. Functional description Table 4. Function table[1] Input Output A B Y L L H L H L H L L H H L [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions Min 0.5 +4.6 V VI < 0 V 50 - mA 0.5 +4.6 V - 50 mA 0.5 +4.6 V - 20 mA [1] VO > VCC or VO < 0 V [1] Max Unit VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 250 mW [1] [2] Tamb = 40 C to +125 C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC VI VO output voltage Conditions Min Max Unit supply voltage 0.8 3.6 V input voltage 0 3.6 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V 40 +125 C VCC = 0.8 V to 3.6 V 0 200 ns/V Tamb ambient temperature t/V input transition rise and fall rate 74AUP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70  VCC - - V VCC = 0.9 V to 1.95 V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30  VCC V VCC = 0.9 V to 1.95 V - - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.75  VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.11 - - V Tamb = 25 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = 1.9 mA; VCC = 1.65 V 1.32 - - V IO = 2.3 mA; VCC = 2.3 V 2.05 - - V IO = 3.1 mA; VCC = 2.3 V 1.9 - - V IO = 2.7 mA; VCC = 3.0 V 2.72 - - V IO = 4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - VI = VIH or VIL 0.3  VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.2 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 40 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF 74AUP1G02 Product data sheet [1] All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.70  VCC - - V VCC = 0.9 V to 1.95 V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V - - 0.30  VCC V 0.35  VCC V Tamb = 40 C to +85 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.7  VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.03 - - V IO = 1.9 mA; VCC = 1.65 V 1.30 - - V IO = 2.3 mA; VCC = 2.3 V 1.97 - - V IO = 3.1 mA; VCC = 2.3 V 1.85 - - V IO = 2.7 mA; VCC = 3.0 V 2.67 - - V IO = 4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - VI = VIH or VIL 0.3  VCC V 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.6 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 50 A 74AUP1G02 Product data sheet [1] All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCC = 0.8 V 0.75  VCC - - V VCC = 0.9 V to 1.95 V 0.70  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V - - 0.25  VCC V 0.30  VCC V Tamb = 40 C to +125 C HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL VCC = 0.8 V VCC = 0.9 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.11 - - V IO = 1.1 mA; VCC = 1.1 V 0.6  VCC - - V IO = 1.7 mA; VCC = 1.4 V 0.93 - - V IO = 1.9 mA; VCC = 1.65 V 1.17 - - V IO = 2.3 mA; VCC = 2.3 V 1.77 - - V IO = 3.1 mA; VCC = 2.3 V 1.67 - - V IO = 2.7 mA; VCC = 3.0 V 2.40 - - V IO = 4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - IO = 1.7 mA; VCC = 1.4 V - - VI = VIH or VIL 0.33  VCC V 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 75 A [1] [1] One input at VCC  0.6 V, other input at VCC or GND. 74AUP1G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter Min Typ [1] Max - 17.0 - ns VCC = 1.1 V to 1.3 V 2.5 5.1 10.8 ns VCC = 1.4 V to 1.6 V 1.6 3.7 6.7 ns Conditions Unit Tamb = 25 C; CL = 5 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 1.3 3.0 5.3 ns VCC = 2.3 V to 2.7 V 1.0 2.4 3.9 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.4 ns - 20.4 - ns VCC = 1.1 V to 1.3 V 2.4 6.0 12.8 ns VCC = 1.4 V to 1.6 V 1.9 4.3 7.9 ns Tamb = 25 C; CL = 10 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 1.6 3.6 6.2 ns VCC = 2.3 V to 2.7 V 1.4 3.0 4.7 ns VCC = 3.0 V to 3.6 V 1.3 2.7 4.2 ns - 23.9 - ns VCC = 1.1 V to 1.3 V 3.4 6.8 14.6 ns VCC = 1.4 V to 1.6 V 2.3 4.8 8.9 ns Tamb = 25 C; CL = 15 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V VCC = 1.65 V to 1.95 V 1.9 4.0 7.0 ns VCC = 2.3 V to 2.7 V 1.7 3.4 5.4 ns VCC = 3.0 V to 3.6 V 1.6 3.2 4.8 ns - 34.2 - ns VCC = 1.1 V to 1.3 V 4.6 9.0 19.9 ns VCC = 1.4 V to 1.6 V 3.4 6.4 11.8 ns Tamb = 25 C; CL = 30 pF tpd propagation delay A, B to Y; see Figure 8 [2] VCC = 0.8 V 74AUP1G02 Product data sheet VCC = 1.65 V to 1.95 V 2.6 5.3 9.3 ns VCC = 2.3 V to 2.7 V 2.4 4.5 7.1 ns VCC = 3.0 V to 3.6 V 2.3 4.2 6.4 ns All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = 25 C power dissipation capacitance f = 1 MHz; VI = GND to VCC CPD VCC = 0.8 V - 2.6 - pF VCC = 1.1 V to 1.3 V - 2.7 - pF VCC = 1.4 V to 1.6 V - 2.9 - pF VCC = 1.65 V to 1.95 V - 3.1 - pF VCC = 2.3 V to 2.7 V - 3.5 - pF VCC = 3.0 V to 3.6 V - 4.1 - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC = 1.1 V to 1.3 V 2.1 12.1 2.1 13.4 ns VCC = 1.4 V to 1.6 V 1.4 7.8 1.4 8.6 ns VCC = 1.65 V to 1.95 V 1.1 6.2 1.1 6.9 ns VCC = 2.3 V to 2.7 V 0.9 4.6 0.9 5.1 ns VCC = 3.0 V to 3.6 V 0.8 4.0 0.8 4.4 ns VCC = 1.1 V to 1.3 V 2.2 14.3 2.2 15.8 ns VCC = 1.4 V to 1.6 V 1.7 9.2 1.7 10.2 ns VCC = 1.65 V to 1.95 V 1.5 7.3 1.5 8.1 ns VCC = 2.3 V to 2.7 V 1.2 5.6 1.2 6.2 ns VCC = 3.0 V to 3.6 V 1.2 5.0 1.2 5.5 ns CL = 5 pF tpd propagation delay A, B to Y; see Figure 8 [1] CL = 10 pF tpd propagation delay 74AUP1G02 Product data sheet A, B to Y; see Figure 8 [1] All information provided in this document is subject to legal disclaimers. Rev. 7 — 21 January 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 21 74AUP1G02 NXP Semiconductors Low-power 2-input NOR gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC = 1.1 V to 1.3 V 3.1 16.4 3.1 18.1 ns VCC = 1.4 V to 1.6 V 2.0 10.4 2.0 11.5 ns VCC = 1.65 V to 1.95 V 1.7 8.3 1.7 9.2 ns VCC = 2.3 V to 2.7 V 1.5 6.3 1.5 7.0 ns VCC = 3.0 V to 3.6 V 1.4 5.7 1.4 6.3 ns CL = 15 pF propagation delay tpd [1] A, B to Y; see Figure 8 CL = 30 pF propagation delay tpd [1] [1] A, B to Y; see Figure 8 VCC = 1.1 V to 1.3 V 4.1 22.4 4.1 24.7 ns VCC = 1.4 V to 1.6 V 2.9 13.9 2.9 15.3 ns VCC = 1.65 V to 1.95 V 2.3 11.1 2.3 12.3 ns VCC = 2.3 V to 2.7 V 2.1 8.5 2.1 9.4 ns VCC = 3.0 V to 3.6 V 2.1 7.7 2.1 8.5 ns tpd is the same as tPLH and tPHL. 12. Waveforms 9, 90 $%LQSXW *1' W 3+/ W 3/+ 92+ 90