74AVCH1T45

74AVCH1T45 Dual supply translating transceiver; 3-state Rev. 02 — 5 May 2009 Product data sheet 1. General description The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. The 74AVCH1T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features I Wide supply voltage range: N VCC(A): 0.8 V to 3.6 V N VCC(B): 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3B exceeds 8000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Maximum data rates: N 500 Mbit/s (1.8 V to 3.3 V translation) N 320 Mbit/s (< 1.8 V to 3.3 V translation) N 320 Mbit/s (translate to 2.5 V or 1.8 V) N 280 Mbit/s (translate to 1.5 V) NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state I I I I I I I I N 240 Mbit/s (translate to 1.2 V) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AVCH1T45GW 74AVCH1T45GM −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 4. Marking Table 2. Marking Marking code[1] K5 K5 Type number 74AVCH1T45GW 74AVCH1T45GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram DIR 5 DIR 3 A 4 VCC(A) VCC(B) VCC(A) 001aag885 A B B VCC(B) 001aag886 Fig 1. Logic symbol Fig 2. Logic diagram 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 2 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 6. Pinning information 6.1 Pinning 74AVCH1T45 74AVCH1T45 VCC(A) GND 1 2 6 5 VCC(B) DIR A A 3 001aag887 VCC(A) 1 6 VCC(B) GND 2 5 DIR 3 4 B 4 B 001aag888 Transparent top view Fig 3. Pin configuration SOT363 Fig 4. Pin configuration SOT886 6.2 Pin description Table 3. Symbol VCC(A) GND A B DIR VCC(B) Pin description Pin 1 2 3 4 5 6 Description supply voltage port A and DIR ground (0 V) data input or output data input or output direction control supply voltage port B 7. Functional description Table 4. Function table[1] Input DIR[3] L H X Input/output[2] A A=B input Z B input B=A Z Supply voltage VCC(A), VCC(B) 0.8 V to 3.6 V 0.8 V to 3.6 V GND[4] [1] [2] [3] [4] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. The input circuit of the data I/O is always active. The DIR input circuit is referenced to VCC(A). If at least one of VCC(A) or VCC(B) is at GND level, the device goes into Suspend mode. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 3 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC(A) VCC(B) IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] [4] Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +4.6 +4.6 +4.6 VCCO + 0.5 +4.6 ±50 100 +150 250 Unit V V mA V mA V V mA mA mA °C mW VI < 0 V [1] −50 −0.5 −50 [1][2][3] [1] VO < 0 V Active mode Suspend or 3-state mode VO = 0 V to VCCO ICC(A) or ICC(B) −0.5 −0.5 −100 −65 Tamb = −40 °C to +125 °C [4] - The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 4.6 V. For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC(A) VCC(B) VI VO Tamb ∆t/∆V [1] [2] Recommended operating conditions Parameter supply voltage A supply voltage B input voltage output voltage ambient temperature input transition rise and fall rate VCCI = 0.8 V to 3.6 V [2] Conditions Min 0.8 0.8 0 Max 3.6 3.6 3.6 VCCO 3.6 +125 5 Unit V V V V V °C ns/V Active mode Suspend or 3-state mode [1] 0 0 −40 - VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 4 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VOH VOL II IBHL IBHH IBHLO IBHHO IOZ IOFF HIGH-level output voltage LOW-level output voltage input leakage current bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current OFF-state output current power-off leakage current VI = VIH or VIL IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V VI = VIH or VIL IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V DIR input; VI = 0 V to 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V A or B port; VCC(A) = VCC(B) = 1.2 V A or B port; VCC(A) = VCC(B) = 1.2 V A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V CI CI/O input capacitance input/output capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V 0.7VCC(A) 0.65VCC(A) 1.6 2 V V V V [3] [1] Conditions Min Typ Max Unit - 0.69 0.07 ±0.025 26 −24 28 −26 ±0.5 ±0.1 ±0.1 1 4 ±0.25 ±2.5 ±1 ±1 - V V µA µA µA µA µA µA µA µA pF pF [1] [2] Tamb = −40 °C to +85 °C VIH HIGH-level input voltage 0.7VCCI 0.65VCCI 1.6 2 V V V V 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 5 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V II IBHL input leakage current bus hold LOW current DIR input; VI = 0 V to 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V IBHH bus hold HIGH current A or B port VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −15 −25 −45 −100 µA µA µA µA 15 25 45 100 µA µA µA µA 0.1 0.25 0.35 0.45 0.55 0.7 ±1 V V V V V V µA [2] [3] Min VCCO − 0.1 0.85 1.05 1.2 1.75 2.3 Typ - Max 0.3VCCI 0.35VCCI 0.7 0.9 0.3VCC(A) 0.35VCC(A) 0.7 0.9 - Unit V V V V V V V V V V V V V V 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 6 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHLO bus hold LOW overdrive current Conditions A or B port VCC(A) = VCC(B) = 1.6 V VCC(A) = VCC(B) = 1.95 V VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current A or B port VCC(A) = VCC(B) = 1.6 V VCC(A) = VCC(B) = 1.95 V VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V IOZ IOFF OFF-state output current power-off leakage current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V ICC supply current A port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V Tamb = −40 °C to +125 °C VIH HIGH-level input voltage data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V 0.7VCC(A) 0.65VCC(A) 1.6 2 V V V V [3] [3] [3] [3] [2] [1] [1] Min 125 200 300 500 −125 −200 −300 −500 - Typ - Max ±5 ±5 ±5 Unit µA µA µA µA µA µA µA µA µA µA µA −2 −2 - 0 0 - 8.0 8.0 8.0 8.0 16 µA µA µA µA µA µA µA 0.7VCCI 0.65VCCI 1.6 2 - - V V V V 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 7 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions data input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V DIR input VCCI = 0.8 V VCCI = 1.1 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = −3 mA; VCC(A) = VCC(B) = 1.1 V IO = −6 mA; VCC(A) = VCC(B) = 1.4 V IO = −8 mA; VCC(A) = VCC(B) = 1.65 V IO = −9 mA; VCC(A) = VCC(B) = 2.3 V IO = −12 mA; VCC(A) = VCC(B) = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC(A) = VCC(B) = 0.8 V to 3.6 V IO = 3 mA; VCC(A) = VCC(B) = 1.1 V IO = 6 mA; VCC(A) = VCC(B) = 1.4 V IO = 8 mA; VCC(A) = VCC(B) = 1.65 V IO = 9 mA; VCC(A) = VCC(B) = 2.3 V IO = 12 mA; VCC(A) = VCC(B) = 3.0 V II IBHL input leakage current bus hold LOW current DIR input; VI = 0 V to 3.6 V; VCC(A) = VCC(B) = 0.8 V to 3.6 V A or B port VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V VI = 0.58 V; VCC(A) = VCC(B) = 1.65 V VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V IBHH bus hold HIGH current A or B port VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V VI = 1.07 V; VCC(A) = VCC(B) = 1.65 V VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V −15 −25 −45 −100 µA µA µA µA 15 25 45 90 µA µA µA µA 0.1 0.25 0.35 0.45 0.55 0.7 ±1.5 V V V V V V µA [2] [3] Min VCCO − 0.1 0.85 1.05 1.2 1.75 2.3 Typ - Max 0.3VCCI 0.35VCCI 0.7 0.9 0.3VCC(A) 0.35VCC(A) 0.7 0.9 - Unit V V V V V V V V V V V V V V 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 8 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHLO bus hold LOW overdrive current Conditions A or B port VCC(A) = VCC(B) = 1.6 V VCC(A) = VCC(B) = 1.95 V VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V IBHHO bus hold HIGH overdrive current A or B port VCC(A) = VCC(B) = 1.6 V VCC(A) = VCC(B) = 1.95 V VCC(A) = VCC(B) = 2.7 V VCC(A) = VCC(B) = 3.6 V IOZ IOFF OFF-state output current power-off leakage current A or B port; VO = 0 V or VCCO; VCC(A) = VCC(B) = 0.8 V to 3.6 V A port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V ICC supply current A port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = 0 V or VCCI; IO = 0 A VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V VCC(A) = 3.6 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = 0.8 V to 3.6 V; VCC(B) = 0.8 V to 3.6 V [1] [2] [3] [3] [3] [3] [2] [1] [1] Min 125 200 300 500 −125 −200 −300 −500 - Typ - Max ±7.5 ±35 ±35 Unit µA µA µA µA µA µA µA µA µA µA µA −8 −8 - 0 0 - 12 12 12 12 24 µA µA µA µA µA µA µA In order to guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH. VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 9 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 11. Dynamic characteristics Table 8. Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter tpd tdis ten Conditions 0.8 V propagation delay A to B B to A disable time enable time DIR to A DIR to B DIR to A DIR to B [1] VCC(B) 1.2 V 8.4 12.7 12.2 7.9 20.6 20.6 1.5 V 8.0 12.4 12.2 7.6 20.0 20.2 1.8 V 8.0 12.2 12.2 8.2 20.4 20.2 2.5 V 8.7 12.0 12.2 8.7 20.7 20.9 3.3 V 9.5 11.8 12.2 10.2 22.0 21.7 15.8 15.8 12.2 11.7 27.5 28.0 Unit ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” Table 9. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter tpd tdis ten Conditions 0.8 V propagation delay A to B B to A disable time enable time DIR to A DIR to B DIR to A DIR to B [1] VCC(A) 1.2 V 12.7 8.4 4.9 9.2 17.6 17.6 1.5 V 12.4 8.0 3.8 9.0 17.0 16.2 1.8 V 12.2 8.0 3.7 8.8 16.8 15.9 2.5 V 12.0 8.7 2.8 8.7 17.4 14.8 3.3 V 11.8 9.5 3.4 8.6 18.1 15.2 15.8 15.8 12.2 11.7 27.5 28.0 Unit ns ns ns ns ns ns tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD power dissipation capacitance Conditions 0.8 V A port: (direction A to B); B port: (direction B to A) A port: (direction B to A); B port: (direction A to B) [1] VCC(A) and VCC(B) 1.2 V 2 11 1.5 V 2 11 1.8 V 2 12 2.5 V 2 14 3.3 V 2 17 1 9 Unit pF pF CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. [2] 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 10 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state Table 11. Dynamic characteristics for temperature range −40 °C to +85 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6. Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Min VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B [1] Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V Min 0.7 0.8 2.2 1.8 0.7 0.8 1.6 1.8 0.6 0.7 1.6 1.8 0.5 0.6 1.5 2.0 0.5 0.6 1.5 0.7 Max 6.8 8.0 8.8 6.7 14.7 15.6 5.4 5.4 6.3 5.9 11.3 11.7 5.1 4.6 5.5 5.7 10.3 10.6 4.7 3.8 4.2 5.2 9.0 8.9 4.5 3.6 4.7 5.5 9.1 9.2 Min 0.6 0.7 2.2 2.0 0.6 0.7 1.6 1.6 0.5 0.5 1.6 1.4 0.5 0.5 1.5 1.5 0.5 0.5 1.5 0.6 Max 6.1 7.7 8.8 6.9 14.6 14.9 4.6 5.1 6.3 6.0 11.1 10.9 4.3 4.4 5.5 5.8 10.2 9.8 3.9 3.4 4.2 5.1 8.5 8.1 3.7 3.1 4.7 5.5 8.6 8.4 Min 0.5 0.6 2.2 1.7 0.5 0.6 1.6 1.2 0.5 0.5 1.6 1.0 0.5 0.5 1.5 0.6 0.5 0.5 1.5 0.7 Max 5.7 7.2 8.8 6.2 13.4 14.5 3.7 4.7 6.3 4.8 9.5 10.0 3.4 3.9 5.5 4.5 8.4 8.9 3.0 3.0 4.2 4.2 7.2 7.2 2.8 2.6 4.7 4.1 6.7 7.5 3.3 V ± 0.3 V Min 0.5 0.5 2.2 2.4 0.5 0.5 1.6 1.7 0.5 0.5 1.6 1.5 0.5 0.5 1.5 1.1 0.5 0.5 1.5 1.7 Max 6.1 7.1 8.8 7.2 14.3 14.9 3.5 4.5 6.3 5.5 10.0 9.8 3.1 3.7 5.5 5.2 8.9 8.6 2.6 2.8 4.2 4.8 7.6 6.8 2.4 2.4 4.7 4.7 7.1 7.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 9.0 9.0 8.8 8.4 17.4 17.8 8.0 6.8 6.3 7.6 14.4 14.3 7.7 6.1 5.5 7.8 13.9 13.2 7.2 5.7 4.2 7.3 13.0 11.4 7.1 6.1 4.7 7.2 13.3 11.8 1.0 1.0 2.2 2.2 1.0 1.0 1.6 2.0 1.0 1.0 1.6 1.8 1.0 1.0 1.5 1.7 1.0 1.0 1.5 1.7 - tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 11 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +125 °C [1] Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6 Symbol Parameter Conditions VCC(B) 1.2 V ± 0.1 V Min VCC(A) = 1.1 V to 1.3 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 1.4 V to 1.6 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 1.65 V to 1.95 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 2.3 V to 2.7 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B VCC(A) = 3.0 V to 3.6 V tpd tdis ten propagation delay disable time enable time A to B B to A DIR to A DIR to B DIR to A DIR to B [1] Unit 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V Min 0.7 0.8 2.2 1.8 0.7 0.8 1.6 1.8 0.6 0.7 1.6 1.8 0.5 0.6 1.5 2.0 0.5 0.6 1.5 0.7 Max 7.5 8.8 9.7 7.4 16.2 17.2 6.0 6.0 7.0 6.5 12.5 13.0 5.7 5.1 6.1 6.3 11.4 11.8 5.2 4.2 4.7 5.8 10.0 9.9 5.0 4.0 5.2 6.0 10.1 10.2 Min 0.6 0.7 2.2 2.0 0.6 0.7 1.6 1.6 0.5 0.5 1.6 1.4 0.5 0.5 1.5 1.5 0.5 0.5 1.5 0.6 Max 6.8 8.5 9.7 7.6 16.1 16.5 5.1 5.7 7.0 6.6 12.3 12.7 4.8 4.9 6.1 6.4 11.3 10.9 4.3 3.8 4.7 5.7 9.5 9.0 4.1 3.5 5.2 6.1 9.6 9.3 Min 0.5 0.6 2.2 1.7 0.5 0.6 1.6 1.2 0.5 0.5 1.6 1.0 0.5 0.5 1.5 0.6 0.5 0.5 1.5 0.7 Max 6.3 8.0 9.7 6.9 14.9 16.0 4.1 5.2 7.0 5.3 10.5 11.1 3.8 4.3 6.1 5.0 9.3 9.9 3.3 3.3 4.7 4.7 8.0 8.0 3.1 2.9 5.2 4.6 7.5 8.3 3.3 V ± 0.3 V Min 0.5 0.5 2.2 2.4 0.5 0.5 1.6 1.7 0.5 0.5 1.6 1.5 0.5 0.5 1.5 1.1 0.5 0.5 1.5 1.7 Max 6.8 7.9 9.7 8.0 15.9 16.5 3.9 5.0 7.0 6.1 11.1 10.9 3.5 4.1 6.1 5.8 9.9 9.6 2.9 3.1 4.7 5.3 8.4 7.6 2.7 2.7 5.2 5.2 7.9 7.9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 9.9 9.9 9.7 9.2 19.1 19.6 8.8 7.5 7.0 8.3 15.8 15.8 8.5 6.8 6.1 8.6 15.4 14.6 8.0 6.3 4.7 8.0 14.3 12.7 7.9 6.8 5.2 7.9 14.7 13.1 1.0 1.0 2.2 2.2 1.0 1.0 1.6 2.0 1.0 1.0 1.6 1.8 1.0 1.0 1.5 1.7 1.0 1.0 1.5 1.7 - tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH. ten is a calculated value using the formula shown in Section 13.4 “Enable times” 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 12 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 12. Waveforms VI A, B input GND tPHL VOH B, A output VOL VM 001aae967 VM tPLH Measurement points are given in Table 13. VOL and VOH are typical output voltage drops that occur with the output load. Fig 5. The data input (A, B) to output (B, A) propagation delay times VI DIR input GND t PLZ output LOW-to-OFF OFF-to-LOW VCCO VM VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aae968 VM t PZL VX t PZH VY VM Measurement points are given in Table 13. VOL and VOH are typical output voltage drops that occur with the output load. Fig 6. Table 13. Enable and disable times Measurement points Input[1] VM 0.5VCCI 0.5VCCI 0.5VCCI Output[2] VM 0.5VCCO 0.5VCCO 0.5VCCO VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.15 V VOH − 0.3 V Supply voltage VCC(A), VCC(B) 1.1 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 13 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 14. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 7. Table 14. Load circuitry for switching times Test data Input VI[1] VCCI VCCI VCCI ∆t/∆V ≤ 1.0 ns/V ≤ 1.0 ns/V ≤ 1.0 ns/V Load CL 15 pF 15 pF 15 pF RL 2 kΩ 2 kΩ 2 kΩ VEXT tPLH, tPHL open open open tPZH, tPHZ GND GND GND tPZL, tPLZ[2] 2VCCO 2VCCO 2VCCO Supply voltage VCC(A), VCC(B) 1.1 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 3.6 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 14 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in Figure 8 is an example of the 74AVCH1T45 being used in an unidirectional logic level-shifting application. 74AVCH1T45 VCC1 VCC(A) 1 2 6 5 VCC(B) VCC2 GND VCC1 A DIR VCC2 B 3 4 system-1 system-2 001aag889 Fig 8. Table 15. Pin 1 2 3 4 5 6 Unidirectional logic level-shifting application Description unidirectional logic level-shifting application Function VCC1 GND OUT DIR IN VCC2 Description supply voltage of system-1 (0.8 V to 3.6 V) device GND output level depends on VCC1 voltage the GND (LOW level) determines B port to A port direction input threshold value depends on VCC2 voltage supply voltage of system-2 (0.8 V to 3.6 V) Name VCC(A) GND A DIR B VCC(B) 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 15 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 13.2 Bidirectional logic level-shifting application Figure 9 shows the 74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. 74AVCH1T45 VCC1 VCC1 VCC(A) 1 2 6 5 VCC(B) VCC2 VCC2 I/O-1 GND DIR I/O-2 A 3 4 B DIR CTRL system-1 system-2 001aag890 Fig 9. Bidirectional logic level-shifting application Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 16. 1 2 H H Description bidirectional logic level-shifting application[1] I/O-2 input Z Description system-1 data to system-2 system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold. DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold. system-2 data to system-1 output Z State DIR CTRL I/O-1 3 4 [1] L L Z input Z output H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 16 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 13.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 17. VCC(A) 0V 0.8 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V Typical total supply current (ICC(A) + ICC(B)) VCC(B) 0V 0 0.1 0.1 0.1 0.1 0.1 0.1 0.8 V 0.1 0.1 0.1 0.1 0.1 0.7 2.3 1.2 V 0.1 0.1 0.1 0.1 0.1 0.3 1.4 1.5 V 0.1 0.1 0.1 0.1 0.1 0.1 0.9 1.8 V 0.1 0.1 0.1 0.1 0.1 0.1 0.5 2.5 V 0.1 0.7 0.3 0.1 0.1 0.1 0.1 3.3 V 0.1 2.3 1.4 0.9 0.5 0.1 0.1 µA µA µA µA µA µA µA Unit 13.4 Enable times The enable times for the 74AVCH1T45 are calculate from the following formulas: • ten (DIR to A) = tdis (DIR to B) + tpd (B to A) • ten (DIR to B) = tdis (DIR to A) + tpd (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AVCH1T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 17 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 14. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 10. Package outline SOT363 (SC-88) 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 18 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 11. Package outline SOT886 (XSON6) 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 19 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 15. Abbreviations Table 18. Acronym CDM CMOS DUT ESD HBM MM Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 16. Revision history Table 19. Revision history Release date 20090505 Data sheet status Product data sheet Product data sheet Change notice Supersedes 74AVCH1T45_1 Document ID 74AVCH1T45_2 Modifications: 74AVCH1T45_1 • Conditions for ICC changed 20071025 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 20 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74AVCH1T45_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 5 May 2009 21 of 22 NXP Semiconductors 74AVCH1T45 Dual supply translating transceiver; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Unidirectional logic level-shifting application. . 15 Bidirectional logic level-shifting application. . . 16 Power-up considerations . . . . . . . . . . . . . . . . 17 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2009 Document identifier: 74AVCH1T45_2