74HC165D

74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 03 — 14 March 2008 Product data sheet 1. General description The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When PL is HIGH, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH for predictable operation. Either the CP or the CE should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated. 2. Features I I I I Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Applications I Parallel-to-serial data conversion NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 4. Ordering information Table 1. Ordering information Temperature range Name 74HC165N 74HCT165N 74HC165D 74HCT165D 74HC165DB 74HCT165DB 74HC165PW 74HCT165PW 74HC165BQ 74HCT165BQ −40 °C to +125 °C −40 °C to +125 °C TSSOP16 −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT338-1 SOT403-1 SOT763-1 −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 −40 °C to +125 °C DIP16 Description plastic dual in-line package; 16 leads (300 mil) Version SOT38-4 Type number Package DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 5. Functional diagram SRG8 C2[LOAD] G1[SHIFT] 15 10 11 12 13 14 3 4 5 6 1 DS D0 D1 D2 D3 D4 D5 D6 D7 PL CP CE 2 15 mna985 mna986 1 ≥1 2 10 11 12 13 14 Q7 Q7 9 7 3 4 5 1 C3/ 3D 2D 2D 9 6 7 Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 2 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 11 12 13 14 3 4 5 6 D0 D1 D2 D3 D4 D5 D6 D7 1 PL 10 DS 2 CP 15 CE 8-BIT SHIFT REGISTER PARALLEL-IN/SERIAL-OUT Q7 9 Q7 7 mna992 Fig 3. Functional diagram 6. Pinning information 6.1 Pinning 74HC165 74HCT165 PL CP D4 D5 D6 D7 Q7 GND 1 2 3 4 5 6 7 8 001aah564 74HC165 74HCT165 16 VCC 15 CE CP 14 D3 13 D2 12 D1 11 D0 10 DS 9 Q7 D4 D5 D6 D7 Q7 2 3 4 5 6 7 8 GND Q7 9 GND(1) terminal 1 index area 16 VCC 15 CE 14 D3 13 D2 12 D1 11 D0 10 DS PL 1 001aah565 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 4. Pin configuration (DIP16, SO16 and (T)SSOP16) Fig 5. Pin configuration (DHVQFN16) 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 3 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 6.2 Pin description Table 2. Symbol PL CP Q7 GND Q7 DS D0 to D7 CE VCC Pin description Pin 1 2 7 8 9 10 11, 12, 13, 14, 3, 4, 5, 6 15 16 Description asynchronous parallel load input (active LOW) clock input (LOW-to-HIGH edge-triggered) complementary output from the last stage ground (0 V) serial output from the last stage serial data input parallel data inputs (also referred to as Dn) clock enable input (active LOW) positive supply voltage 7. Functional description Table 3. Function table[1] Inputs PL parallel load serial shift L L H H H H hold “do nothing” H H [1] Operating modes Qn registers CE X X L L ↑ ↑ H X CP X X ↑ ↑ L L X H DS X X l h l h X X D0 to D7 Q0 L H X X X X X X L H L H L H q0 q0 L to L H to H q0 to q5 q0 to q5 q0 to q5 q0 to q5 q1 to q6 q1 to q6 Outputs Q7 H L q6 q6 q6 q6 q7 q7 L H q6 q6 q6 q6 q7 q7 Q1 to Q6 Q7 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 4 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register CP CE DS PL D0 D1 D2 D3 D4 D5 D6 D7 Q7 Q7 inhibit load serial shift mna993 Fig 6. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol VCC IIK IOK IO ICC IGND Tstg Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 V < VO < VCC + 0.5 V [1] [1] Conditions Min −0.5 −50 −65 Max +7 ±20 ±20 ±25 50 +150 Unit V mA mA mA mA mA °C 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 5 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Ptot Parameter total power dissipation Conditions Tamb = −40 °C to +125 °C DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package [1] [2] [3] [4] [5] [2] [3] [4] [5] Min - Max 750 500 500 500 Unit mW mW mW mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 °C. Ptot derates linearly with 8 mW/K above 70 °C. Ptot derates linearly with 5.5 mW/K above 60 °C. Ptot derates linearly with 4.5 mW/K above 60 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 −40 74HC165 Typ 5.0 1.67 Max 6.0 VCC VCC +125 625 139 83 Min 4.5 0 0 −40 74HCT165 Typ 5.0 1.67 Max 5.5 VCC VCC +125 139 V V V °C ns/V ns/V ns/V Unit 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC165 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 6 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH HIGH-level output voltage Conditions Min VI = VIH or VIL IO = −20 µA; VCC = 2.0 V IO = −20 µA; VCC = 4.5 V IO = −20 µA; VCC = 6.0 V IO = −4.0 mA; VCC = 4.5 V IO = −5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V IO = 20 µA; VCC = 4.5 V IO = 20 µA; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current supply current input capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 µA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC ∆ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V per input pin; VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V Dn and DS inputs CP CE, and PL inputs CI input capacitance 35 65 3.5 126 234 157.5 292.5 171.5 318.5 µA µA pF 0 0.16 0.1 0.26 ±0.1 8.0 0.1 0.33 ±1 80 0.1 0.4 ±1 160 V V µA µA 4.4 3.98 4.5 4.32 4.4 3.84 4.4 3.7 V V VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0 0 0 0.15 0.16 3.5 0.1 0.1 0.1 0.26 0.26 ±0.1 8.0 0.1 0.1 0.1 0.33 0.33 ±1 80 0.1 0.1 0.1 0.4 0.4 ±1 160 V V V V V µA µA pF 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max 74HCT165 VIH VIL VOH 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 7 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter 74HC165 tpd propagation delay CP or CE to Q7, Q7; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF PL to Q7, Q7; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF D7 to Q7, Q7; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF tt transition time Q7, Q7 output; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width CP input HIGH or LOW; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL input LOW; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trec recovery time PL to CP, CE; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 100 20 17 22 8 6 125 25 21 150 30 26 ns ns ns 80 16 14 14 5 4 100 20 17 120 24 20 ns ns ns 80 16 14 17 6 5 100 20 17 120 24 20 ns ns ns [2] [1] Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 52 19 15 16 50 18 14 15 36 13 10 11 19 7 6 165 33 28 165 33 28 120 24 20 75 15 13 - 205 41 35 205 41 35 150 30 26 95 19 16 - 250 50 43 250 50 43 180 36 31 110 22 19 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 8 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter tsu set-up time Conditions Min DS to CP, CE; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CE to CP and CP to CE; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Dn to PL; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time DS to CP, CE and Dn to PL; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CE to CP and CP to CE; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum frequency CP input; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance per package; VI = GND to VCC [3] 25 °C Typ Max 11 4 3 - −40 °C to +85 °C −40 °C to +125 °C Unit Min 100 20 17 Max Min 120 24 20 Max ns ns ns 80 16 14 80 16 14 80 16 14 17 6 5 22 8 6 - 100 20 17 100 20 17 - 120 24 20 120 24 20 - ns ns ns ns ns ns 5 5 5 6 2 2 - 5 5 5 - 5 5 5 - ns ns ns 5 5 5 6 30 35 - −17 −6 −5 17 51 61 56 35 - 5 5 5 5 24 28 - - 5 5 5 4 20 24 - - ns ns ns MHz MHz MHz MHz pF 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 9 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter 74HCT165 tpd propagation delay CE, CP to Q7, Q7; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF PL to Q7, Q7; see Figure 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF D7 to Q7, Q7; see Figure 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt tW transition time pulse width Q7, Q7 output; see Figure 7 VCC = 4.5 V CP input; see Figure 7 VCC = 4.5 V PL input; see Figure 8 VCC = 4.5 V trec tsu recovery time PL to CP, CE; see Figure 8 VCC = 4.5 V set-up time DS to CP, CE; see Figure 10 VCC = 4.5 V CE to CP and CP to CE; see Figure 10 VCC = 4.5 V Dn to PL; see Figure 11 VCC = 4.5 V th hold time DS to CP, CE and Dn to PL; see Figure 10 VCC = 4.5 V CE to CP and CP to CE; see Figure 10 VCC = 4.5 V fmax maximum frequency CP input; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 26 44 48 21 17 MHz MHz 0 −7 0 0 ns 7 −1 9 11 ns 20 10 25 30 ns 20 7 25 30 ns 20 2 25 30 ns 20 8 25 30 ns 20 9 25 30 ns 16 6 20 24 ns [2] [1] Conditions Min 25 °C Typ Max −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max - 17 14 20 17 14 11 7 34 40 28 15 - 43 50 35 19 - 51 60 42 22 ns ns ns ns ns ns ns 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 10 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12 Symbol Parameter CPD power dissipation capacitance Conditions Min per package; VI = GND to VCC − 1.5 V [3] 25 °C Typ Max 35 - −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max pF [1] [2] [3] tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; Σ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 12. Waveforms 1/fmax VI CP or CE input GND tW tPHL VOH Q7 or Q7 output VOL tTHL tTLH mna987 VM tPLH VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the maximum clock frequency and the output transition times 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 11 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register VI PL input GND tW VI CE, CP input GND tPHL VOH Q7 or Q7 output VOL VM mna988 VM trec VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel load to clock (CP) and clock enable (CE) recovery time VI D7 input GND tPLH VOH Q7 output VOL tPHL VOH Q7 output VOL VM mna989 VM tPHL VM tPLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 12 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register VI CP, CE input GND (1) VM th tsu VI DS input GND tsu VI CP, CE input GND VM tW VM tsu th mna990 The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. (1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1. Fig 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE) VI Dn input GND tsu VI PL input GND VM VM mna991 VM VM th tsu th Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL) Table 8. Type 74HC165 74HCT165 Measurement points Input VI VCC 3V VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 13 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC VCC G VI VO RL S1 DUT RT CL open 001aad983 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 12. Test circuit for measuring switching times Table 9. Type 74HC165 74HCT165 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 kΩ 1 kΩ S1 position tPHL, tPLH open open 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 14 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 13. Package outline SOT38-4 (DIP16) 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 15 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 16 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT338-1 (SSOP16) 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 17 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT403-1 (TSSOP16) 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 18 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 17. Package outline SOT763-1 (DHVQFN16) 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 19 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 14. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20080314 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT165_CNV_2 Document ID 74HC_HCT165_3 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Package SOT763-1 (DHVQFN16) added to Section 4 “Ordering information” and Section 13 “Package outline”. Family data added, see Section 10 “Static characteristics” Product specification - 74HC_HCT165_CNV_2 December 1990 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 20 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT165_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 14 March 2008 21 of 22 NXP Semiconductors 74HC165; 74HCT165 8-bit parallel-in/serial out shift register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 March 2008 Document identifier: 74HC_HCT165_3