74HC5555N,112

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT5555 Programmable delay timer with oscillator Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 FEATURES GENERAL DESCRIPTION • Positive and negative edge triggered The 74HC/HCT5555 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • Retriggerable or non-retriggerable • Programmable delay minimum: 100 ns maximum: depends on input frequency and division ratio • Divide-by range of 2 to 224 • Direct reset terminates output pulse • Very low power consumption in triggered start mode • retriggerable/non-retriggerable monostable • automatic power-ON reset • output control logic • oscillator control logic • overriding asynchronous master reset (MR). The 74HC/HCT5555 are precision programmable delay timers which consist of: • 24-stage binary counter • integrated oscillator (using external timing components) • 3 oscillator operating modes: – RC oscillator – Crystal oscillator – External oscillator • Device is unaffected by variations in temperature and VCC when using an external oscillator QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. SYMBOL tPHL/tPLH • Direct drive for a power transistor • Low power consumption in active mode with respect to TTL type timers CONDITIONS propagation delay CL = 15 pF; VCC = 5 V A, B to Q/Q • Automatic power-ON reset • Schmitt trigger action on both trigger inputs PARAMETER TYP. 24 UNIT 24 ns MR to Q/Q 19 20 ns RS to Q/Q 26 28 ns 3.5 3.5 pF 23 36 pF CI input capacitance CPD power dissipation capacitance per buffer notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): • High precision due to digital timing PD = CPD x VCC2 x fi + Σ(CL x VCC2 x fo) where: • Output capability: 20 mA fi = input frequency in MHz • ICC category: MSI. fo = output frequency in MHz Σ(CL x VCC2 x fo) = sum of outputs. APPLICATIONS CL = output load capacitance in pF • Motor control VCC = supply voltage in V • Attic fan timers • Delay circuits • Automotive applications • Precision timing • Domestic appliances. September 1993 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE 74HC/HCT5555N 16 DIL plastic SOT38Z 74HC/HCT5555D 16 SO16 plastic SOT109A 2 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 PINNING SYMBOL PIN DESCRIPTION RS 1 clock input/oscillator pin RTC 2 external resistor connection CTC 3 external capacitor connection A 4 trigger input (positive-edge triggered) B 5 trigger input (negative-edge triggered) RTR/RTR 6 retriggerable/non-retriggerable input (active HIGH/active LOW) Q 7 pulse output (active LOW) GND 8 ground (0 V) Q 9 pulse output (active HIGH) S 0 − S3 10, 11, 12, 13 programmable input OSC CON 14 oscillator control MR 15 master reset input (active HIGH) VCC 16 positive supply voltage handbook, halfpage X/Y 10 0 1 2 11 12 13 4 8 2 15 RX CX 3 14 handbook, halfpage CTRDIVm [T] Y=0 Y = 15 + & 4 1 5 CT = 0 CT = m R S I=0 15 V16 9 7 R R MGA643 Fig.2 IEC logic diagram. September 1993 16 R TC 2 15 MR C TC 3 OSC 14 CON A 4 13 S 3 5555 B 5 RTR/ RTR 6 11 S1 Q 7 10 S 0 GND 8 9 12 S2 Q Fig.1 Pin configuration. !G 6 1 MGA642 16G17 17 1 VCC RS 3 Philips Semiconductors Product specification Programmable delay timer with oscillator handbook, full pagewidth 1 RS 74HC/HCT5555 2 3 10 11 12 13 R TC C TC S0 S1 S2 S3 CP 24 - STAGE COUNTER CD OSC 14 CON POWER-ON RESET 15 MR 4 A 5 B MONOSTABLE CIRCUITRY Q 9 OUTPUT STAGE Q 7 6 RTR/RTR MGA644 Fig.3 Functional diagram. FUNCTIONAL DESCRIPTION The oscillator configuration allows the design of RC or crystal oscillator circuits. The device can operate from an external clock signal applied to the RS input (RTC and CTC must not be connected). The oscillator frequency is determined by the external timing components (RT and CT), within the frequency range 1 Hz to 4 MHz (32 kHz to 20 MHz with crystal oscillator). In the HCT version the MR input is TTL compatible but the RS input has CMOS input switching levels. The RS input can be driven by TTL input levels if RS is tied to VCC via a pull-up resistor. The counter divides the frequency to obtain a long pulse duration. The 24-stage is digitally programmed via the select inputs (S0 to S3). Pin S3 can also be used to select the test mode, which is a convenient way of functionally testing the counter. The “5555” is triggered on either the positive-edge, negative-edge or both. • Trigger pulse applied to input A for positive-edge triggering September 1993 • Trigger pulse applied input B for negative-edge triggering • Trigger pulse applied to inputs A and B (tied together) for both positive-edge and negative triggering. The Schmitt trigger action in the trigger inputs, transforms slowly changing input signals into sharply defined jitter-free output signals and provides the circuit with excellent noise immunity. The OSC CON input is used to select the oscillator mode, either continuously running (OSC CON = HIGH) or triggered start mode (OSC CON = LOW). The continuously running mode is selected where a start-up delay is an undesirable feature and the triggered start mode is selected where very low power consumption is the primary concern. The start of the programmed time delay occurs when output Q goes HIGH (in the triggered start mode, the previously disabled oscillator will start-up). After the programmed time delay, the flip-flop stages are reset and the output returns to its original state. 4 An internal power-on reset is used to reset all flip-flop stages. The output pulse can be terminated by the asynchronous overriding master reset (MR), this results in all flip-flop stages being reset. The output signal is capable of driving a power transistor. The output time delay is calculated using the following formula (minimum time delay is 100 ns): 1 --- × division ratio (s). fi Once triggered, the output width may be extended by retriggering the gated, active HIGH-going input A or the active LOW-going input B. By repeating this process, the output pulse period (Q = HIGH, Q = LOW) can be made as long as desired. This mode is selected by RTR/RTR = HIGH. A LOW on RTR/RTR makes, once triggered, the outputs (Q, Q) independent of further transitions of inputs A and B. September 1993 S0 S1 S2 S3 OSC CON RS R TC C TC 5 B A ndbook, full pagewidth CP CD Fig.4 Logic diagram. Q CD CP Q CD CP Q CP Q CD CD CP Q CD CP Q CP Q CD CD CP Q CD CP Q CP Q CD CD CP Q CD CP Q CP Q CD Q Q CD CP Q CD CP Q CP Q CD CD CP Q CD CP Q CP Q CD MGA655 CD CP Q CD CP Q CP Q CD Programmable delay timer with oscillator RTR/RTR MR VCC CD CP Q CD CP Q CP Q CD Philips Semiconductors Product specification 74HC/HCT5555 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 TEST MODE Set S3 to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S0, S1 and S2 to a logic HIGH level, this programs the counter to divide-by 28 (256). Apply a trigger pulse and clock in 255 pulses, this sets all flip-flop stages to a logic HIGH level. Set S3 to a logic HIGH level, this causes the counter to divide-by 224. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 224 (16 777 216) clock pulses. FUNCTION TABLE INPUTS OUTPUTS B Q Q MR A H X X L H L ↑ X one HIGH level output pulse one LOW level output pulse L X ↓ one HIGH level output pulse one LOW level output pulse Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care ↑ = LOW-to-HIGH transition ↓ = HIGH-to-LOW transition. September 1993 6 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 DELAY TIME SELECTION SELECT INPUTS S3 S2 L OUTPUT Q/Q (FREQUENCY DIVIDING) S1 L S0 L BINARY DECIMAL L 21 2 4 L L L H 22 L L H L 23 8 H 24 16 32 L L H L H L L 25 L H L H 26 64 L 27 128 256 L H H L H H H 28 . . . . . . L 217 131 072 H 218 262 144 524 288 H L H L L L H L H L 219 H L H H 220 1 048 576 L 221 2 097 152 4 194 304 H H L H H L H 222 H H H L 223 8 388 608 H 224 16 777 216 H H H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 handbook, full pagewidth RS MR A Q MGA649 Timing example shown for S3, S2, S1, S0 = 0011 (binary 24, decimal 16). Fig.5 Timing diagram. September 1993 7 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI. DC CHARACTERISTICS FOR 74HC Tamb (°C) SYMBOL TEST CONDITION +25 −40 to +85 −40 to +125 MIN TYP MAX MIN MAX MIN PARAMETER − − − UNIT MAX VCC (V) VI OTHER − − − 1.9 4.4 5.9 − − − V V V 2.0 4.5 6.0 Io = −20 µA 3.84 − 5.34 − 3.7 5.2 − − V V 4.5 6.0 Io = −6.0 mA Io = −7.8 mA 3 4.5 − − 2.7 4.2 − − V V 4.5 6.0 Io = −20 mA Io = −20 mA − − − 0.1 0.1 0.1 − − − 0.1 0.1 0.1 V V V 2.0 4.5 6.0 Io = 20 µA 0.15 0.26 0.15 0.26 − − 0.33 0.33 − − 0.40 0.40 V V 4.5 6.0 Io = 6.0 mA Io = 7.8 mA − − − − 0.9 0.9 − − 1.14 1.14 − − 1.34 1.34 V V 4.5 6.0 Io = 20 mA Io = 25 mA HIGH level input voltage RS input 1.7 3.6 4.8 − − − − − − 1.7 3.6 4.8 − − − 1.7 3.6 4.8 − − − V V V 2 4.5 6.0 LOW level input voltage RS input − − − − − − 0.3 0.9 1.2 − − − 0.3 0.9 1.2 − − − 0.3 0.9 1.2 V V V 2.0 4.5 6.0 VOH HIGH level output voltage Q and Q outputs 1.9 4.4 5.9 VOH HIGH level output voltage Q and Q outputs 3.98 4.32 − 5.48 5.81 − VOH HIGH level output voltage Q and Q outputs 3.3 4.8 − − − − VOL LOW level output voltage Q and Q outputs − − − 0 0 0 0.1 0.1 0.1 VOL LOW level output voltage Q and Q outputs − − VOL LOW level output voltage Q and Q outputs VIH VIL September 1993 2 4.5 6.0 1.9 4.4 5.9 8 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 Tamb (°C) SYMBOL VOH +25 −40 to +85 −40 to +125 MIN TYP MAX MIN MAX MIN 3.98 − 5.48 − − − 3.84 − 5.34 − 3.7 5.2 − − V V 4.5 6.0 RS = GND; OSC CON = VCC Io = −2.6 mA Io = −3.3 mA 3.98 − 5.48 − − − 3.84 − 5.34 − 3.7 5.2 − − V V 4.5 6.0 RS = VCC; OSC CON = GND; untriggered Io = −0.65 mA Io = −0.85 mA 1.9 4.4 5.9 2.0 4.5 6 − − − 1.9 4.4 5.9 − − − 1.9 4.4 5.9 − − − V V V 2.0 4.5 6.0 RS = VCC; OSC CON = VCC Io = −20 µA 1.9 4.4 5.9 2.0 4.5 6.0 − − − 1.9 4.4 5.9 − − − 1.9 4.4 5.9 − − − V V V 2 4.5 6.0 RS = VCC; OSC CON = GND; untriggered Io = −20 µA PARAMETER HIGH level output voltage RTC output TEST CONDITION UNIT MAX VCC (V) VI OTHER VOH HIGH level output voltage CTC output 3.98 − 5.48 − − − 3.84 − 5.34 − 3.7 5.2 − − V V 4.5 6.0 RS = VIH; OSC CON = VIH Io = −3.2 mA Io = −4.2 mA VOL LOW level output voltage RTC output − − − − 0.26 0.26 − − 0.33 0.33 − − 0.4 0.4 V V 4.5 6 RS = VCC; OSC CON = VCC Io = 2.6 mA Io = 3.3 mA − − − 0 0 0 0.1 0.1 0.1 − − − 0.1 0.1 0.1 − − − 0.1 0.1 0.1 V V V 2.0 4.5 6 RS = VCC; OSC CON = VCC Io = 20 µA − − − − 0.26 0.26 − − 0.33 0.33 − − 0.4 0.4 V V 4.5 6.0 RS = VIL; OSC CON = VIL; untriggered Io = 3.2 mA Io = 4.2 mA VOL LOW level output voltage CTC output September 1993 9 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) SYMBOL +25 PARAMETER MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS tPLH/tPHL propagation delay A, B to Q, Q − − − 77 28 22 240 48 41 − − − 300 60 51 − − − 360 72 61 ns ns ns 2.0 4.5 6.0 Fig.6 tPLH/tPHL propagation delay MR to Q, Q − − − 61 22 18 185 37 31 − − − 230 46 39 − − − 280 56 48 ns ns ns 2.0 4.5 6.0 Fig.7 tPLH/tPHL propagation delay RS to Q, Q − − − 83 30 24 250 50 43 − − − 315 63 54 − − − 375 75 64 ns ns ns 2.0 4.5 6.0 Fig.8; note 1 tTHL/tTLH output transition time − − − 19 7 6 75 15 13 − − − 95 19 16 − − − 110 22 19 ns ns ns 2.0 4.5 6.0 Fig.6 tW trigger pulse width A = HIGH 70 14 12 17 6 5 − − − 90 18 15 − − − 105 21 18 − − − ns ns ns 2.0 4.5 6.0 Fig.6 B = LOW tW master reset pulse width HIGH 70 14 12 19 7 6 − − − 90 18 15 − 105 21 18 − − − ns ns ns 2.0 4.5 6.0 Fig.7 tW clock pulse width RS; HIGH or LOW 80 16 14 25 9 7 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.8 tW minimum output pulse width Q = HIGH, Q = LOW − − − 275 100 80 − − − − − − − − − − − − − − − ns ns ns 2.0 4.5 6.0 Fig.6; note 1 trt retrigger time A, B − − − 0 0 0 − − − − − − − − − − − − − − − ns ns ns 2.0 4.5 6.0 Fig.10; note 2 REXT external timing resistor 5 1 − − 1000 1000 − − − − − − − − − − kΩ kΩ 2.0 5.0 Fig.13 CEXT external timing capacitor 50 50 pF pF 2.0 5.0 Fig.13 trem removal time MR to A, B 120 24 20 ns ns ns 2.0 4.5 6.0 Fig.7 September 1993 no limits 39 14 11 − − − − − − 150 30 26 10 180 36 31 − − − Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 Tamb (°C) SYMBOL +25 PARAMETER MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS fmax maximum clock pulse frequency 2 10 12 5.9 18 21 − − − 1.8 8 10 − − − 1.3 6.6 8 − − − MHz MHz MHz 2.0 4.5 6.0 Fig.8; note 3 fmax maximum clock pulse frequency 6 30 35 24.8 75 89 − − − 4.8 24 28 − − − 4 20 24 − − − MHz MHz MHz 2.0 4.5 6.0 Fig.9; note 4 Notes 1. One stage selected. 2. It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period exceeds the clock input cycle time divided by 2. 3. One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the RS clock input. 4. One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of the RS clock input. September 1993 11 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: non-standard; bus driver with extended specification on VOH and VOL ICC category: MSI. Tamb (°C) +25 SYMBOL PARAMETER TEST CONDITION −40 to +85 MIN UNIT V CC (V) MAX − 4.4 − V 4.5 Io = −20 µA 3.84 − 3.7 − V 4.5 Io = −6 mA MIN TYP MAX MIN MAX − OTHER HIGH level output voltage Q and Q outputs 4.4 VOH HIGH level output voltage Q and Q outputs 3.98 4.32 − VOH HIGH level output voltage Q and Q outputs 3.3 − − 3 − 2.7 − V 4.5 Io = −20 mA VOL LOW level output voltage Q and Q outputs − 0 0.1 − 0.1 − 0.1 V 4.5 Io = 20 µA VOL LOW level output voltage Q and Q outputs − 0.15 0.26 − 0.33 − 0.40 V 4.5 Io = 6 mA VOL LOW level output voltage Q and Q outputs − − − 1.14 − 1.34 V 4.5 0.9 4.4 VI VOH September 1993 4.5 −0 to +125 12 − Io = 20 mA Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 Tamb (°C) +25 SYMBOL PARAMETER VOH HIGH level output voltage RTC output VOH HIGH level output voltage CTC output VOL LOW level output voltage RTC output VOL LOW level output voltage CTC output TEST CONDITION −40 to +85 −0 to +125 MIN TYP MAX MIN MAX MIN UNIT V CC (V) MAX 3.98 − − 3.84 − 3.7 − V 3.98 − − 3.84 − 3.7 − 4.4 4.5 − 4.4 − 4.4 4.4 4.5 − 4.4 − 3.98 − − − − − 0 − − VI OTHER 4.5 RS = GND; OSC CON = VCC Io = −2.6 mA V 4.5 RS = VCC; OSC CON = GND; untriggered Io = −0.65 mA − V 4.5 RS = VCC; OSC CON = VCC Io = −20 µA 4.4 − V 4.5 RS = VCC; OSC CON = GND; untriggered Io = −20 µA 3.84 − 3.7 − V 4.5 RS = VIH; OSC CON = VIH Io = −3.2 mA 0.26 − 0.33 − 0.4 V 4.5 RS = VCC; OSC CON = VCC Io = 2.6 mA 0.1 − 0.1 − 0.1 V 4.5 RS = VCC; OSC CON = VCC Io = 20 µA 4.5 RS = VIL; OSC CON = VIL; untriggered Io = 3.2 mA 0.26 − 0.33 − 0.4 V Notes 1. The RS input has CMOS input switching levels. 2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the following table. UNIT LOAD COEFFICIENT September 1993 INPUT UNIT LOAD COEFFICIENT MR 0.35 A 0.69 B 0.50 RTR/RTR 0.35 OSC CON 1.20 S0 - S2 0.65 S3 0.40 13 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) SYMBOL +25 PARAMETER MIN TYP MAX TEST CONDITION −40 to +85 −40 to +125 MIN MIN MAX UNIT MAX VCC (V) WAVEFORMS tPLH/tPHL propagation delay A, B to Q, Q − 28 48 − 60 − 72 ns 4.5 Fig.6 tPHL/tPLH propagation delay MR to Q, Q − 24 41 − 51 − 62 ns 4.5 Fig.7 tPHL/tPLH propagation delay RS to Q, Q − 32 54 − 68 − 81 ns 4.5 Fig.8; note 1 tTHL/tTLH output transition time − 7 15 − 19 − 22 ns 4.5 Fig.6 tW trigger pulse width A = HIGH B = LOW 21 12 − 26 − 32 − ns 4.5 Fig.6 tW master reset pulse width HIGH 14 5 − 18 − 21 − ns 4.5 Fig.7 tW clock pulse width RS; HIGH or LOW 16 9 − 20 − 24 − ns 4.5 Fig.8 tW minimum output pulse width Q = HIGH, Q = LOW − 100 − − − − − ns 4.5 Fig.6 trt retrigger time A, B − 0 − − − − − ns 4.5 Fig.10; note 2 REXT external timing resistor 1 − 1000 − − − − kΩ 4.5 Fig.13 CEXT external timing capacitor 50 pF 4.5 Fig.13 trem removal time MR to A, B 24 14 − 30 − 36 − ns 4.5 Fig.7 fmax maximum clock pulse frequency 10 18 − 8 − 6.6 − MHz 4.5 Fig.8; note 3 fmax maximum clock pulse frequency 30 75 − 24 − 20 − MHz 4.5 Fig.9; note 4 September 1993 no limits 14 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 Notes 1. One stage selected. 2. It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period exceeds the clock input cycle time divided by 2. 3. One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the RS clock input. 4. One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of the RS clock input. September 1993 15 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 AC WAVEFORMS tW handbook, full pagewidth 90% VM (1) B INPUT 10% 90% VM (1) A INPUT GND 10% tW t THL t TLH 90% VM (1) Q OUTPUT 10% t PHL t PLH tW 90% Q OUTPUT VM (1) 10% t TLH t THL MGA653 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the triggering of the delay timer by input A or B, the minimum pulse widths of the trigger inputs A and B, the output pulse width and output transition times. September 1993 16 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 handbook, full pagewidth MR INPUT VM (1) tW t rem A INPUT VM (1) t rem VM (1) B INPUT t PLH VM (1) Q OUTPUT t PHL Q OUTPUT VM (1) MGA652-1 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to outputs (Q and Q) propagation delays and the master reset to trigger inputs (A and B) removal time. September 1993 17 Philips Semiconductors Product specification Programmable delay timer with oscillator handbook, full pagewidth 74HC/HCT5555 1/f max RS INPUT 1 2 VCC tW t PHL VM (1) Q OUTPUT t PLH VM (1) Q OUTPUT MGA651 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and the maximum clock frequency. 1/f max handbook, full pagewidth RS INPUT VM (1) t PHL Q OUTPUT VM (1) t PLH Q OUTPUT VM (1) MGA654 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and the maximum clock frequency (Output waveforms are not synchronized with respect to the RS waveform). September 1993 18 Philips Semiconductors Product specification Programmable delay timer with oscillator handbook, full pagewidth 74HC/HCT5555 A INPUT tW B INPUT t rt tW Q OUTPUT tW tW tW MGA650 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Output pulse control using retrigger pulse (RTR/RTR = HIGH). September 1993 19 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 APPLICATION INFORMATION MBA333 14 handbook, g halfpage fs (mA/V) max. 12 R bias = 560 kΩ handbook, halfpage typ. 10 VCC 8 0.47 µ F min. output 100 µF input 6 vi A io (f = 1 kHz) 4 GND MGA645 2 0 1 2 3 4 5 VCC (V) 6 Fig.12 Typical forward transconductance gfs as a function of the supply voltage at VCC at Tamb = 25 °C. Fig.11 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see Fig.12) and MR = LOW. MGA647 5 10halfpage handbook, f osc (Hz) handbook, halfpage Rt 10 4 MR (from logic) Ct 1 RS 103 C2 102 R2 R TC C TC 2 3 Rt Ct MGA646 10 103 10 – 4 104 10 – 3 R t (Ω ) 106 105 10 – 2 C t ( µ F) 10 – 1 Typical formula for oscillator frequency: 1 f osc = -------------------------------2.5 × R t × C t Ct curve at Rt = 100 kΩ; R2 = 200 kΩ. Rt curve at Ct = 1 nF; R2 = 2 x Rt. RC oscillator frequency as a function of Rt and Ct at VCC = 2 to 6 V; Tamb = 25 °C. Fig.13 Application information. September 1993 Fig.14 Example of an RC oscillator. 20 Philips Semiconductors Product specification Programmable delay timer with oscillator 74HC/HCT5555 Timing Component Limitations Start-up Using External Clock Termination of the Timing Pulse The oscillator frequency is mainly determined by RtCt, provided R2 ≈ 2Rt and R2C2 50 pF, up to any practical value, 10 kΩ < Rt < 1 MΩ. In order to avoid start-up problems, Rt >> 1 kΩ. Typical Crystal Oscillator In Fig.15, R2 is the power limiting resistor. For starting and maintaining oscillation a minimum transconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 kΩ. Above 14 MHz it is recommended replacement of R2 by a capacitor with a typical value of 35 pF. Accuracy Device accuracy is very precise for long time delays and has an accuracy of better than 1% for short time delays (1% applies to values ≥ 400 ns). Tolerances are dependent on the external components used, either RC network or crystal oscillator. September 1993 • clock = HIGH; the timing pulse may be lengthened by a maximum of tW/2 (tW = clock pulse width) • clock = LOW; the timing pulse may be shortened by a maximum of tW/2 (tW = clock pulse width). This effect can be minimized by selecting more delay stages. When using only one or two delay stages, it is recommended to use an external time base that is synchronized with the negative-edge of the clock. Start-up Using RC Oscillator The first clock cycle is ≈35% of a time period too long. This effect can also be minimized by selecting more delay stages. Start-up Using Crystal Oscillator A crystal oscillator requires at least two clock cycles to start-up plus an unspecified period (ms) before the amplitude of the clock signal increases to its expected level. Although this device also operates at lower clock amplitudes, it is recommended to select the continuously running mode (OSC CON = HIGH) to prevent start-up delays. 21 • high clock frequency and large number of stages are selected. This depends on the dynamic relationship that exists between the clock frequency and the ripple through delay of the subsequent stages. Synchronization When frequencies higher than those specified in the Table 'Synchronization limits' are used, the termination of timing pulse will lose synchronization with the falling edge of the oscillator. The unsynchronized timing pulse introduces errors, which can be minimized by increasing the number of stages used e.g. a 20 MHz clock frequency using all 24 stages will result in a frequency division of 16 777 225 instead of 16 777 216, an error of 0.0005%. The amount of error increases at high clock frequencies as the number of stages decrease. A clock frequency of 40 MHz and 4 stages selected results in a division of 18 instead of 16, a 12.5% error. Application example: • If a 400 ns timing pulse was required it would be more accurate to utilize a 5 MHz clock frequency using 1 stage or a 10 MHz clock frequency using 2 stages (due to synchronization with falling edge of the oscillator) than a 40 MHz clock frequency and 4 stages (synchronization is lost). Philips Semiconductors Product specification Programmable delay timer with oscillator Minimum Output Pulse Width The minimum output pulse width is determined by the minimum clock pulse width, plus the maximum propagation delay of A, B to Q. The rising edge of Q is dominated by the A, B to Q propagation delay, while the falling edge of Q is dominated by RS to Q propagation delay. These propagation delays are not equal. The 74HC/HCT5555 RS to Q propagation delay is some what longer, resulting in inaccurate outputs for extremely short pulses. The propagation delays are listed in the section 'AC Characteristics'. With these numbers it is possible to calculate the maximum deviation (an example is shown in Fig.16). Figure 16 is valid for an external clock where the trigger is synchronized to the falling edge of the clock only. The graph shows that the minimum programmed pulse width of 100 ns is: • minimum of 4% too long • typically 7% too long • maximum of 10% too long. SYNCHRONIZATION LIMITS NUMBER OF STAGES SELECTED CLOCK FREQUENCY (TYPICAL) 1 18 MHz 2 14 MHz 3 11 MHz 4 9.6 MHz 5 8.3 MHz 6 7.3 MHz 7 6.6 MHz 8 6 MHz . . 17 3.2 MHz 18 3.0 MHz 19 2.9 MHz 20 2.8 MHz 21 2.7 MHz 22 2.6 MHz 23 2.5 MHz 24 2.4 MHz September 1993 22 Philips Semiconductors Product specification Programmable delay timer with oscillator handbook, halfpage 74HC/HCT5555 MR (from logic) 1 RS R TC 2 R bias 100 kΩ to 1 MΩ C3 22 to 37 pF C2 R2 2.2 kΩ 100 pF MLB336 Fig.15 External components configuration for a crystal oscillator. MGA648 40 deviation (%) handbook, full pagewidth 36 32 28 max. expected typ. expected min. expected 24 20 16 12 8 4 0 0 100 200 300 400 500 programmed time (ns) Fig.16 Graphic representation of short time delay accuracy; one stage selected; VCC = 4.5 V. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. September 1993 23 600