74HCT20D,653

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74HC20; 74HCT20 Dual 4-input NAND gate Rev. 4 — 18 November 2015 Product data sheet 1. General description The 74HC20; 74HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Complies with JEDEC standard JESD7A  Low-power dissipation  Input levels:  For 74HC20: CMOS level  For 74HCT20: TTL level  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +80 C and from 40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number 74HC20D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT20D 74HC20DB 74HCT20DB 74HC20PW 74HCT20PW 74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 4. Functional diagram $  %  < &     '   $   %  < &     '    DDD Fig 1. Functional diagram Fig 2. $ % < &  ' $ % < &  ' DDD Logic symbol    $   %  <  &    ' DDD Fig 3. DDD IEC Logic symbol Fig 4. Logic diagram 5. Pinning information 5.1 Pinning +& +&7 $   9&& %   ' QF   & &   QF '   % <   $ *1'   < +& +&7 $   9&& %   ' QF   & &   QF '   % <   $ *1'   < DDD Fig 5. Pin configuration SOT108-1 74HC_HCT20 Product data sheet DDD Fig 6. Pin configuration SOT337-1 and SOT402-1 All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 15 74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 1B, 1C, 1D 1, 2, 4, 5 data input n.c. 3, 11 not connected 1Y 6 data output GND 7 ground (0 V) 2Y 8 data output 2A, 2B, 2C, 2D 9, 10, 12, 13 data input VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nC nD nY L X X X H X L X X H X X L X H X X X L H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot SO14, and (T)SSOP14 packages [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 74HC_HCT20 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 15 74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC20 Min Typ 74HCT20 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC20 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2 - 20 - 40 A 74HC_HCT20 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 15 74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT20 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA - 0.15 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2 - 20 - 40 A ICC additional supply current per input pin; VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 30 108 - 135 - 147 A CI input capacitance - 3.5 - - - - - pF 74HC_HCT20 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 15 74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for test circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) 74HC20 propagation delay nA, nB, nC or nD to nY; see Figure 7 tpd [1] VCC = 2.0 V - 28 90 115 135 ns VCC = 4.5 V - 10 18 23 27 ns VCC = 6.0 V - 8 15 20 23 ns - 8 - - - ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 22 - - - pF - 16 28 35 42 ns VCC = 5.0 V; CL = 15 pF transition time tt [2] see Figure 7 VCC = 6.0 V power dissipation capacitance CPD per package; VI = GND to VCC [3] 74HCT20 tpd propagation delay nA, nB, nC or nD to nY; see Figure 7 [1] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF transition time tt power dissipation capacitance CPD [1] - 13 - - - ns VCC = 4.5 V; see Figure 7 [2] - 7 15 19 22 ns per package; VI = GND to VCC  1.5 V [3] - 17 - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching;  (CL  VCC2  fo) = sum of outputs. 74HC_HCT20 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 15 74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 11. Waveforms 9, Q$Q%Q& Q'LQSXW 90 *1' W3+/ 92+ Q