74LVC169

74LVC169 Presettable synchronous 4-bit up/down binary counter Rev. 05 — 8 June 2009 Product data sheet 1. General description The 74LVC169 is a synchronous presettable 4-bit binary counter which features an internal look-ahead carry circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the LOW-to-HIGH transition of the clock. The counter is fully programmable; that is, the outputs may be preset to any number between 0 and its maximum count. Presetting is synchronous with the clock and takes place regardless of the levels of the count enable inputs. A LOW level on the parallel enable (pin PE) input disables the counter and causes the data at the Dn input to be loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the counter counts up, when LOW, it counts down. The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a LOW-level output pulse with a duration approximately equal to a HIGH level portion of pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded stages. The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing the control of data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the next LOW-to-HIGH transition of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters the flip-flops on the next LOW-to-HIGH transition of the clock. NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be HIGH. The pin U/D input determines the direction of the counting. The terminal count output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW, when a counter reaches 15 in the count up mode.The pin TC output state is not a function of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For this reason the use of pin TC as a clock signal is not recommended; see the following logic equations: count enable = CEP • CET • PE count up: TC = Q3 • Q2 • Q1 • Q0 • CET • U ⁄ D count down: TC = Q3 • Q2 • Q1 • Q0 • CET • U ⁄ D 2. Features I I I I I I I I I I 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Up/down counting Two count enable inputs for n-bit cascading Built-in look-ahead carry capability Presettable for programmable operation Complies with JEDEC standard JESD8-B / JESD36 ESD protection: N HBM JESD22-A114D exceeds 2000 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Temperature range Package Name 74LVC169D 74LVC169DB −40 °C to +125 °C −40 °C to +125 °C SO16 SSOP16 TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT338-1 SOT403-1 Type number 74LVC169PW −40 °C to +125 °C 74LVC169BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1 quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 2 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 4. Functional diagram CTR4 M1 [LOAD] M2 [COUNT] 3 D0 9 1 2 7 10 PE U/D CP CEP CET Q0 14 Q1 13 Q2 12 Q3 11 3 4 5 6 1,7D [1] [2] [4] [8] 001aaa646 9 4 D1 5 D2 6 1 D3 10 7 2 M3 [UP] M4 [DOWN] G5 G6 3, 5 CT=15 4, 5 CT=0 15 2, 3, 5, 6+/C7 TC 15 2, 3, 5, 6− 14 13 12 11 001aaa645 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 3 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter D0 3 D CP Q Q 14 Q0 D1 4 D CP Q Q 13 Q1 D2 5 D CP Q Q 12 Q2 D3 6 D CP Q Q 11 Q3 PE 9 CEP 7 10 CET CP U/D 2 1 15 TC 001aaa649 Fig 3. Logic diagram 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 4 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 5. Pinning information 5.1 Pinning 74LVC169 terminal 1 index area 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 GND(1) 8 9 PE 11 Q3 10 CET GND U/D 2 3 4 5 6 7 1 CP 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 CET 9 001aaa644 74LVC169 U/D CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 D0 D1 D2 D3 CEP PE 001aaa682 Transparent top view (1) The die substrate is attached to this pad using conductive die material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO16 and (T)SSOP16 package Fig 5. Pin configuration DHVQFN16 package 5.2 Pin description Table 2. Symbol U/D CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC Pin description Pin 1 2 3, 4, 5, 6 7 8 9 10 14, 13, 12, 11 15 16 Description up/down control input clock input (LOW-to-HIGH, edge-triggered) data input count enable input (active LOW) ground (0 V) parallel enable input (active LOW) count enable carry input (active LOW) flip-flop output terminal count output (active LOW) supply voltage 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 5 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 6. Functional description Table 3. Function table[1] Input CP Parallel load (Dn to Qn) Count up (increment) Count down (decrement) Hold (do nothing) ↑ ↑ ↑ ↑ ↑ ↑ [1] Operating modes Output U/D X X h I X X CEP X X I I h X CET X X I I X X PE I l h h h h Dn I h X X X X Qn L H count up count down qn qn TC * * * * * H H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition * = The TC is LOW when CET is LOW and the counter is at terminal count Terminal count up is (HHHH) and terminal count down is (LLLL) 0 15 14 13 12 1 2 3 4 5 6 7 11 count down count up 10 9 8 001aaa647 Fig 6. State diagram 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 6 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter PE D0 D1 D2 D3 CP U/D CEP and CET Q0 Q1 Q2 Q3 TC 13 load 14 15 0 1 2 inhibit 2 2 1 0 15 14 13 count up count down 001aaa648 The following sequence is illustrated: - Load (preset) to thirteen. - Count up to fourteen, fifteen (maximum), zero, one and two. - Inhibit. - Countdown to one, zero (minimum), fifteen, fourteen and thirteen. Fig 7. Typical timing sequence 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 7 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [1] Max +6.5 +5.5 ±50 VCC + 0.5 ±50 100 +150 500 Unit V mA V mA V mA mA mA °C mW VO > VCC or VO < 0 V −0.5 −100 −65 Tamb = −40 °C to +125 °C [2] - The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SO16 packages: above 70 °C, Ptot derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 °C, Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C, Ptot derates linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature in free air VCC = 2.7 V to 3.6 V input transition rise and fall rate VCC = 1.2 V to 2.7 V Conditions for maximum speed performance for low-voltage applications Min 2.7 1.2 0 0 −40 0 0 Typ Max 3.6 3.6 5.5 VCC +125 20 10 Unit V V V V °C ns/V ns/V 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 8 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V VCC = 1.2 V VCC = 2.7 V to 3.6 V VI = VIH or VIL IO = −100 µA; VCC = 2.7 V to 3.6 V VCC − 0.2 IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II ICC ∆ICC input leakage VCC = 3.6 V; VI = 5.5 V or GND current supply current additional supply current input capacitance VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 1.65 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A VCC = 0 V to 3.6 V; VI = GND to VCC GND ±0.1 0.1 5 0.2 0.4 0.55 ±5 10 500 0.3 0.6 0.8 ±20 40 5000 V V V µA µA µA 2.2 2.4 2.2 VCC VCC − 0.3 2.05 2.25 2.0 V V V V −40 °C to +85 °C Min VCC 2.0 Typ[1] Max GND 0.8 −40 °C to +125 °C Unit Min VCC 2.0 Max GND 0.8 V V V V CI - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 9 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tpd propagation delay Conditions CP to Qn; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V CP to TC; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V CET to TC; see Figure 9 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V U/D to TC; see Figure 10 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width CP HIGH or LOW; see Figure 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time Dn to CP; see Figure 11 VCC = 2.7 V VCC = 3.0 V to 3.6 V PE to CP; see Figure 11 VCC = 2.7 V VCC = 3.0 V to 3.6 V U/D to CP; see Figure 12 VCC = 2.7 V VCC = 3.0 V to 3.6 V CEP, CET to CP; see Figure 12 VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time Dn, PE, CEP, CET, U/D to CP; see Figure 11 and 12 VCC = 2.7 V VCC = 3.0 V to 3.6 V 0.0 0.5 0.0 0.0 0.5 ns ns 5.5 4.5 2.1 5.5 4.5 ns ns 6.5 5.5 2.8 6.5 5.5 ns ns 3.5 3.0 1.2 3.5 3.0 ns ns 3.0 2.5 1.0 3.0 2.5 ns ns 5.0 4.0 1.2 5.0 4.0 ns ns [2] [2] [2] [2] −40 °C to +85 °C Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Typ[1] 17 4.0 21 4.8 19 4.1 21 3.7 Max 7.2 6.6 8.8 7.5 7.2 6.2 8.2 6.9 −40 °C to +125 °C Unit Min 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 9.0 8.5 11.0 9.5 9.0 8.0 10.5 9.0 ns ns ns ns ns ns ns ns ns ns ns ns 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 10 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter fmax maximum frequency Conditions see Figure 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(0) CPD output skew time power dissipation capacitance VCC = 3.0 V to 3.6 V per input pin; VI = GND to VCC VCC = 3.0 V to 3.6 V [3] [4] −40 °C to +85 °C Min 150 150 Typ[1] 200 20 Max 1.0 - −40 °C to +125 °C Unit Min 150 150 Max 1.5 MHz MHz ns pF [1] [2] [3] [4] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching ∑(CL × VCC2 × fo) = sum of outputs 11. Waveforms 1/fmax VI CP input GND tW t PHL VOH Qn, TC output VOL VM 001aaa651 VM t PLH Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 8. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 11 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter VI CET GND tPHL VOH TC VOL 001aaa652 VM tPLH VI VM Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 9. Input (CET) to output (TC) propagation delays VI U/D GND tPHL VOH TC VOL 001aaa653 VM tPLH VI VM Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 10. The up/down control input (U/D) to output (TC) propagation delays 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 12 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter VI PE input GND t su th VI CP input GND t su th VI Dn input GND 001aaa654 VM t su th VM t su th VM The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE) VI CEP, CET, U/D input GND th tsu VI CP input GND VM 001aaa655 VM th tsu The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Logic levels: VOL and VOH are the typical output voltage levels that occur with the output load. Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D) Table 8. VCC 1.2 V 2.7 V 3.0 V to 3.6 V Measurement points Input VM 0.5VCC 1.5 V 1.5 V Output VM 0.5VCC 1.5 V 1.5 V Supply voltage 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 13 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RL = Load resistance RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 13. Test circuit for measuring switching times Table 9. Test data Input VI 1.2 V 2.7 V 3.0 V to 3.6 V [1] Supply voltage Load tr, tf ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns CL 30 pF 50 pF 50 pF RL 500 Ω[1] 500 Ω 500 Ω S1 position tPLH: tPHL open open open VCC 2.7 V 2.7 V The circuit preforms better when RL = 1000 kΩ. 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 14 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 12. Application information CP U/D PE D0 D1 D2 D3 PE U/D CP CEP CET Q0 Q1 Q2 Q3 TC D0 D1 D2 D3 PE U/D CP CEP CET Q0 Q1 Q2 Q3 TC D0 D1 D2 D3 PE U/D CP CEP CET Q0 Q1 Q2 Q3 TC D0 D1 D2 D3 PE U/D CP CEP CET Q0 Q1 Q2 Q3 TC least significant 4-bit counter most significant 4-bit counter 001aaa650 Fig 14. Synchronous multistage counting scheme 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 15 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 15. Package outline SOT109-1 (SO16) 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 16 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT338-1 (SSOP16) 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 17 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 17. Package outline SOT403-1 (TSSOP16) 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 18 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 18. Package outline SOT763-1 (DHVQFN16) 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 19 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 14. Abbreviations Table 10. Acronym CDM DUT ESD HBM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20090608 Data sheet status Product data sheet Change notice Supersedes 74LVC169_4 Document ID 74LVC169_5 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been updated and adapted to the new company name where appropriate. Table 7 “Dynamic characteristics” 3.0 V to 3.6 V max tPLH and tPHL values changed due to ECN06_058. Product specification Product specification Product specification Product specification 74LVC169_3 74LVC169_2 74LVC169_1 - 74LVC169_4 74LVC169_3 74LVC169_2 74LVC169_1 20041014 20040512 19980520 19960823 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 20 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC169_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 8 June 2009 21 of 22 NXP Semiconductors 74LVC169 Presettable synchronous 4-bit up/down binary counter 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 June 2009 Document identifier: 74LVC169_5