74LVC332DBJ

74LVC332 Triple 3-input OR gate Rev. 1 — 20 March 2013 Product data sheet 1. General description The 74LVC332 is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits      Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC332D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVC332DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVC332PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC332BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm SOT762-1 74LVC332 NXP Semiconductors Triple 3-input OR gate 4. Functional diagram    $  &   $  <   %  $  <    &  $ •  %  Logic symbol Fig 2. < & DDD DDD Fig 1. •   &  %   <   % • IEC logic symbol Fig 3. DDD Logic diagram (one gate) 5. Pinning information 5.1 Pinning  9&& %   & WHUPLQDO LQGH[DUHD $   $   & &   % <   $ *1'   < $  < %   & &  <  *1'  %   %  &    <  <  % *1' $  9&& /9& /9& $ DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 74LVC332 Product data sheet Fig 5. Pin configuration for DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2013 © NXP B.V. 2013. All rights reserved. 2 of 14 74LVC332 NXP Semiconductors Triple 3-input OR gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 9 data input 1B, 2B, 3B 2, 4, 10 data input 1C, 2C, 3C 13, 5, 11 data input 1Y, 2Y, 3Y 12, 6, 8 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function selection[1] Input Output nA nB nC nY L L L L X X H H X H X H H X X H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current Conditions VI < 0 [1] VO > VCC or VO < 0 [2] VO = 0 V to VCC Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +5.5 V - 50 mA 0.5 VCC + 0.5 V - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 60 +150 C - 500 mW total power dissipation Ptot Tamb = 40 C to +85 C [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. [3] For (T)SSOP14 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 74LVC332 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2013 © NXP B.V. 2013. All rights reserved. 3 of 14 74LVC332 NXP Semiconductors Triple 3-input OR gate 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage functional Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature in free air 40 - +85 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 40 C to +85 C Conditions VCC = 1.2 V Product data sheet Unit Min Max Min Max 1.08 - - 1.08 - V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V VCC = 1.65 V to 1.95 V - - 0.35  VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V 0.35  VCC V VCC  0.2 - - VCC  0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC332 40 C to +125 C Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2013 © NXP B.V. 2013. All rights reserved. 4 of 14 74LVC332 NXP Semiconductors Triple 3-input OR gate Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Min Typ[1] Max Min Max Unit ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 0.5 4.6 11.6 0.5 13.4 ns VCC = 2.3 V to 2.7 V 1.0 2.7 6.6 1.0 7.6 ns VCC = 2.7 V 1.1 2.8 7.0 1.1 8.1 ns 0.8 2.4 5.9 0.8 6.8 ns VCC = 1.65 V to 1.95 V - 8.1 - - - pF VCC = 2.3 V to 2.7 V - 8.2 - - - pF VCC = 3.0 V to 3.6 V - 9.2 - - - pF nA, nB, nC to nY; see Figure 6 [2] VCC = 3.0 V to 3.6 V power dissipation capacitance CPD 40 C to +125 C Unit Typ[1] per gate; VI = GND to VCC [3] [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 74LVC332 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 March 2013 © NXP B.V. 2013. All rights reserved. 5 of 14 74LVC332 NXP Semiconductors Triple 3-input OR gate 11. AC waveforms VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW 9, Q$Q%Q& LQSXW 90 VCC *1' W3+/ W3/+ 92+ Q