BF1205C,115

BF1205C Dual N-channel dual gate MOS-FET Rev. 3 — 7 September 2011 Product data sheet 1. Product profile 1.1 General description The BF1205C is a combination of two dual gate MOS-FET amplifiers with shared source and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1 bias of amplifier b. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features and benefits  Two low noise gain controlled amplifiers in a single package; one with a fully integrated bias and one with a partly integrated bias  Internal switch to save external components  Superior cross-modulation performance during AGC  High forward transfer admittance  High forward transfer admittance to input capacitance ratio. 1.3 Applications  Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage  digital and analog television tuners  professional communication equipment. BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 1.4 Quick reference data Table 1. Quick reference data Per MOS-FET unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - - 6 V - - 30 mA - - 180 mW amplifier a; ID = 19 mA 26 31 41 mS amplifier b; ID = 13 mA 28 33 43 mS amplifier a - 2.2 2.7 pF amplifier b - 2.0 2.5 pF VDS drain-source voltage ID drain current (DC) Ptot total power dissipation Tsp  107 C yfs forward transfer admittance f = 1 MHz Cig1-ss input capacitance at gate 1 [1] f = 1 MHz Crss reverse transfer capacitance f = 1 MHz - 20 - fF NF noise figure amplifier a; f = 400 MHz - 1.3 1.9 dB amplifier b; f = 800 MHz - 1.4 2.1 dB amplifier a 100 105 - dBV amplifier b 100 103 - dBV - - 150 C Xmod input level for k = 1 % at 40 dB AGC junction temperature Tj [1] cross-modulation Tsp is the temperature at the soldering point of the source lead. 2. Pinning information Table 2. Discrete pinning Pin Description 1 gate 1 (a) 2 gate 2 Simplified outline 6 3 gate 1 (b) 4 drain (b) 5 source 6 drain (a) 1 5 2 Symbol 4 3 AMP a G1 (A) D (A) G2 S G1 (B) D (B) 001aaa706 AMP b sym033 BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 2 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 3. Ordering information Table 3. Ordering information Type number BF1205C Package Name Description Version - plastic surface mounted package; 6 leads SOT363 4. Marking Table 4. Marking Type number Marking code[1] BF1205C M6* [1] * = p or -: made in Hong Kong. * = t: made in Malaysia. * = W: made in China. 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per MOS-FET VDS drain-source voltage - 6 V ID drain current (DC) - 30 mA IG1 gate 1 current - 10 mA IG2 gate 2 current - 10 mA - 180 mW Tsp  107 C [1] Ptot total power dissipation Tstg storage temperature 65 +150 C Tj junction temperature - 150 C [1] Tsp is the temperature at the soldering point of the source lead. 6. Thermal characteristics Table 6. BF1205C Product data sheet Thermal characteristics Symbol Parameter Rth(j-s) thermal resistance from junction to soldering point Conditions All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 Typ Unit 240 K/W © NXP B.V. 2011. All rights reserved. 3 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aac193 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Tsp (˚C) Fig 1. Power derating curve. 7. Static characteristics Table 7. Static characteristics Tj = 25 C. Symbol Parameter Conditions Min Typ Max Unit amplifier a 6 - - V amplifier b 6 - - V Per MOS-FET; unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0 V; ID = 10 A V(BR)G1-SS gate 1-source breakdown voltage VGS = VDS = 0 V; IG1-S = 10 mA 6 - 10 V V(BR)G2-SS gate 2-source breakdown voltage VGS = VDS = 0 V; IG2-S = 10 mA 6 - 10 V V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 - 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 - 1.5 V VG1-S(th) gate 1-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 A 0.3 - 1.0 V VG2-S(th) gate 2-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 A 0.4 - 1.0 V IDSX drain-source current VG2-S = 4 V; VDS(b) = 5 V; RG1 = 150 k IG1-S IG2-S gate 1 cut-off current gate 2 cut-off current 14 - 24 mA amplifier b [2] 9 - 17 mA amplifier a; VG1-S(a) = 5 V; ID(b) = 0 A - - 50 nA amplifier b; VG1-S(b) = 5 V; VDS(b) = 0 V - - 50 nA - - 20 nA VG2-S = 4 V; VG1-S(a) = VDS(a) = VDS(b) = 0 V; VG1-S(b) = 0 V; [1] RG1 connects gate 1 (b) to VGG = 0 V (see Figure 3). RG1 connects gate 1 (b) to VGG = 5 V (see Figure 3). Product data sheet [1] VG2-S = VDS(a) = 0 V [2] BF1205C amplifier a; VDS(a) = 5 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 4 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa552 20 ID (mA) 16 (1) (2) 12 (3) G1 (A) D (A) 8 (4) G2 S 4 (6) (5) G1 (B) D (B) RG1 0 0 1 2 3 4 5 VGG VGG (V) 001aaa553 (1) ID(b); RG1 = 120 k. VGG = 5 V: amplifier a is off; amplifier b is on (2) ID(b); RG1 = 150 k. VGG = 0 V: amplifier a is on; amplifier b is off. (3) ID(b); RG1 = 180 k. (4) ID(a); RG1 = 180 k. (5) ID(a); RG1 = 150 k. (6) ID(a); RG1 = 120 k. Fig 2. Drain currents of MOS-FET a and b as function of VGG. Fig 3. Functional diagram. 8. Dynamic characteristics 8.1 Dynamic characteristics for amplifier a Table 8. Dynamic characteristics for amplifier a[1] Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA. Symbol Parameter Conditions Min Typ Max Unit yfs forward transfer admittance Tj = 25 C 26 31 41 mS Cig1-ss input capacitance at gate 1 f = 1 MHz - 2.2 2.7 pF Cig2-ss input capacitance at gate 2 f = 1 MHz - 3.0 - pF Coss output capacitance f = 1 MHz - 0.9 - pF Crss reverse transfer capacitance f = 1 MHz - 20 - fF Gtr power gain BS = BS(opt); BL = BL(opt) f = 200 MHz; GS = 2 mS; GL = 0.5 mS 31 35 39 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 26 30 34 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 21 25 29 dB f = 11 MHz; GS = 20 mS; BS = 0 S - 3.0 - dB f = 400 MHz; YS = YS(opt) - 1.3 1.9 dB f = 800 MHz; YS = YS(opt) - 1.4 2.1 dB NF noise figure BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 5 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET Table 8. Dynamic characteristics for amplifier a[1] …continued Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA. Symbol Parameter Xmod Conditions cross-modulation Min Typ Max Unit at 0 dB AGC 90 - - dBV at 10 dB AGC - 90 - dBV at 20 dB AGC - 99 - dBV at 40 dB AGC 100 105 - dBV input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] For the MOS-FET not in use: VG1-S(b) = 0 V; VDS(b) = 0 V. [2] Measured in Figure 33 test circuit. [2] 8.1.1 Graphs for amplifier a 001aaa554 30 001aaa555 32 (1) ID (mA) (2) ID (mA) (3) (1) (2) (4) 24 (3) 20 (4) (5) 16 (5) (6) 10 (7) (6) 8 (8) (9) (7) 0 0 0 0.4 0.8 1.2 1.6 2 VG1-S (V) 0 2 6 VDS (V) (1) VG2-S = 4 V. (1) VG1-S(a) = 1.8 V. (2) VG2-S = 3.5 V. (2) VG1-S(a) = 1.7 V. (3) VG2-S = 3 V. (3) VG1-S(a) = 1.6 V. (4) VG2-S = 2.5 V. (4) VG1-S(a) = 1.5 V. (5) VG2-S = 2 V. (5) VG1-S(a) = 1.4 V. (6) VG2-S = 1.5 V. (6) VG1-S(a) = 1.3 V. (7) VG2-S = 1 V. (7) VG1-S(a) = 1.2 V. VDS(a) = 5 V; VG1-S(b) = VDS(b) = 0 V; Tj = 25 C. 4 (8) VG1-S(a) = 1.1 V. (9) VG1-S(a) = 1 V. VG2-S = 4 V; VG1-S(b) = VDS(b) = 0 V; Tj = 25 C. Fig 4. Transfer characteristics; typical values. BF1205C Product data sheet Fig 5. Output characteristics; typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 6 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa556 40 yfs (mS) ID (a) (mA) 16 (1) (2) 30 001aaa557 20 12 20 (3) 8 (4) 10 4 (5) (6) 0 0 0 8 16 24 0 32 20 40 60 ID (b) (μA) ID (mA) (1) VG2-S = 4 V. VDS(a) = 5 V; VG2-S = 4 V; VDS(b) = 5 V; VG1-S(b) = 0 V; Tj = 25 C. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. VDS(a) = 5 V; VG1-S(b) = VDS(b) = 0 V; Tj = 25 C. Fig 6. Forward transfer admittance as a function of drain current; typical values. BF1205C Product data sheet Fig 7. Drain current as a function of internal G1 current (current in pin drain (b) if MOS-FET (b) is switched off); typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 7 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa558 20 ID (mA) 16 001aaa559 32 ID (mA) 24 (1) 12 (2) (3) 16 (4) (5) 8 (6) 8 4 0 0 0 1 2 3 4 5 0 2 4 Vsup (V) VDS(a) = VDS(b) = Vsupply, VG2-S = 4 V, Tj = 25 C, RG1(b) = 150 k (connected to ground); see Figure 3. 6 VG2-S (V) (1) VDS(b) = 5 V. (2) VDS(b) = 4.5 V. (3) VDS(b) = 4 V. (4) VDS(b) = 3.5 V. (5) VDS(b) = 3 V. (6) VDS(b) = 2.5 V. VDS(a) = 5 V; VG1-S(b) = 0 V; gate 1 (a) = open; Tj = 25 C. Fig 8. Drain current of amplifier a as a function of supply voltage of a and b amplifier; typical values. 001aaa560 120 Fig 9. Drain current as a function of gate 2 and drain supply voltage; typical values. 001aaa561 0 gain reduction (dB) 10 Vunw (dBμV) 110 20 100 30 90 40 80 50 0 10 20 30 40 50 gain reduction (dB) VDS(a) = VDS(b) = 5 V; VG1-S(b) = 0 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C; see Figure 33. Fig 10. Unwanted voltage for 1 % cross-modulation as a function of gain reduction; typical values. BF1205C Product data sheet 0 1 2 3 4 VAGC (V) VDS(a) = VDS(b) = 5 V; VG1-S(b) = 0 V; f = 50 MHz; see Figure 33. Fig 11. Gain reduction as a function of AGC voltage; typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 8 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa562 32 001aaa564 102 bis, gis (mS) ID (mA) 10 24 bis 16 1 8 10−1 gis 10−2 0 0 20 40 60 gain reduction (dB) 10 Fig 12. Drain current as a function of gain reduction; typical values. 001aaa565 yfs (mS) 102 −ϕfs (deg) yfs VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V; ID(a) = 19 mA. Fig 13. Input admittance as a function of frequency; typical values. 001aaa566 103 −ϕrs 10 102 yrs −ϕfs 10 1 10 1 103 102 10 1 10 f (MHz) Fig 14. Forward transfer admittance and phase as a function of frequency; typical values. Product data sheet 1 103 102 f (MHz) VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V; ID(a) = 19 mA. BF1205C 103 −ϕrs (deg) yrs (mS) 102 10 103 f (MHz) VDS(a) = VDS(b) = 5 V; VG1-S(b) = 0 V; f = 50 MHz; Tamb = 25 C; see Figure 33. 102 102 VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V; ID(a) = 19 mA. Fig 15. Reverse transfer admittance and phase as a function of frequency: typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 9 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa567 10 bos, gos (mS) bos 1 gos 10−1 10−2 102 10 103 f (MHz) VDS(a) = 5 V; VG2-S(a) = 4 V; VDS(b) = VG1-S(b) = 0 V; ID(a) = 19 mA. Fig 16. Output admittance as a function of frequency; typical values. 8.1.2 Scattering parameters for amplifier a Table 9. Scattering parameters for amplifier a VDS(a) = 5 V; VG2-S = 4 V; ID(a) = 19 mA; VDS(b) = 0 V; VG-1S(b) = 0 V; Tamb = 25 C. f (MHz) S11 S21 S12 Magnitude ratio Angle (deg) Magnitude ratio Angle (deg) 50 0.992 3.91 3.07 100 0.990 7.76 3.06 200 0.982 300 S22 Magnitude ratio Angle (deg) Magnitude ratio Angle (deg) 175.56 0.0007 83.61 0.992 1.47 171.18 0.0017 83.19 0.992 2.93 15.42 3.04 162.42 0.0026 78.19 0.990 5.84 0.971 22.99 3.01 153.79 0.0037 73.75 0.988 8.71 400 0.956 30.52 2.96 145.22 0.0047 69.82 0.985 11.59 500 0.938 37.83 2.90 136.78 0.0055 66.12 0.982 14.48 600 0.917 45.14 2.83 128.46 0.0061 62.11 0.979 17.31 700 0.893 52.31 2.76 120.20 0.0065 58.86 0.975 20.14 800 0.867 59.47 2.69 111.98 0.0068 58.28 0.972 22.98 900 0.838 66.23 2.60 103.90 0.0067 50.64 0.968 25.85 1000 0.807 73.10 2.52 95.875 0.0065 47.28 0.966 28.74 8.1.3 Noise data for amplifier a Table 10. Noise data for amplifier a VDS(a) = 5 V; VG2-S = 4 V; ID(a) = 19 mA; VDS(b) = 0 V; VG-1S(b) = 0 V; Tamb = 25 C. BF1205C Product data sheet f (MHz) Fmin (dB) opt ratio (deg) rn () 400 1.3 0.718 16.06 0.683 800 1.4 0.677 37.59 0.681 All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 10 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 8.2 Dynamic characteristics for amplifier b Table 11. Dynamic characteristics for amplifier b Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 13 mA. Symbol Parameter Conditions Min Typ Max Unit yfs forward transfer admittance Tj = 25 C 28 33 43 Cig1-ss input capacitance at gate 1 f = 1 MHz - 2.0 2.5 pF Cig2-ss input capacitance at gate 2 f = 1 MHz - 3.4 - pF Coss output capacitance f = 1 MHz - 0.85 - pF Crss reverse transfer capacitance f = 1 MHz - 20 - fF f = 200 MHz; GS = 2 mS; GL = 0.5 mS 31 35 39 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 28 32 36 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 24 28 32 dB f = 11 MHz; GS = 20 mS; BS = 0 S - 5 - dB f = 400 MHz; YS = YS(opt) - 1.3 1.9 dB - 1.4 2.1 dB at 0 dB AGC 90 - - dBV at 10 dB AGC - 88 - dBV at 20 dB AGC - 94 - dBV at 40 dB AGC 100 103 - dBV power gain Gtr NF noise figure BS = BS(opt); BL = BL(opt) [1] f = 800 MHz; YS = YS(opt) Xmod cross-modulation input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] For the MOS-FET not in use: VG1-S(a) = 0 V; VDS(a) = 0 V. [2] Measured in Figure 34 test circuit. BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 mS [2] © NXP B.V. 2011. All rights reserved. 11 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 8.2.1 Graphs for amplifier b 001aaa568 (1) (4) 30 ID (mA) (2) ID (mA) 001aaa569 32 (1) (3) 24 (2) (5) 20 (3) (4) 16 (5) (6) 10 (6) 8 (7) (7) 0 0 0 0.4 0.8 1.2 1.6 2 VG1-S (V) 0 2 4 6 VDS (V) (1) VG2-S = 4 V. (1) VG1-S(b) = 1.6 V. (2) VG2-S = 3.5 V. (2) VG1-S(b) = 1.5 V. (3) VG2-S = 3 V. (3) VG1-S(b) = 1.4 V. (4) VG2-S = 2.5 V. (4) VG1-S(b) = 1.3 V. (5) VG2-S = 2 V. (5) VG1-S(b) = 1.2 V. (6) VG2-S = 1.5 V. (6) VG1-S(b) = 1.1 V. (7) VG2-S = 1 V. (7) VG1-S(b) = 1 V. VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C. VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C. Fig 17. Transfer characteristics; typical values. Fig 18. Output characteristics; typical values. BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 12 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa570 100 (1) IG1 (μA) 80 (2) (3) 001aaa571 (1) (2) 40 yfs (mS) (3) 30 (4) (4) 60 20 40 (5) (5) 10 20 (6) (6) (7) (7) 0 0 0 0.4 0.8 1.2 0 1.6 2 VG1-S (V) 8 (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (7) VG2-S = 1 V. VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C. 001aaa572 24 24 32 ID (mA) (1) VG2-S = 4 V. Fig 19. Gate 1 current as a function of gate 1 voltage; typical values. 16 VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C. Fig 20. Forward transfer admittance as a function of drain current; typical values. 001aaa573 16 ID (mA) ID (mA) 12 16 8 8 4 0 0 10 20 30 40 50 IG1 (μA) VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C. Fig 21. Drain current as a function of gate 1 current; typical values. BF1205C Product data sheet 0 0 1 2 3 4 5 VGG (V) VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C; RG1(b) = 150 k (connected to VGG); see Figure 3. Fig 22. Drain current as a function of gate 1 supply voltage (VGG); typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 13 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa574 24 001aaa575 16 (1) ID (mA) (1) ID (mA) (2) (3) (2) 12 (4) (3) 16 (5) (4) (5) 8 (6) (7) (8) 8 4 0 0 0 2 4 6 0 VGG = VDS (V) 2 4 6 VG2-S (V) (1) RG1(b) = 68 k. (1) VGG = 5.0 V. (2) RG1(b) = 82 k. (2) VGG = 4.5 V. (3) RG1(b) = 100 k. (3) VGG = 4.0 V. (4) RG1(b) = 120 k. (4) VGG = 3.5 V. (5) RG1(b) = 150 k. (5) VGG = 3.0 V. VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C; RG1(b) = 150 k (connected to VGG); see Figure 3. (6) RG1(b) = 180 k. (7) RG1(b) = 220 k. (8) RG1(b) = 270 k. VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C; RG1(b) is connected to VGG; see Figure 3. Fig 23. Drain current as a function of gate 1 (VGG), drain supply voltage and value of RG1; typical values. BF1205C Product data sheet Fig 24. Drain current as a function of gate 2 voltage; typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 14 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa576 30 Vunw (dBμV) (1) IG1 (μA) (2) 20 001aaa577 120 110 (3) (4) 100 (5) 10 90 80 0 0 2 4 6 0 20 VG2-S (V) 40 60 gain reduction (dB) VDS(b) = 5 V; VGG = 5 V; VDS(a) = VG1-S(a) = 0 V; RG1(b) = 150 k (connected to VGG); fw = 50 MHz; funw = 60 MHz; Tamb = 25 C; see Figure 34. (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS(b) = 5 V; VDS(a) = VG1-S(a) = 0 V; Tj = 25 C; RG1(b) = 150 k (connected to VGG); see Figure 3. Fig 25. Gate 1 current as a function of gate 2 voltage; typical values. 001aaa578 0 gain reduction (dB) 10 Fig 26. Unwanted voltage for 1 % cross-modulation as a function of gain reduction; typical values. 001aaa579 16 ID (mA) 12 20 8 30 4 40 0 50 0 1 2 3 4 0 VAGC (V) VDS(b) = 5 V; VGG = 5 V; VDS(a) = VG1-S(a) = 0 V; RG1(b) = 150 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Figure 34. Fig 27. Typical gain reduction as a function of AGC voltage. BF1205C Product data sheet 20 40 60 gain reduction (dB) VDS(b) = 5 V; VGG = 5 V; VDS(a) = VG1-S(a) = 0 V; RG1(b) = 150 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Figure 34. Fig 28. Drain current as a function of gain reduction; typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 15 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 001aaa581 102 001aaa582 102 102 bis, gis (mS) yfs yfs (mS) 10 −ϕfs (deg) bis 1 10 10 −ϕfs gis 10−1 10−2 10 102 1 103 10 f (MHz) f (MHz) VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; ID(b) = 13 mA. Fig 29. Input admittance as a function of frequency; typical values. 001aaa583 103 103 −ϕrs (deg) yrs (μS) −ϕrs 102 1 103 102 102 VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; ID(b) = 13 mA. Fig 30. Forward transfer admittance and phase as a function of frequency; typical values. 001aaa584 10 bos, gos (mS) bos 1 yrs gos 10 10 1 10 1 103 102 10−1 10−2 10 VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; ID(b) = 13 mA. Fig 31. Reverse transfer admittance and phase as a function of frequency; typical values. BF1205C Product data sheet 102 103 f (MHz) f (MHz) VDS(b) = 5 V; VG2-S = 4 V; VDS(a) = VG1-S(a) = 0 V; ID(b) = 13 mA. Fig 32. Output admittance as a function of frequency; typical values. All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 16 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 8.2.2 Scattering parameters for amplifier b Table 12. Scattering parameters for amplifier b VDS(b) = 5 V; VG2-S = 4 V; ID(b) = 13 mA; VDS(a) = 0 V; VG1-S(a) = 0 V; Tamb = 25 C. f (MHz) S11 S21 50 0.986 3.66 3.26 100 0.982 7.01 3.24 S12 Magnitude Angle Magnitude ratio (deg) ratio Angle (deg) S22 Magnitude ratio Angle Magnitude (deg) ratio Angle (deg) 175.93 0.0008 84.23 0.988 1.65 172.04 0.0015 84.91 0.988 3.27 200 0.975 13.71 3.22 164.24 0.0029 83.96 0.986 6.50 300 0.966 20.36 3.19 156.53 0.0042 82.86 0.984 9.69 400 0.955 27.04 3.15 148.86 0.0055 81.88 0.982 12.88 500 0.943 33.62 3.10 141.24 0.0066 80.92 0.978 16.07 600 0.927 40.16 3.05 133.70 0.0076 80.15 0.975 19.21 700 0.909 46.70 2.99 126.13 0.0086 79.68 0.972 22.35 800 0.891 52.07 2.92 118.64 0.0094 78.28 0.968 25.52 900 0.868 59.48 2.84 111.09 0.0100 78.28 0.965 28.65 1000 0.846 65.86 2.77 103.58 0.0107 78.15 0.961 31.85 8.2.3 Noise data for amplifier b Table 13. Noise data for amplifier b VDS(b) = 5 V; VG2-S = 4 V; ID(b) = 13 mA; VDS(a) = 0 V; VG1-S(a) = 0 V; Tamb = 25 C. BF1205C Product data sheet f (MHz) Fmin (dB) opt ratio (deg) rn () 400 1.3 0.695 13.11 0.694 800 1.4 0.674 32.77 0.674 All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 17 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 9. Test information VDS(a) VAGC 5V 4.7 nF 10 kΩ 4.7 nF RGEN 50 Ω g2 4.7 nF Vi BF1205C g1 (b) 50 Ω 4.7 nF d (a) g1 (a) 4.7 nF 50 Ω L1 2.2 μH RL 50 Ω S d (b) L2 2.2 μH RG1 4.7 nF VGG VDS(b) 0V 5V 001aaa563 Fig 33. Cross-modulation test set-up for amplifier a. VDS(a) VAGC 5V 4.7 nF 10 kΩ 4.7 nF 50 Ω d (a) g1 (a) 4.7 nF g2 4.7 nF RGEN 50 Ω L1 2.2 μH g1 (b) 50 Ω BF1205C S 4.7 nF d (b) L2 2.2 μH RG1 RL 50 Ω 4.7 nF Vi VGG 5V VDS(b) 5V 001aaa580 Fig 34. Cross-modulation test set-up for amplifier b. BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 18 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 10. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 c bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 35. Package outline. BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 19 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 11. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes BF1205C v.3 20110907 Product data sheet - BF1205C v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. BF1205C v.2 20060815 Product data sheet - BF1205C v.1 BF1205C v.1 (9397 750 13005) 20040518 Product data sheet - - BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 20 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 12. Legal information 12.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 21 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com BF1205C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 7 September 2011 © NXP B.V. 2011. All rights reserved. 22 of 23 BF1205C NXP Semiconductors Dual N-channel dual gate MOS-FET 14. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.2 8.2.1 8.2.2 8.2.3 9 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics for amplifier a . . . . . . . 5 Graphs for amplifier a . . . . . . . . . . . . . . . . . . . . 6 Scattering parameters for amplifier a . . . . . . . 10 Noise data for amplifier a . . . . . . . . . . . . . . . . 10 Dynamic characteristics for amplifier b . . . . . . 11 Graphs for amplifier b . . . . . . . . . . . . . . . . . . . 12 Scattering parameters for amplifier b . . . . . . . 17 Noise data for amplifier b . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 September 2011 Document identifier: BF1205C