BLD6G21L-50,112

BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Rev. 2 — 17 August 2010 Product data sheet 1. Product profile 1.1 General description The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution using NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The main and peak device, input splitter and output combiner are integrated in a single package. This package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier and the other is not connected. It only requires the proper input/output match and bias setting as with a normal class-AB transistor. Table 1. Typical performance RF performance at Th = 25 °C. Mode of operation TD-SCDMA [1][2] f VDS PL(AV) Gp ηD ACPR PL(3dB) (MHz) (V) (W) (dB) (%) (dBc) (W) 2010 to 2025 28 8 14.5 43 −24 53 [1] Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. [2] IDq = 170 mA (main); VGS(amp)peak = 0 V. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features and benefits „ Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz: ‹ Average output power = 8 W ‹ Power gain = 14.5 dB ‹ Efficiency = 43 % „ Fully optimized integrated Doherty concept: ‹ integrated asymmetrical power splitter at input ‹ integrated power combiner ‹ peak biasing down to 0 V ‹ low junction temperature ‹ high efficiency „ 100 % peak power tested for guaranteed output power capability BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor „ „ „ „ „ „ Integrated ESD protection Good pair match (main and peak on the same chip) Independent control of main and peak bias Internally matched for ease of use Excellent ruggedness Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances (RoHS) 1.3 Applications „ High efficiency RF power amplifiers with digital pre-distortion for TD-SCDMA multi carrier applications in the 2010 MHz to 2025 MHz range. 2. Pinning information Table 2. Pinning Pin Description Simplified outline Graphic symbol BLD6G21L-50 (SOT1130A) 1 drain 2 gate + bias main 3 source 4 n.c. 5 bias peak 1 1 [1] 5 2 3 3 2 4 001aak920 5 BLD6G21LS-50 (SOT1130B) 1 drain 2 gate + bias main 3 source 4 n.c. 5 bias peak 1 1 [1] 5 2 3 3 001aak920 2 4 [1] 5 Connected to flange. 3. Ordering information Table 3. Ordering information Type number BLD6G21L-50 Package Name Description Version - flanged ceramic package; 2 mounting holes; 4 leads SOT1130A earless flanged ceramic package; 4 leads SOT1130B BLD6G21LS-50 - BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 2 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 4. Block diagram RF-input/bias main main amplifier 2 90° 90° 1 bias peak peak amplifier 5 RF-output/VDS 001aak932 Fig 1. Block diagram of BLD6G21L-50 and BLD6G21LS-50 5. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Valid for both main and peak device. Symbol Parameter VDS Conditions Min Max Unit drain-source voltage - 65 V VGS(amp)main main amplifier gate-source voltage −0.5 +13 V VGS(amp)peak peak amplifier gate-source voltage −0.5 +13 V ID drain current - 10.2 A Tstg storage temperature −65 +150 °C Tj junction temperature - 200 °C 6. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-case) thermal resistance from junction to case [1] Tcase = 80 °C; PL = 8 W [1] Typ Unit 2.1 K/W When operated with a 6-carrier TD-SCDMA modulated signal with PAR = 10.8 dB at 0.01 % probability on CCDF. 7. Characteristics Table 6. Characteristics Valid for both main and peak device. Symbol Parameter Conditions V(BR)DSS drain-source breakdown voltage Min Typ Max Unit VGS = 0 V; ID = 0.62 mA 65 - - V VGS(th) gate-source threshold voltage VDS = 10 V; ID = 31 mA 1.4 1.8 2.4 V VGSq gate-source quiescent voltage VDS = 28 V; ID = 170 mA 1.55 2.05 2.55 V IDSS drain leakage current VGS = 0 V; VDS = 28 V - 1.4 μA IDSX drain cut-off current VGS = VGS(th) + 3.75 V; VDS = 10 V 4.95 5.5 - A BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 - © NXP B.V. 2010. All rights reserved. 3 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Table 6. Characteristics …continued Valid for both main and peak device. Symbol Parameter Conditions Min Typ Max Unit IGSS gate leakage current VGS = 11 V; VDS = 0 V - - 140 nA gfs forward transconductance VDS = 10 V; ID = 1.55 A 1.4 2.2 - S RDS(on) drain-source on-state resistance VGS = VGS(th) + 3.75 V; ID = 1.085 A - 0.52 0.736 Ω 8. Application information Table 7. Application information Mode of operation: 6-carrier TD-SCDMA; PAR 10.8 dB at 0.01 % probability on CCDF; f = 2017.5 MHz; RF performance at VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; unless otherwise specified; in a production circuit. Symbol Parameter Conditions Min Typ Max Unit PL(AV) average output power - 8 - W Gp power gain PL(AV) = 8 W 13 14.5 - dB ηD PARO drain efficiency PL(AV) = 8 W 39 43 - % output peak-to-average ratio PL(AV) = 8 W - 9.4 - dB RLin input return loss PL(AV) = 8 W 8 23 - dB ACPR adjacent channel power ratio PL(AV) = 8 W - −24 −20 dBc Table 8. Application information Mode of operation: Pulsed CW; δ = 10 %; tp = 100 μs; RF performance at VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; unless otherwise specified; in a production circuit. Symbol Parameter Conditions PL(3dB) output power at 3 dB gain compression Min Typ Max Unit 46 53 - W 8.1 Ruggedness in Doherty operation The BLD6G21L-50 and BLD6G21LS-50 are capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the following conditions: VDS = 28 V; IDq = 170 mA; PL = 8 W (TD-SCDMA); f = 2017.5 MHz. 8.2 Impedance information Table 9. Typical impedance Measured Load Pull data; typical values unless otherwise specified. f ZS ZL MHz Ω Ω 1995 3.5 − 12.3j 6.7 − 6.1j 2010 3.6 − 12.7j 6.7 − 6.1j 2017.5 3.6 − 12.7j 6.7 − 5.7j 2025 3.7 − 12.7j 6.4 − 5.2j 2040 4.0 − 12.9j 5.7 − 4.8j BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 4 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor drain ZL gate ZS 001aaf059 Fig 2. Definition of transistor impedance 8.3 Performance curves Performance curves are measured in a BLD6G21L-50 application circuit. 8.3.1 CW pulsed 001aam428 17 001aam429 60 ηD (%) Gp (dB) 15 (1) (2) (3) (4) (5) (6) 40 (6) (5) (4) (3) (2) (1) 13 20 11 0 30 35 40 45 50 30 35 PL (dBm) 45 50 PL (dBm) VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; δ = 10 %; tp = 100 μs on 1 ms period. VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; δ = 10 %; tp = 100 μs on 1 ms period. (1) VGS(amp)peak = 0 V (1) VGS(amp)peak = 0 V (2) VGS(amp)peak = 0.2 V (2) VGS(amp)peak = 0.2 V (3) VGS(amp)peak = 0.4 V (3) VGS(amp)peak = 0.4 V (4) VGS(amp)peak = 0.5 V (4) VGS(amp)peak = 0.5 V (5) VGS(amp)peak = 0.6 V (5) VGS(amp)peak = 0.6 V (6) VGS(amp)peak = 0.8 V (6) VGS(amp)peak = 0.8 V Fig 3. 40 Power gain as a function of load power; typical values Fig 4. Drain efficiency as a function of load power; typical values BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 5 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 001aam430 16 001aam431 60 ηD (%) Gp (dB) 14 (3) (2) (1) 40 (1) (2) (3) 12 20 10 0 30 36 42 48 30 35 40 PL (dBm) 50 PL (dBm) VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; δ = 10 %; tp = 100 μs on 1 ms period. VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; δ = 10 %; tp = 100 μs on 1 ms period. (1) f = 2010 MHz (1) f = 2010 MHz (2) f = 2018 MHz (2) f = 2018 MHz (3) f = 2025 MHz (3) f = 2025 MHz Fig 5. 45 Power gain as a function of load power; typical values Fig 6. Drain efficiency as a function of load power; typical values 001aam432 50 RLin (dB) 40 30 20 (3) (2) (1) 10 0 30 36 42 48 PL (dBm) VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; δ = 10 %; tp = 100 μs on 1 ms period. (1) f = 2010 MHz (2) f = 2018 MHz (3) f = 2025 MHz Fig 7. Input return loss as a function of load power; typical values BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 6 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 8.3.2 TD-SCDMA 001aam433 17 001aam434 48 ηD (%) Gp (dB) 15 (1) (2) (3) (4) (5) (6) 32 (6) (5) (4) (3) (2) (1) 13 16 11 0 22 30 38 46 22 30 PL(AV) (dBm) 46 PL(AV) (dBm) VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. (1) VGS(amp)peak = 0 V (1) VGS(amp)peak = 0 V (2) VGS(amp)peak = 0.2 V (2) VGS(amp)peak = 0.2 V (3) VGS(amp)peak = 0.4 V (3) VGS(amp)peak = 0.4 V (4) VGS(amp)peak = 0.5 V (4) VGS(amp)peak = 0.5 V (5) VGS(amp)peak = 0.6 V (5) VGS(amp)peak = 0.6 V (6) VGS(amp)peak = 0.8 V (6) VGS(amp)peak = 0.8 V Fig 8. 38 Power gain as a function of average load power; typical values Fig 9. Drain efficiency as a function of average load power; typical values BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 7 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 001aam435 16 ηD Gp (dB) 43 ηD (%) 42 15.5 41 15 40 Gp 39 14.5 38 14 0 0.2 0.4 37 0.6 0.8 VGS(amp)peak (V) VDS = 28 V; IDq = 170 mA; PL(AV) = 8 W; Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. Fig 10. Power gain and drain efficiency as function of peak amplifier gate-source voltage; typical values 001aam436 16 001aam437 48 ηD (%) Gp (dB) 14 32 (1) (2) (3) 12 (1) (2) (3) 16 10 0 22 26 30 34 38 42 PL(AV) (dBm) VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. 18 34 42 PL(AV) (dBm) VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. (1) f = 2010 MHz (1) f = 2010 MHz (2) f = 2018 MHz (2) f = 2018 MHz (3) f = 2025 MHz (3) f = 2025 MHz Fig 11. Power gain as a function of average load power; typical values 26 Fig 12. Drain efficiency as a function of average load power; typical values BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 8 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 9. Test information VGS(amp)main VDD C2 R1 C6 C7 C11 L1 VGS(amp)peak C3 C12 C13 INPUT BLD6G21-50-V2 C19 C9 C20 C10 C21 C1 C17 C18 C14 L2 C4 C15 R2 C16 C5 OUTPUT C8 BLD6G21-50-V2 001aak944 The striplines are on a double copper-clad gold plated Rogers 4350B Printed-Circuit Board (PCB) with εr = 3.5 and thickness = 0.76 mm. See Table 10 for list of components. Fig 13. Component layout Table 10. List of components See Figure 13 for component layout. Component Description Value Dimensions [1] C1, C3, C5, C18 multilayer ceramic chip capacitor 9.1 pF C2, C4, C12, C15 multilayer ceramic chip capacitor 100 nF C6 electrolytic capacitor 470 μF; 63 V C7, C8 multilayer ceramic chip capacitor 10 μF C9, C10 multilayer ceramic chip capacitor 1.5 pF [1] C11, C13, C14, C16 multilayer ceramic chip capacitor 8.2 pF [1] C17 multilayer ceramic chip capacitor 1.2 pF [1] C19, C20 multilayer ceramic chip capacitor 0.7 pF [1] C21 multilayer ceramic chip capacitor 1.2 pF [1] L1, L2 copper wire - diameter = 0.8 mm; length = 8 mm R1 SMD resistor 3.6 Ω 1206 R2 SMD resistor 33 Ω 1206 [1] American Technical Ceramics type 100B or capacitor of same quality. BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 9 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 10. Package outline Flanged ceramic package; 2 mounting holes; 4 leads SOT1130A D A F D1 L U1 B q C c 1 H U2 E1 p E 3 w1 A 4 2 b b1 C Q 5 10 mm scale Dimensions mm B 5 w2 0 Unit(1) A A max 4.65 nom min 3.76 b b1 1.14 5.26 0.89 5.00 p Q(2) 0.18 9.65 9.65 9.65 9.65 1.14 17.12 3.00 3.30 1.70 0.10 9.40 9.40 9.40 9.40 0.89 16.10 2.69 2.92 1.45 c D D1 E E1 F H L q U1 U2 20.19 9.65 0.805 0.39 0.6 0.01 0.02 0.795 0.38 Note 1. millimeter dimensions are derived from the original inch dimensions. 2. dimension is measured 0.030 inch (0.76 mm) from the body. Outline version References IEC JEDEC JEITA w2 0.25 0.51 15.24 max 0.183 0.045 0.207 0.007 0.38 0.38 0.38 0.38 0.045 0.674 0.118 0.130 0.067 inches nom min 0.148 0.035 0.197 0.004 0.37 0.37 0.37 0.37 0.035 0.634 0.106 0.115 0.057 w1 20.45 9.91 sot1130a_po European projection Issue date 09-10-12 10-02-02 SOT1130A Fig 14. Package outline SOT1130A BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 10 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Earless flanged ceramic package; 4 leads SOT1130B D A F 3 D1 L D U1 c 1 U2 H E1 E Z Z1 α 4 2 b b1 5 w2 0 Q 5 10 mm scale Dimensions Unit(1) D A b b1 c D D1 E E1 1.14 5.26 0.18 9.65 9.65 9.65 9.65 1.14 17.12 3.00 1.70 9.91 9.91 0.89 5.00 0.10 9.40 9.40 9.40 9.40 0.89 16.10 2.69 1.45 9.65 9.65 max 0.183 0.045 0.207 0.007 0.38 inches nom min 0.148 0.035 0.197 0.004 0.37 0.38 0.38 0.38 0.045 0.674 0.118 0.069 0.39 0.39 0.37 0.37 0.37 0.035 0.634 0.106 0.059 0.38 0.38 mm max 4.65 nom min 3.76 F H L Q U1 U2 w2 Z 0.51 0.02 References IEC JEDEC JEITA 64° 2.79 5.41 62° 0.120 0.223 64° 0.110 0.213 62° Note 1. millimeter dimensions are derived from the original inch dimensions. 2. dimension is measured 0.030 inch (0.76 mm) from the body. Outline version α Z1 3.05 5.66 sot1130b_po European projection Issue date 09-10-12 09-12-14 SOT1130B Fig 15. Package outline SOT1130B BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 11 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 11. Abbreviations Table 11. Abbreviations Acronym Description CCDF Complementary Cumulative Distribution Function CW Continuous Wave LDMOS Laterally Diffused Metal-Oxide Semiconductor PAR Peak-to-Average power Ratio RF Radio Frequency SMD Surface Mounted Device TD-SCDMA Time Division-Synchronous Code Division Multiple Access VSWR Voltage Standing-Wave Ratio 12. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes BLD6G21L-50_BLD6G21LS-50 v.2 20100817 Product data sheet - BLD6G21L-50_ BLD6G21LS-50 v.1 Modifications: BLD6G21L-50_BLD6G21LS-50 v.1 • • • • • • Figure 1 on page 3: Some corrections have been made. Table 5 on page 3: The typical value of Rth(j-case) has been changed. Table 6 on page 3: The values of IDSX have been changed. Table 7 on page 4: Several values have been changed or added. Table 8 on page 4: Table has been added. Section 8.3 on page 5: Figures have been updated. 20091028 Objective data sheet BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 - - © NXP B.V. 2010. All rights reserved. 12 of 15 BLD6G21L-50; BLD6G21LS-50 NXP Semiconductors TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 13 of 15 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com BLD6G21L-50_BLD6G21LS-50 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 17 August 2010 © NXP B.V. 2010. All rights reserved. 14 of 15 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 15. Contents 1 1.1 1.2 1.3 2 3 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Application information. . . . . . . . . . . . . . . . . . . 4 Ruggedness in Doherty operation . . . . . . . . . . 4 Impedance information . . . . . . . . . . . . . . . . . . . 4 Performance curves . . . . . . . . . . . . . . . . . . . . . 5 CW pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TD-SCDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 August 2010 Document identifier: BLD6G21L-50_BLD6G21LS-50