CBTL02043BBQ

CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 Rev. 1 — 10 March 2011 Product data sheet 1. General description CBTL02043A/B is a 2 differential channel, 2-to-1 multiplexer/demultiplexer switch for PCI Express Generation 3 (Gen3), or other high-speed serial interface applications. The CBTL02043A/B can switch two differential signals to one of two locations. Using a unique design technique, NXP has minimized the impedance of the switch such that the attenuation observed through the switch is negligible, and also minimized the channel-to-channel skew as well as channel-to-channel crosstalk, as required by the high-speed serial interface. CBTL02043A/B allows expansion of existing high speed ports for extremely low power. The device's pinouts are optimized to match different application layouts. CBTL02043A has input and output pins on the opposite of the package, and is suitable for edge connector(s) with different signal sources on the motherboard. CBTL02043B has outputs on both sides of the package, and the device can be placed between two connectors to multiplex differential signals from a controller. Please refer to Section 8 for layout examples. 2. Features and benefits 2 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer High-speed signal switching for PCIe Gen3 8 Gbit/s High bandwidth: 10 GHz at −3 dB Low insertion loss: −0.5 dB at 100 MHz −1.3 dB at 4.0 GHz Low return loss: −20 dB at 4 GHz Low crosstalk: −35 dB at 4 GHz Low off-state isolation: −20 dB at 4 GHz Low intra-pair skew: 5 ps typical Low inter-pair skew: 35 ps maximum VDD operating range: 3.3 V ± 10 % Shutdown pin (XSD) for power-saving mode Standby current less than 1 μA ESD tolerance: 2000 V HBM 1000 V CDM DHVQFN20 package NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 3. Applications Routing of high-speed differential signals with low signal attenuation PCIe Gen3 DisplayPort 1.2 USB 3.0 SATA 6 Gbit/s 4. Ordering information Table 1. Ordering information Package Name CBTL02043ABQ CBTL02043BBQ DHVQFN20 DHVQFN20 Description plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm[1] plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm[1] Version SOT764-1 SOT764-1 Type number [1] Total height after printed-circuit board mounting = 1.0 mm maximum. 5. Functional diagram A0_P A0_N A1_P A1_N B0_P B0_N B1_P B1_N C0_P C0_N C1_P C1_N SEL XSD 002aaf073 Fig 1. Functional diagram of CBTL02043A; CBTL02043B CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 2 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 6. Pinning information 6.1 Pinning CBTL02043A 20 GND VDD terminal 1 index area XSD A0_P A0_N GND VDD A1_P A1_N SEL 2 3 4 5 6 7 8 9 VDD 10 GND 11 terminal 1 index area 19 B0_P 18 B0_N 17 B1_P 16 B1_N 15 C0_P 14 C0_N 13 C1_P 12 C1_N A0_P A0_N C0_P C0_N A1_P A1_N C1_P C1_N 2 3 4 5 6 7 8 9 GND 10 VDD 11 CBTL02043B GND 1 20 VDD 19 XSD 18 B0_P 17 B0_N 16 VDD 15 GND 14 B1_P 13 B1_N 12 SEL 1 002aaf912 002aaf913 Transparent top view Transparent top view a. CBTL02043A Fig 2. Pin configuration for DHVQFN20 b. CBTL02043B 6.2 Pin description Table 2. Symbol A0_P A0_N A1_P A1_N B0_P B0_N B1_P B1_N C0_P C0_N C1_P C1_N SEL Pin description Pin CBTL02043A 3 4 7 8 19 18 17 16 15 14 13 12 9 CBTL02043B 2 3 6 7 18 17 14 13 4 5 8 9 12 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CMOS single-ended input channel 0, port A differential signal input/output channel 1, port A differential signal input/output channel 0, port B differential signal input/output channel 1, port B differential signal input/output channel 0, port C differential signal input/output channel 1, port C differential signal input/output operation mode select SEL = LOW: A ↔ B SEL = HIGH: A ↔ C Type Description CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 3 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 Pin description …continued Pin CBTL02043A CBTL02043B 19 CMOS single-ended input Shutdown pin; should be driven LOW or connected to VSS for normal operation. When HIGH, all paths are switched off (non-conducting high-impedance state), and supply current consumption is minimized. positive supply voltage, 3.3 V (± 10 %) supply ground 2 Type Description Table 2. Symbol XSD VDD GND[1] 1, 6, 10 5, 11, 20, center pad 11, 16, 20 1, 10, 15, center pad power power [1] DHVQFN20 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 7. Functional description Refer to Figure 1 “Functional diagram of CBTL02043A; CBTL02043B”. 7.1 Function selection and shutdown function The CBTL02043A/B provides a shutdown function to minimize power consumption when the application is not active, but power to the CBTL02043A/B is provided. The XSD pin (active HIGH) places all channels in high-impedance state (non-conducting) while reducing current consumption to near-zero. When XSD pin is LOW, the device operates normally. Table 3. Function selection X = Don’t care. XSD HIGH LOW LOW SEL X LOW HIGH Function An, Bn and Cn pins are high-Z An to Bn and vice versa An to Cn and vice versa CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 4 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 8. Application design-in information CBTL02043A eSATA CONTROLLER MINI CARD/ mSATA CONNECTOR PCIe CONTROLLER CBTL02043A eSATA CONTROLLER eSATA/USB 3.0 COMBO CONNECTOR USB 3.0 CONTROLLER 002aaf914 Fig 3. Applications using CBTL02043A USB 3.0 CONTROLLER CBTL02043B USB 3.0 CONNECTOR USB 3.0 CONNECTOR 002aaf915 Fig 4. Application using CBTL02043B CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 5 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 9. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tcase VESD Parameter supply voltage case temperature electrostatic discharge voltage HBM CDM [1] [2] [1] [2] Conditions Min −0.3 −40 - Max +4.6 +85 2000 1000 Unit V °C V V Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 10. Recommended operating conditions Table 5. Symbol VDD VI Tamb Recommended operating conditions Parameter supply voltage input voltage ambient temperature operating in free air Conditions Min 3.0 −40 Typ 3.3 Max 3.6 VDD +85 Unit V V °C 11. Static characteristics Table 6. Static characteristics VDD = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol IDD Parameter supply current Conditions operating mode; VDD = max.; XSD = LOW shutdown mode; VDD = max.; XSD = HIGH IIH IIL VIH VIL VI VIC VID [1] [2] Min 0.65VDD 0 Typ[1] 1.35 - Max 2.5 1 ±5[2] ±5[2] 0.35VDD 2.4 VDD 2 1.6 Unit mA μA μA μA V V V V V V HIGH-level input current LOW-level input current HIGH-level input voltage LOW-level input voltage input voltage common-mode input voltage differential input voltage VDD = max.; VI = VDD VDD = max.; VI = GND SEL, XSD pins SEL, XSD pins differential pins SEL, XSD pins peak-to-peak - Typical values are at VDD = 3.3 V, Tamb = 25 °C, and maximum loading. Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW. CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 6 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 12. Dynamic characteristics Table 7. Dynamic characteristics VDD = 3.3 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol DDIL Parameter differential insertion loss Conditions channel is OFF f = 4 GHz f = 100 MHz channel is ON f = 4 GHz f = 100 MHz DDNEXT differential near-end crosstalk adjacent channels are ON f = 4 GHz f = 100 MHz B−3dB DDRL Ron Cio(on) tPD −3 dB bandwidth differential return loss ON-state resistance on-state input/output capacitance propagation delay from Port A to Port B, or Port A to Port C, or vice versa supply voltage valid or XSD going LOW to channel specified operating conditions f = 4 GHz f = 100 MHz VDD = 3.3 V; VI = 2 V; II = 19 mA −35 −65 10 −20 −25 6 1.5 60 dB dB GHz dB dB Ω pF ps −1.3 −0.5 dB dB −20 −50 dB dB Min Typ[1] Max Unit Switching characteristics tstartup start-up time 10 ms tPZH tPZL tPHZ tPLZ tsk(dif) tsk [1] OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay differential skew time skew time intra-pair inter-pair - 5 - 300 70 50 50 35 ns ns ns ns ps ps Typical values are at VDD = 3.3 V; Tamb = 25 °C, and maximum loading. CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 7 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 VDD SEL 0.5VDD tPZL 0.5VDD 0V tPLZ 0.85VOH 0.25VOH tPZH 0.85VOH 0.25VOH tPHZ VOH VOL VOH VOL 002aag013 output 1 output 2 Output 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Output 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. The outputs are measured one at a time with one transition per measurement. Fig 5. Voltage waveforms for enable and disable times CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 8 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 13. Test information 2 × VIC open GND VDD PULSE GENERATOR VIC DUT RT CL 50 pF VO RL 200 Ω RL 200 Ω 002aag014 CL = load capacitance; includes jig and probe capacitance. RT = termination resistance; should be equal to Zo of the pulse generator. All input pulses are supplied by generators having the following characteristics: PRR ≤ 5 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns. Fig 6. Test circuitry for switching times PORT 1 4-PORT, 20 GHz NETWORK ANALYZER PORT 2 PORT 3 PORT 4 DUT 002aae655 Fig 7. Table 8. Test Test circuit Test data Load CL RL 200 Ω 200 Ω 200 Ω 2 × VIC GND open 50 pF 50 pF Switch tPLZ, tPZL (output on B side) tPHZ, tPZH (output on B side) tPD CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 9 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 14. Package outline DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 8. Package outline SOT764-1 (DHVQFN20) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. CBTL02043A_CBTL02043B Product data sheet Rev. 1 — 10 March 2011 10 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 11 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 9. CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 12 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 9. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 11. Acronym CDM DUT ESD HBM I/O PCI PCIe PRR SATA USB Abbreviations Description Charged-Device Model Device Under Test ElectroStatic Discharge Human Body Model Input/Output Peripheral Component Interconnect PCI Express Pulse Repetition Rate Serial Advanced Technology Attachment Universal Serial Bus 17. Revision history Table 12. Revision history Release date 20110310 Data sheet status Product data sheet Change notice Supersedes Document ID CBTL02043A_CBTL02043B v.1 CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 13 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2011. All rights reserved. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 1 — 10 March 2011 14 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBTL02043A_CBTL02043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 10 March 2011 15 of 16 NXP Semiconductors CBTL02043A; CBTL02043B 3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen3 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function selection and shutdown function . . . . 4 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering of SMD packages . . . . . . . . . . . . . . 11 Introduction to soldering . . . . . . . . . . . . . . . . . 11 Wave and reflow soldering . . . . . . . . . . . . . . . 11 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 11 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 March 2011 Document identifier: CBTL02043A_CBTL02043B