CBTL05023BS,118

CBTL05023 Multiplexer/demultiplexer switch for Thunderbolt applications Rev. 5 — 15 July 2013 Product data sheet 1. General description The CBTL05023 is a multiplexer/demultiplexer switch chip for DisplayPort v1.2 signals and the control signals of a 10 Gbit/s channel. The 10 Gbit/s channel does not pass through this switch. This chip provides BIASOUT output control signal, and the DC-biasing pull-down resistors to facilitate an external 10 Gbit/s channel. The AUX MUX is a 2 : 1 switch with CA_DETect pin selecting between AUX and DDC (Direct Display Control) signals. The DP MUX is a 2 : 1 switch that selects between DPML (DisplayPort Main Link) and LSTX/LSRX signals. This chip also includes three control signal buffers: HPDOUT, CA_DETOUT and BIASOUT. CBTL05023 is powered by a 3.3 V supply and it is available in 3 mm  3 mm HVQFN24 package with 0.4 mm pitch. 2. Features and benefits 2.1 AUX MUX 2 : 1 switch  This 2 : 1 switch is controlled by CA_DET signal multiplexing of the 1 Mbit/s differential AUX and DDC (Direct Display Control) signals  When CA_DET is HIGH, DDC path is selected  Differential AUX channel:  Low insertion loss: 0.5 dB at 5 MHz  Low return loss: 19 dB at 5 MHz  Low ON-state resistance: 7.5   Bandwidth: 5 GHz  Low off-state isolation: 75 dB at 5 MHz  Low crosstalk: 40 dB at 5 MHz  Common-mode input voltage VIC: 0 V to 3.3 V  Differential input voltage VID: 1.4 V (maximum)  DDC channel has DDC_CLK and DDC_DAT I2C signals  100 kHz 3.3 V voltage swing  Both AUXIO+ and AUXIO outputs have 900  (20 %) pull-down resistor that is enabled by the status of the BIASOUT output pin  These pull-down resistors provide DC bias for the 10 Gbit/s channel CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 2.2 DP MUX 2 : 1 switch The DP MUX is a 2:1 switch that is controlled by DP_PD pin multiplexing of a differential DPML signal and LSTX/LSRX signals  The DPML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s  The low speed DC coupled signals LSTX and LSRX are 3.3 V single-ended signals that operated at 1 Mbit/s  5.4 Gbit/s DPML channel:  Low insertion loss for DP-DPMLO path: 2.0 dB at 2.5 GHz  Low insertion loss for LS-DPMLO path: 2.0 dB at 2.5 GHz  Low return loss for DP-DPMLO path: 15 dB at 2.5 GHz  Low return loss for LS-DPMLO path: 14 dB at 2.5 GHz  Low ON-state resistance for DP-DPMLO path: 9   Low ON-state resistance for LS-DPMLO path: 13   High bandwidth: 7 GHz  Low off-state isolation: 20 dB at 2.5 GHz  Low crosstalk: 25 dB at 2.5 GHz  Common-mode input voltage VIC: 0 V to 3.3 V  Differential input voltage VID: 1.4 V (maximum) 2.3 General  The input of the HPDOUT (Hot Plug Detect output) buffer is 5 V tolerant  HPDOUT, CA_DETOUT and BIASOUT buffers  CA_DET input leakage current < 0.1 A to prevent driving the 1 M pull-down to a HIGH level  BIASOUT buffer is able to provide enough current to drive the bias circuit for the PIN diode path  BIASOUT buffer can drive up to six sets of bias circuits for the 10 Gbit/s paths  When AUXIO_EN is LOW or (BIASIN = 0 and DP_PD = 1), this chip is in Sleep mode  AUXIO+ and AUXIO of AUX MUX are disabled  CA_DETOUT and HPDOUT buffers are on  When the chip is in Sleep mode, CBTL05023 consumes < 3.5 mW  Patent-pending high-bandwidth analog pass-gate technology  Very low intra-pair differential skew (5 ps typical)  All channels have back current protection  All channels support rail-to-rail input voltage  CMOS input buffer with hysteresis  Single 3.3 V  10 % power supply  HVQFN24 3 mm  3 mm package, 0.4 mm pitch, with exposed center pad for thermal relief and electrical ground  ESD: 2500 V HBM, 1250 V CDM  Operating temperature range: 0 C to 85 C CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 3. Ordering information Table 1. Ordering information Type number CBTL05023BS [1] Topside marking Package Name Description Version 023 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3  3  0.85 mm[1] SOT905-1 Maximum package height is 1 mm. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature CBTL05023BS CBTL05023BS,118 HVQFN24 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 0 C to +85 C 4. Block diagram BIASOUT CONTROL LOGIC AUX− E AUX+ DDC_DAT AUX MUX 2:1 DDC_CLK S BIASIN AUXIO_EN AUXIO− 900 Ω AUXIO+ 900 Ω CA_DET CA_DETOUT HPD HPDOUT DP+ DP− 3.3 V DPMLO+ DP MUX 2:1 DPMLO− LSTX LSRX S DP_PD 002aag229 Fig 1. CBTL05023 Product data sheet Block diagram of CBTL05023 All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 5. Pinning information CA_DET 18 19 DPMLO+ 20 DPMLO− 21 GND 22 AUXIO+ 23 AUXIO− terminal 1 index area 24 BIASOUT 5.1 Pinning 17 HPD BIASIN 1 AUXIO_EN 2 16 CA_DETOUT CBTL05023BS VDD 3 15 VDD Transparent top view 12 HPDOUT DP+ 11 DP− 10 DP_PD GND 9 13 LSRX AUX+ 8 DDC_CLK 5 AUX− 7 14 LSTX 6 DDC_DAT 4 002aag230 Center pad is connected to printed-circuit board ground plane for electrical grounding and thermal relief. Refer to Section 10 and Section 11 for package-related information. Fig 2. Pin configuration for HVQFN24 5.2 Pin description Table 3. Pin description Symbol Pin Type Description AUX differential signals. The input to this pin must be AC-coupled externally. Data path signals AUX 7 differential I/O AUX+ 8 differential I/O AUXIO 23 differential I/O AUXIO+ 22 differential I/O Differential pairs that are DC-coupled to 3.3 V and ground. These two pins are internally connected to 1 k pull-down resistors that are enabled by the status of BIASOUT output pin (see Table 18 for details). CBTL05023 Product data sheet DDC_CLK 5 single-ended I/O Pair of single-ended terminals for DDC clock and data signals. DDC_DAT 4 single-ended I/O DP 10 differential I/O DP+ 11 differential I/O DPMLO 20 differential I/O DPMLO+ 19 differential I/O Differential pair that is DC-coupled to 3.3 V and ground. LSRX 13 single-ended I/O Single-ended signal with DC coupled to 3.3 V. LSTX 14 single-ended I/O Single-ended signal with DC coupled to ground. High speed differential pair. The input to this pin must be AC-coupled externally. All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 4 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications Table 3. Pin description …continued Symbol Pin Type Description HPDOUT 12 CMOS output 3.3 V CMOS output buffer for HPD. HPD 17 CMOS input CMOS input with 5 V tolerance. CA_DET 18 CMOS input When CA_SET is HIGH, the DDC_CLK and DDC_DAT replace AUX differential pair. CA_DETOUT 16 CMOS output 3.3 V CMOS output buffer for CA_DET. BIASIN 1 CMOS input CMOS input buffer. BIASOUT 24 CMOS output This output enables the 1 k pull-down resistors for both AUXIO+ and AUXIO. It enables the DC bias of the 10 Gbit/s data path. It provides power through six sets of 3.2 k bias circuits for 10 Gbit/s paths. AUXIO_EN 2 CMOS input If AUXIO_EN is LOW, then AUXIO+ and AUXIO are in high-impedance state for Sleep mode. DP_PD 6 CMOS input If DP_PD is LOW, then DPMLO+ and DPMLO are connected to DP+ and DP. If DP_PD is HIGH, then DPMLO+ and DPMLO are connected to LSTX and LSRX. This multiplexer must work during initial power-up that might have VDD = 2.3 V. power 3.3 V supply. Both pin 3 and pin 15 must be connected to system power supply. Control signals 3.3 V supply option 3, 15 VDD Ground connections GND 9, 21[1] ground 0 V (ground). GND center pad ground The center pad must be connected to GND plane for both electrical grounding and thermal relief. [1] CBTL05023 Product data sheet HVQFN24 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 5 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 6. Functional description Refer to Figure 1 “Block diagram of CBTL05023”. The following sections describe the individual block functions and capabilities of the device in more detail. 6.1 Buffer function tables Table 4. BIASOUT buffer X = don’t care. AUXIO_EN BIASIN BIASOUT 0 X 0 1 0 0 1 1 1 Table 5. HPD buffer HPD input HPDOUT output 0 0 1 1 Table 6. CA_DET buffer CA_DET input CA_DETOUT output 0 0 1 1 6.2 AUX MUX state and function tables The 2 : 1 AUXIO+ and AUXIO are controlled by three signals: AUXIO_EN, CA_DET and BIASIN. Table 7. AUX MUX state X = don’t care. AUXIO_EN input Product data sheet DP_PD input AUX MUX State 0 X X 3-state sleep 1 0 0 ON DP/DP++ 1 0 1 3-state sleep 1 1 0 3-state illegal 1 1 1 3-state 10 Gbit/s mode Table 8. CBTL05023 BIASIN input AUX MUX function CA_DET input AUXIO 0 AUX 1 DDC All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 6.3 Operation modes of both DPML MUX and AUX MUX Table 9. DPML MUX function DP_PD input DPMLO outputs 0 DP+ and DP 1 LSRX and LSTX Table 10. Operation modes X = don’t care. AUXIO_EN BIASIN DP_PD CA_DET BIASOUT AUXIO DPMLO State 0 X 0 X 0 3-state DP input sleep 0 X 1 X 0 3-state LS sleep 1 0 0 0 0 AUX input DP input DP mode 1 0 0 1 0 DDC DP input DP++ mode 1 0 1 X 0 3-state LS detect 1 1 0 X 1 1 k pull-down DP input illegal 1 1 1 X 1 1 k pull-down LS 10 Gbit/s mode CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit supply voltage [1] 0.3 +4.6 V VI input voltage [1] 0.3 +5.5 V Tstg storage temperature 65 +150 C VESD electrostatic discharge voltage VDD Parameter Conditions HBM [2] - 2500 V CDM [3] - 1250 V [1] All voltage values, except differential voltages, are with respect to network ground terminal. [2] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. [3] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 8. Recommended operating conditions Table 12. Operating conditions Over operating free-air temperature range, unless specified otherwise. Symbol Parameter Conditions VDD supply voltage 3.3 V supply option initial supply voltage before power supply negotiation done VI input voltage Tamb ambient temperature operating in free air CMOS inputs MUX I/O pins [1] CBTL05023 Product data sheet [1] Min Typ Max Unit 3.0 3.3 3.6 V 2.3 - - V 0.3 - VDD + 0.3 V 0.3 - VDD + 0.3 V 0 - 85 C During power supply negotiation only a limited supply voltage is available. The control logic and multiplexers must be in full function with degraded performance. The channel between LSTX/LSRX and DPMLO+/DPMLO must work. The initial Ron of DP MUX in Table 15 should be < 50 . All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 8 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 9. Characteristics 9.1 Device general characteristics Table 13. General characteristics Symbol Parameter Conditions Min Typ Max Unit IDD supply current VDD = 3.6 V with no load on BIASOUT - - 2.8 mA Pcons power consumption VDD = 3.6 V with no load on BIASOUT - - 10 mW Sleep mode; AUXIO_EN = 0 or (BIASIN = 0 and DP_PD = 1) - - 3.5 mW - - 10 ms - 2 4 s tstartup start-up time supply voltage valid to channel specified operating characteristics trcfg reconfiguration time DP_PD, AUXIO_EN, BIASIN or CA_DET state change to channel specified operating characteristics [1] [1] Outputs are undefined during reconfiguration, including enable and disable time of the multiplexers. 9.2 AUX/DDC channel characteristics Table 14. AUX/DDC channel characteristics Symbol Parameter DDIL differential insertion loss Conditions Min Typ Max Unit channel is OFF; f = 5 MHz - 75 - dB channel is ON; f = 5 MHz - 0.5 - dB DDRL differential return loss f = 5 MHz - 19 - dB DDNEXT differential near-end crosstalk adjacent channels are ON; f = 5 MHz - 40 - dB Ron ON-state resistance VDD = 3.3 V; VI = 3.3 V; II = 20 mA - 7.5 -  B3dB 3 dB bandwidth - 5 - GHz tPD propagation delay from DDC to AUXIO - 70 - ps from AUX to AUXIO - 70 - ps tsk(dif) differential skew time intra-pair - 5 - ps VI input voltage AUX+/AUX and AUXIO+/AUXIO 0 - VDD V VIC common-mode input voltage AUX+/AUX and AUXIO+/AUXIO 0 - VDD V VID differential input voltage AUX+/AUX and AUXIO+/AUXIO; peak-to-peak value - - 1.4 V ILIH HIGH-level input leakage current VDD = max.; VI = VDD - - 0.5 A ILIL LOW-level input leakage current VDD = max.; VI = GND - - 0.5 A CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 9.3 DisplayPort Main Link (DPML) channel characteristics Table 15. DPML channel characteristics Symbol Parameter Conditions Min Typ Max Unit DDIL differential insertion loss DP-DPMLO path; channel is OFF f = 2.5 GHz - 20 - dB f = 1.35 GHz - 26 - dB f = 2.5 GHz - 2.0 - dB f = 1.35 GHz - 1.0 - dB f = 100 MHz - 0.5 - dB f = 2.5 GHz - 20 - dB f = 1.35 GHz - 26 - dB f = 2.5 GHz - 2.0 - dB f = 1.35 GHz - 1.5 - dB f = 100 MHz - 1.5 - dB f = 2.5 GHz - 15 - dB f = 100 MHz - 24 - dB f = 2.5 GHz - 14 - dB f = 100 MHz - 18 - dB f = 2.5 GHz - 25 - dB f = 100 MHz - 60 - dB DP-DPMLO path - 9 -  LS-DPMLO path - 13 -  - - 50  - 7.0 - GHz DP-DPMLO path; channel is ON LS-DPMLO path; channel is OFF LS-DPMLO path; channel is ON DDRL differential return loss DP-DPMLO path LS-DPMLO path DDNEXT Ron differential near-end crosstalk adjacent channels are ON ON-state resistance VDD = 3.3 V; VI = 3.3 V; II = 10 mA initial ON-state resistance before power supply negotiation done; VDD = 2.3 V; VI = 2.3 V; II = 10 mA B3dB 3 dB bandwidth tPD propagation delay from DP+/DP to DPMLO+/DPMLO - 100 - ps tsk(dif) differential skew time intra-pair - 5 - ps VI input voltage LSTX/LSRX to DPMLO+/DPMLO channel 0.3 - VDD + 0.6 V VIC common-mode input voltage DP+/DP and DPMLO+/DPMLO 0 - VDD V VID differential input voltage DP+/DP and DPMLO+/DPMLO channel; peak-to-peak value - - 1.4 V ILIH HIGH-level input leakage current VDD = max.; VI = VDD - - 0.5 A ILIL LOW-level input leakage current VDD = max.; VI = GND - - 0.5 A CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 10 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 9.4 Control signals characteristics Table 16. CA_DET input buffer characteristics Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage input leakage current ILI [1] Conditions measured with input at VIH(max) and VIL(min) [1] Min Typ Max Unit 0.7  VDD - - V - - 0.3  VDD V - - 0.1 A The leakage current on CA_DET pin must not drive the 1 M pull-down to a HIGH level. Table 17. HPD, BIASIN, DP_PD, AUXIO_EN input buffer characteristics Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage CMOS inputs 0.7  VDD - - V VIL LOW-level input voltage CMOS inputs - - 0.3  VDD V ILI input leakage current measured with input at VIH(max) and VIL(min) - - 1 A Table 18. BIASOUT output buffer characteristics This buffer provides the power supply current for the PIN diode bias path and it drives six sets of bias resistors for the 10 Gbit/s signal paths. Symbol Parameter Conditions Min Typ Max Unit Ipd pull-down current VO = 0.4 V 5 - - mA Ipu pull-up current VO = VDD  0.4 V - - 9 mA tPD propagation delay - 40 60 ns Table 19. CA_DETOUT, HPDOUT output buffer characteristics Symbol Parameter Conditions Min Typ Max Unit Ipd pull-down current VO = 0.4 V 2 - - mA Ipu pull-up current VO = VDD  0.4 V tPD propagation delay Table 20. Symbol [1] - 2 mA 70 100 ns AUXIO+ and AUXIO- pins in 10 Gbit/s mode (AUXIO_EN = BIASIN = DP_PD = 1) characteristics Parameter LOW-level output voltage VOL - Conditions IO = 1 mA [1] Min Typ Max Unit 0.72 0.90 1.1 V This VOL is contributed from the 900  pull-down resistors on these two pins. CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 10. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3 x 3 x 0.85 mm B D SOT905-1 A terminal 1 index area A E A1 c detail X C e1 e 6 b1 v w b 7 11 M y y1 C C A B C M 12 L 13 5 e b1 e2 Eh 17 1 LC terminal 1 index area 24 23 19 18 Dh X L1 LC 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 b b1 c D (1) Dh E (1) Eh e e1 e2 L L1 LC v w y y1 mm 1 0.05 0.00 0.25 0.15 0.45 0.35 0.2 3.1 2.9 2.05 1.75 3.1 2.9 2.05 1.75 0.4 1.8 1.8 0.35 0.15 0.1 0.0 0.3 0.2 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included Fig 3. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT905-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 06-03-13 06-03-31 Package outline SOT905-1 (HVQFN24) CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 11. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 11.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 11.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 11.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 11.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 4) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 21 and 22 Table 21. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 22. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 4. CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 4. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 12. Abbreviations Table 23. CBTL05023 Product data sheet Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DDC Direct Display Control DP DisplayPort DPML DisplayPort Main Link ESD ElectroStatic Discharge HBM Human Body Model HBR2 High Bit Rate 2 ML Main Link MUX Multiplexer PIN P-type, Intrinsic, N-type All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 13. Revision history Table 24. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTL05023 v.5 20130715 Product data sheet - CBTL05023 v.4 Modifications: CBTL05023 v.4 Modifications: • • • • Section 2.3 “General”, first bullet item: corrected term from “Hug Plug Detect” to “Hot Plug Detect” Table 1 “Ordering information”: added column “Topside marking” Added Section 3.1 “Ordering options” De-activated hyper links in previous revision history 20121031 Product data sheet - CBTL05023 v.3 • Descriptive title of data sheet changed from “Multiplexer/demultiplexer switch chip” to “Multiplexer/demultiplexer switch for Thunderbolt applications” • Table 13 “AUX/DDC channel characteristics”: – ILIH Max value changed from “5 A” to “0.5 A” – ILIL Max value changed from “5 A” to “0.5 A” • Table 14 “DPML channel characteristics”: – ILIH Max value changed from “5 A” to “0.5 A” – ILIL Max value changed from “5 A” to “0.5 A” • Table 16 “HPD, BIASIN, DP_PD, AUXIO_EN input buffer characteristics”: – ILI Max value changed from “10 A” to “1 A” CBTL05023 v.3 Modifications: CBTL05023 v.2 Modifications: 20120621 • - CBTL05023 v.2 Table 2 “Pin description”, last row: “Type” for Pin “center pad” corrected from “power” to “ground” 20120515 • • • Product data sheet Product data sheet - CBTL05023 v.1 Section 2.2 “DP MUX 2 : 1 switch”, third bullet, ninth sub-bullet: changed from “50 dB” to “25 dB” Section 2.3 “General”, fourth bullet: inserted “Patent-pending” Table 14 “DPML channel characteristics”, DDNEXT characteristic: – Typ value for condition f = 2.5 GHz changed from “50 dB” to “25 dB” – Typ value for condition f = 100 MHz changed from “65 dB” to “60 dB” CBTL05023 v.1 CBTL05023 Product data sheet 20111104 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 - © NXP B.V. 2013. All rights reserved. 16 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. CBTL05023 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 17 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBTL05023 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 July 2013 © NXP B.V. 2013. All rights reserved. 18 of 19 CBTL05023 NXP Semiconductors Multiplexer/demultiplexer switch for Thunderbolt applications 16. Contents 1 2 2.1 2.2 2.3 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 7 8 9 9.1 9.2 9.3 9.4 10 11 11.1 11.2 11.3 11.4 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 AUX MUX 2 : 1 switch . . . . . . . . . . . . . . . . . . . 1 DP MUX 2 : 1 switch. . . . . . . . . . . . . . . . . . . . . 2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Buffer function tables . . . . . . . . . . . . . . . . . . . . 6 AUX MUX state and function tables . . . . . . . . . 6 Operation modes of both DPML MUX and AUX MUX . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device general characteristics . . . . . . . . . . . . . 9 AUX/DDC channel characteristics . . . . . . . . . . 9 DisplayPort Main Link (DPML) channel characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 10 Control signals characteristics . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering of SMD packages . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 July 2013 Document identifier: CBTL05023