CBTL06DP213
Third generation high-performance DisplayPort multiplexer
Rev. 4 — 23 March 2017
Product data sheet
1. General description
CBTL06DP213 is an NXP third generation high-performance multi-channel multiplexer,
meant for DisplayPort (DP) v1.3 or Embedded DisplayPort applications operating at data
rate of 1.62 Gbit/s, 2.7 Gbit/s, 5.4 Gbit/s or 8.1 Gbit/s. It is designed using NXP proprietary
high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1
multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable
of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and
Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated
AUX and DDC I/Os, CBTL06DP213 provides an additional level of multiplexing of AUX
and DDC signals delivering true flexibility and choice.
A typical application of CBTL06DP213 is on motherboards where one of two GPU
DisplayPort sources needs to be selected to connect to a DisplayPort sink device or
connector. A controller chip selects which path to use by setting a select signal HIGH or
LOW. Due to the bidirectional nature of the signal paths, CBTL06DP213 can also be used
in the reverse topology, for example, to connect one display source device to one of two
display sink devices or connectors.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.3 - 8.1 Gbit/s) signals
4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
main link signals
1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
1 channel with 2 : 1 multiplexing/switching for HPD signal
High-bandwidth analog pass-gate technology
Ron on DP high-speed channels: 14
Low insertion loss:
0.9 dB at 100 MHz
1.3 dB at 2.7 GHz
1.7 dB at 4 GHz
3 dB at 11.1 GHz
Low crosstalk: 35 dB at 2.7 GHz
Low off-state isolation: 30 dB at 2.7 GHz, 25 dB at 4 GHz
Low return loss:
20.3 dB at 100 MHz
16.7 dB at 1.35 GHz
12.9 dB at 2.7 GHz
12 dB at 4 GHz
CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
Very low intra-pair skew (5 ps typical)
Very low inter-pair skew (< 80 ps)
Switch/multiplexer position select CMOS input
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor
Supports HDMI/DVI incorrect dongle connection
Single 3.3 V power supply
Operation current of 2 mA typical,
ESD 2 kV HBM, 500 V CDM
Available in 5 mm 5 mm, 0.5 mm ball pitch TFBGA48 package
3. Applications
Motherboard applications requiring DisplayPort and PCI Express
switching/multiplexing
Docking stations
Notebook computers
Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board
connectors
4. Ordering information
Table 1.
Ordering information
Type number
CBTL06DP213EE
[1]
Topside
mark
Solder process
Package
6D213
Pb-free (SnAgCu TFBGA48
solder compound)
Name
Description
Version
plastic thin fine-pitch ball grid array package; SOT918-1
48 balls; body 5 5 0.8 mm[1]
Total height including solder balls after printed circuit board mounting = 1.15 mm maximum.
For more information on product marking, refer to
www.nxp.com/products/related/package-markings.html.
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable part number Package
Packing method
Minimum
order
quantity
Temperature
CBTL06DP213EE
CBTL06DP213EE,118
Reel 13” Q1/T1
*standard mark SMD
3000
Tamb = 40 C to +105 C
CBTL06DP213
Product data sheet
TFBGA48
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Rev. 4 — 23 March 2017
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
5. Functional diagram
VDD
CBTL06DP213
IN1_n+
IN1_n−
IN2_n+
IN2_n−
4
0
4
1
AUX1+
AUX1−
00
AUX2+
AUX2−
10
DDC_CLK1
DDC_DAT1
01
DDC_CLK2
DDC_DAT2
11
HPD_1
OUT_n+
OUT_n−
4
AUX+ or SCL
AUX− or SDA
AUX+
AUX−
0
HPDIN
HPD_2
1
GPU_SEL
DDC_AUX_SEL
TST0
GND
Fig 1.
CBTL06DP213
Product data sheet
002aag784
Functional diagram
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
6. Pinning information
6.1 Pinning
ball A1
index area
CBTL06DP213EE
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
002aag785
Transparent top view
Fig 2.
Pin configuration for TFBGA48
1
2
A
GPU_SEL
VDD
B
OUT_0−
OUT_0+
C
3
GND
4
5
6
IN1_0−
IN1_1−
IN1_2−
IN1_0+
IN1_1+
IN1_2+
7
TST0
8
9
IN1_3+
IN1_3−
IN2_0+
IN2_0−
DDC_AUX
_SEL
GND
D
OUT_1−
OUT_1+
IN2_1+
IN2_1−
E
OUT_2−
OUT_2+
IN2_2+
IN2_2−
F
OUT_3−
OUT_3+
IN2_3+
IN2_3−
GND
GND
G
H
AUX−
AUX+
J
HPDIN
HPD_1
HPD_2
GND
DDC_CLK2
AUX2+
VDD
DDC_DAT2
AUX2−
GND
DDC_CLK1
AUX1+
DDC_DAT1
AUX1−
002aag786
Transparent top view
Fig 3.
CBTL06DP213
Product data sheet
Ball mapping
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
6.2 Pin description
Table 3.
Pin description
Symbol
Ball
Type
Description
GPU_SEL
A1
3.3 V CMOS
single-ended input
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
DDC_AUX_SEL
C2
3.3 V CMOS
single-ended input
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX I/Os are connected to their
respective DDCOUT terminals.
TST0
B7
3.3 V CMOS
single-ended input
Test pin for NXP use only. Should be tied to VDD in the application
use cases.
IN1_0+
B4
differential I/O
IN1_0
A4
differential I/O
Four high-speed differential pairs for DisplayPort signals, path 1,
left-side.
IN1_1+
B5
differential I/O
IN1_1
A5
differential I/O
IN1_2+
B6
differential I/O
IN1_2
A6
differential I/O
IN1_3+
A8
differential I/O
IN1_3
A9
differential I/O
IN2_0+
B8
differential I/O
IN2_0
B9
differential I/O
IN2_1+
D8
differential I/O
IN2_1
D9
differential I/O
IN2_2+
E8
differential I/O
IN2_2
E9
differential I/O
IN2_3+
F8
differential I/O
IN2_3
F9
differential I/O
OUT_0+
B2
differential I/O
OUT_0
B1
differential I/O
OUT_1+
D2
differential I/O
OUT_1
D1
differential I/O
OUT_2+
E2
differential I/O
OUT_2
E1
differential I/O
OUT_3+
F2
differential I/O
OUT_3
F1
differential I/O
AUX1+
H9
differential I/O
AUX1
J9
differential I/O
AUX2+
H6
differential I/O
AUX2
J6
differential I/O
DDC_CLK1
H8
differential I/O
DDC_DAT1
J8
differential I/O
CBTL06DP213
Product data sheet
Four high-speed differential pairs for DisplayPort signals, path 2,
left-side.
Four high-speed differential pairs for DisplayPort signals,
right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
Pair of single-ended terminals for DDC clock and data signals,
path 1, left-side.
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
Table 3.
Pin description …continued
Symbol
Ball
Type
Description
DDC_CLK2
H5
differential I/O
DDC_DAT2
J5
differential I/O
Pair of single-ended terminals for DDC clock and data signals,
path 2, left-side.
AUX+
H2
differential I/O
AUX
H1
differential I/O
High-speed differential pair for AUX or single-ended DDC signals,
right-side.
HPD_1
J2
single-ended I/O
Single ended channel for the HPD signal, path 1, left-side.
HPD_2
H3
single-ended I/O
Single ended channel for the HPD signal, path 2, left-side.
HPDIN
J1
single-ended I/O
Single ended channel for the HPD signal, right-side.
VDD
A2, J4
power supply
3.3 V power supply.
GND
B3, C8, ground
G2, G8,
H4, H7
Ground.
7. Functional description
Refer to Figure 1 “Functional diagram”.
The CBTL06DP213 uses a 3.3 V power supply. All main signal paths are implemented
using high-bandwidth pass-gate technology and are bidirectional. No clock or reset signal
is needed for the multiplexer to function.
The switch position for the main channels is selected using the select signal GPU_SEL.
Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the
DDC / AUX channel. The detailed operation is described in Section 7.1.
7.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
DDC_AUX_SEL as described below.
Table 4.
GPU_SEL
IN1_n
IN2_n
0
active; connected to OUT_n
high-impedance
1
high-impedance
active; connected to OUT_n
Table 5.
CBTL06DP213
Product data sheet
Multiplexer/switch select control for INn and OUTn channels
Multiplexer/switch select control for HPD channel
GPU_SEL
HPD_1
HPD_2
0
active; connected to HPDIN
high-impedance
1
high-impedance
active; connected to HPDIN
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
Table 6.
Multiplexer/switch select control for DDC and AUX channels
DDC_AUX_SEL
GPU_SEL
AUX1
AUX2
DDC_CLK1,
DDC_DAT1
DDC_CLK2,
DDC_DAT2
0
0
active;
connected to AUX
high-impedance
high-impedance
high-impedance
0
1
high-impedance
active;
connected to AUX
high-impedance
high-impedance
1
0
high-impedance
high-impedance
active;
connected to AUX
high-impedance
1
1
high-impedance
high-impedance
high-impedance
active;
connected to AUX
8. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Tcase
case temperature
VESD
Conditions
electrostatic discharge HBM
voltage
CDM
Min
Max
Unit
0.3
+5
V
40
+105
C
[1]
-
2000
V
[2]
-
500
V
[1]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2]
Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 8.
Symbol
Parameter
VDD
supply voltage
VI
input voltage
Tamb
CBTL06DP213
Product data sheet
Recommended operating conditions
Conditions
CMOS inputs
ambient temperature
HPD inputs
[1]
DDC/AUX inputs
[2]
Min
Typ
Max
Unit
3.0
3.3
3.6
V
0.3
-
VDD + 0.3
V
0.3
-
VDD + 0.3
V
0.3
-
VDD + 0.3
V
other inputs
0.3
-
+2.6
V
operating in free air
40
-
+105
C
[1]
HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is
placed in series.
[2]
DDC/AUX inputs are tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and
the pin is placed in series.
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
10. Characteristics
10.1 General characteristics
Table 9.
General characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
operating mode
-
2
3
mA
Pcons
power consumption
operating mode
-
-
10
mW
tstartup
start-up time
supply voltage valid to channel specified
operating characteristics
-
-
5
ms
trcfg
reconfiguration time
GPU_SEL or DDC_AUX_SEL state change
to channel specified operating characteristics
-
-
1
s
10.2 DisplayPort channel characteristics
Table 10.
DisplayPort channel characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VI
input voltage
0.3
-
+2.6
V
VIC
common-mode input voltage
0
-
2.0
V
VID
differential input voltage
peak-to-peak
-
-
+1.2
V
Ron
ON-state resistance
VDD = 3.3 V; VI = 2 V; II = 20 mA
-
14
-
DDIL
differential insertion loss
channel is ON; f 100 MHz
-
0.9
-
dB
channel is ON; f = 2.7 GHz
-
1.3
-
dB
channel is ON; f = 4 GHz
-
1.7
-
dB
channel is OFF; f = 2.7 GHz
-
30
-
dB
channel is OFF; f = 4 GHz
-
25
-
dB
f = 100 MHz
-
20.3
-
dB
f = 1.35 GHz
-
16.7
-
dB
f = 2.7 GHz
-
12.9
-
dB
f = 4 GHz
-
12.0
-
dB
f = 100 MHz
-
65
-
dB
f = 2.7 GHz
-
35
-
dB
f = 4 GHz
-
23
-
dB
DDRL
differential return loss
DDNEXT differential near-end crosstalk
Conditions
adjacent channels are ON
B
bandwidth
3.0 dB intercept
-
11.1
-
GHz
tPD
propagation delay
from left-side port to right-side port
or vice versa
-
80
-
ps
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
tsk
skew time
inter-pair
-
-
80
ps
CBTL06DP213
Product data sheet
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Third generation high-performance DisplayPort multiplexer
10.3 AUX and DDC ports
Table 11.
AUX and DDC port characteristics
Symbol
Parameter
VI
input voltage
VO
output voltage
VIC
VID
tPD
[1]
Conditions
Min
Typ
Max
Unit
0.3
-
VDD + 0.3
V
no load
-
VI
VDD + 0.3
V
common-mode input voltage
AUX
0
-
2.0
V
differential input voltage
AUX
-
-
+1.4
V
propagation delay
from left-side port to right-side
port or vice versa
-
80
-
ps
Max
Unit
[1]
Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.
10.4 HPDIN input, HPD_x outputs
Table 12.
HPD input and output characteristics
Symbol
Parameter
VI
input voltage
VO
output voltage
propagation delay
tPD
[1]
Conditions
Min
0.3
-
VDD + 0.3
V
no load
-
VI
VDD + 0.3
V
-
80
-
ps
from HPDIN to HPD_x or vice versa
[1]
Typ
Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.
10.5 GPU_SEL and DDC_AUX_SEL inputs
Table 13.
GPU_SEL and DDC_AUX_SEL input characteristics
Symbol
Parameter
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
ILI
input leakage current
CBTL06DP213
Product data sheet
Conditions
VDD = 3.6 V; 0.3 V VI 3.9 V
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Rev. 4 — 23 March 2017
Min
Typ
Max
Unit
2.0
-
-
V
-
-
0.8
V
-
-
10
A
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
11. Package outline
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm
B
D
SOT918-1
A
ball A1
index area
E
A2
A
A1
detail X
e1
∅v
∅w
b
e
M
M
C
C A B
C
y1 C
y
J
H
G
F
E
e2
e
D
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
9
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.15
0.25
0.15
0.90
0.75
0.35
0.25
5.1
4.9
5.1
4.9
0.5
4
4
0.15
0.05
0.08
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT918-1
---
MO-195
---
Fig 4.
EUROPEAN
PROJECTION
ISSUE DATE
05-09-21
05-10-13
Package outline TFBGA48 (SOT918-1)
CBTL06DP213
Product data sheet
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTL06DP213
Product data sheet
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CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
12.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 15.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 5.
CBTL06DP213
Product data sheet
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Rev. 4 — 23 March 2017
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CBTL06DP213
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Third generation high-performance DisplayPort multiplexer
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
13. Abbreviations
Table 16.
CBTL06DP213
Product data sheet
Abbreviations
Acronym
Description
AUX
Auxiliary channel (in DisplayPort definition)
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
DP
DisplayPort
DVI
Digital Video Interface
ESD
ElectroStatic Discharge
GPU
Graphics Processor Unit
HBM
Human Body Model
HDMI
High-Definition Multimedia Interface
I/O
Input/Output
PCI
Peripheral Component Interconnect
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Rev. 4 — 23 March 2017
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CBTL06DP213
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Third generation high-performance DisplayPort multiplexer
14. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTL06DP213 v.4
20170323
Product data sheet
-
CBTL06DP213 v.3.1
Modifications:
CBTL06DP213 v.3.1
Modifications:
•
•
Updated to DP v1.3
Table 10 “DisplayPort channel characteristics”: Added f = 4 GHz char data for DDIL, DDRL,
and DDNEXT
20150316
•
•
Product data sheet
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CBTL06DP213 v.3
Figure 1 “Functional diagram”: pin name changed from “XSD” to “TST0”
Figure 3 “Ball mapping”: pin (ball) B7 changed from “XSD” to “TST0”
CBTL06DP213 v.3
20150108
Product data sheet
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CBTL06DP213 v.2
CBTL06DP213 v.2
20120619
Product data sheet
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CBTL06DP213 v.1
CBTL06DP213 v.1
20120213
Product data sheet
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CBTL06DP213
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 23 March 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
14 of 17
CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
CBTL06DP213
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 23 March 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
15 of 17
CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Licenses
Purchase of NXP ICs with HDMI technology
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
15.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTL06DP213
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 23 March 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
16 of 17
CBTL06DP213
NXP Semiconductors
Third generation high-performance DisplayPort multiplexer
17. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
8
9
10
10.1
10.2
10.3
10.4
10.5
11
12
12.1
12.2
12.3
12.4
13
14
15
15.1
15.2
15.3
15.4
15.5
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Multiplexer/switch select functions . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General characteristics . . . . . . . . . . . . . . . . . . . 8
DisplayPort channel characteristics . . . . . . . . . 8
AUX and DDC ports . . . . . . . . . . . . . . . . . . . . . 9
HPDIN input, HPD_x outputs . . . . . . . . . . . . . . 9
GPU_SEL and DDC_AUX_SEL inputs. . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Soldering of SMD packages . . . . . . . . . . . . . . 11
Introduction to soldering . . . . . . . . . . . . . . . . . 11
Wave and reflow soldering . . . . . . . . . . . . . . . 11
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 11
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 March 2017
Document identifier: CBTL06DP213
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