CBTL05024
High performance multiplexer/demultiplexer switch for
Thunderbolt applications
Rev. 4 — 27 March 2014
Product data sheet
1. General description
The CBTL05024 is a multiplexer/demultiplexer switch chip optimized to interface the
Thunderbolt/MiniDP connector with Thunderbolt systems. It supports 10.3125 Gbit/s
Thunderbolt or DisplayPort v1.2 channels.
The TB MUX is a 3 : 1 switch that selects between Thunderbolt data path and
DisplayPort v1.2 side-band signals — either DDC or AUX.
The DP MUX is a 2 : 1 switch that selects between DP ML (DisplayPort Main Link) and
LS TX/RX signals. Both LSTX and LSRX are the side-band signals for Thunderbolt
channel.
This chip also includes HPD and CA_DET buffers for HPD_IN and CA_DET control
signals.
CBTL05024 is powered by a 3.3 V supply and it is available in a 3 mm 3 mm HVQFN24
package with 0.4 mm pitch.
2. Features and benefits
2.1 TB MUX 3 : 1 switch
This 3 : 1 switch is implemented by two cascaded 2 : 1 switches
The first 2 : 1 10G MUX is controlled by TB_ENA, AUXIO_EN and DP_PD pins
The second 2 : 1 AUX MUX is controlled by CA_DET signal multiplexing of the
720 Mbit/s Differential FAUX (or 1 Mbit/s AUX) and DDC (Direct Display Control)
signals
When CA_DET is HIGH, DDC path is selected
Differential TB channel
Low insertion loss: 1.3 dB at 5 GHz
Low return loss: < 20 dB at 5 GHz
Low ON-state resistance: 8
Bandwidth: 10 GHz
Low off-state isolation: 20 dB at 5 GHz
Low crosstalk: 36 dB at 5 GHz
Differential input voltage VID: 1.2 V (maximum)
Differential AUX channel
Low insertion loss: 1.1 dB at 5 MHz; 1.8 dB at 360 MHz
Low return loss: 18 dB at 5 MHz; 16 dB at 360 MHz
CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
Low ON-state resistance: 13 (typical); 16 (maximum)
Bandwidth: 3 GHz
Low off-state isolation: 80 dB at 5 MHz; 55 dB at 360 MHz
Low crosstalk: 26 dB at 2.7 GHz
Common-mode input voltage VIC: 0 V to 3.3 V
Differential input voltage VID: 1.4 V (maximum)
DDC channel
ON-state resistor: 50 (maximum)
100 kHz 3.3 V voltage swing signal
Both AUXIO+ and AUXIO outputs have 85 k (20 %) resistors
The 85 k AUXIO pull-up resistor
The 85 k AUXIO+ pull-down resistor is always present
2.2 DP MUX 2 : 1 switch
Multiplexes between differential DP ML signal and LSTX/LSRX signals
The DP ML (DisplayPort Main Link) runs up to HBR2 data rate of 5.4 Gbit/s
The low speed DC-coupled signals LSTX and LSRX are 3.3 V single-ended signals
that operate at 1 Mbit/s
5.4 Gbit/s DP-DPMLO path for DP MUX
Low insertion loss for DP-DPMLO path: 1.2 dB at 2.7 GHz
Low return loss for DP-DPMLO path: 15 dB at 2.7 GHz
Low ON-state resistance for DP-DPMLO path: 9
High bandwidth: 5.5 GHz
Low off-state isolation: 20 dB at 2.7 GHz
Low crosstalk: 25 dB at 2.7 GHz
Common-mode input voltage VIC: 0 V to 3.3 V
Differential input voltage VID: 1.4 V (maximum)
LS-DPMLO path for DP MUX
Low insertion loss: single-ended insertion loss (ON) is 1.0 dB at 5 MHz
Low return loss: single-ended return loss (ON) is 20 dB at 5 MHz
Low ON-state resistance: 16 (typical) for VDD = 3.3 V
High bandwidth: Single-ended 3 dB bandwidth is 1 GHz
Low off-state isolation: single-ended insertion loss (OFF) is 60 dB at 5 MHz
Low crosstalk: 40 dB at 5 GHz
2.3 General
The input of the HPD (Hot Plug Detect) buffer is 5 V tolerant
HPDOUT and CA_DETOUT buffers
CA_DET input leakage current < 0.1 A to prevent driving the 1 M pull-down to a
HIGH level
Integrated LSRX buffer with 1 M pull-down resistor (R1) on the LSRX buffer input
Integrated 8.75 k pull-up resistor (R4) on the LSTX pin
CBTL05024
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 21
CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
When AUXIO_EN = 1, TB_ENA = 0 and DP_PD = 1, the CBTL05024 is in
Detect mode
AUXIO+ and AUXIO of the TB MUX are disabled
LS path is selected in DP MUX
CA_DET and HPD buffers are on
When the CBTL05024 is in Detect mode, this chip consumes < 18 W
Patent-pending high bandwidth analog pass-gate technology
Very low intra-pair differential skew (5 ps typical)
Back current protection on connector pins (AUXIO+/, DPMLO+/, CA_DET and HPD
pins)
All channels support rail-to-rail input voltage
All CMOS input buffer with hysteresis
Single 3.3 V 10 % power supply
HVQFN24 3 mm 3 mm package, 0.4 mm pitch, exposed center pad for thermal relief
and electrical ground
ESD: 2000 V HBM, 1000 V CDM
Operating temperature range 20 C to 85 C
3. Ordering information
Table 1.
Ordering information
Type number
CBTL05024BS
[1]
Topside
marking
Package
Name
Description
024
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads; SOT905-1
24 terminals; body 3 3 0.85 mm[1]
Version
Maximum package height is 1 mm.
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature
CBTL05024BS
CBTL05024BSHP
HVQFN24
Reel 13” Q2/T3
*standard mark SMD
6000
Tamb = 20 C to +85 C
CBTL05024
Product data sheet
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Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 21
CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
4. Block diagram
CBTL05024
CONTROL
LOGIC
TB_ENA
AUXIO_EN
DP_PD
3.3 V
TB−
R3
85 kΩ
TB+
AUXIO−
10G
MUX
2:1
AUX−
AUX+
AUX
MUX
2:1
DDC_DAT
AUXIO+
R2
85 kΩ
DDC_CLK
CA_DET
CA_DETOUT
DP+
DP−
3.3 V
DPMLO+
DP
MUX
2:1
R4
8.75 kΩ
DPMLO−
LSTX
LSRX
LSRX buffer
R1
1 MΩ
HPD
HPDOUT
002aag997
Fig 1.
CBTL05024
Product data sheet
Block diagram of CBTL05024
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Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 21
CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
5. Pinning information
CA_DET
18
19 DPMLO+
20 DPMLO−
21 GND
22 AUXIO+
23 AUXIO−
terminal 1
index area
24
AUXIO_EN
5.1 Pinning
AUX− 1
17 HPD
AUX+ 2
16 CA_DETOUT
CBTL05024BS
VDD 3
15 TB_ENA
14 LSTX
DDC_DAT 4
Transparent top view
12
HPDOUT
DP+ 11
DP− 10
13 LSRX
GND 9
TB+ 8
TB− 7
DP_PD
6
DDC_CLK 5
GND(1)
002aag998
(1) Center pad is connected to PCB GND plane for electrical grounding and thermal relief.
Refer to Section 10 for package-related information.
Fig 2.
CBTL05024
Product data sheet
Pin configuration
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Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 21
CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
5.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
1
differential I/O
AUX+
2
differential I/O
AUX differential signals. The input to this pin must
be AC-coupled externally.
TB
7
differential I/O
TB+
8
differential I/O
Thunderbolt differential signals. These output
signals must be AC-coupled externally.
AUXIO
23
differential I/O
Differential signals for TB MUX.
AUXIO+
22
differential I/O
DDC_CLK
5
single-ended I/O
DDC_DAT
4
single-ended I/O
DP
10
differential I/O
DP+
11
differential I/O
High-speed differential pair. The input to this pin
must be AC-coupled externally.
DPMLO
20
differential I/O
Differential signals for DP MUX.
DPMLO+
19
differential I/O
LSRX
13
single-ended output Single-ended TB low speed receive signal.
LSTX
14
single-ended I/O
Single-ended TB low speed transmit signal.
Data path signals
AUX
Pair of single-ended terminals for DDC clock and
data signals.
Control signals
HPDOUT
12
CMOS output
Output buffer for HPD.
HPD
17
CMOS input
HPD input with 5 V tolerance.
CA_DET
18
CMOS input
When CA_DET = HIGH, DDC_CLK and DDC_DAT
is selected. When CA_DET = LOW, AUX path is
selected.
CA_DETOUT
16
CMOS output
3.3 V CMOS output buffer for CA_DET.
TB_ENA
15
CMOS input
The control input signal to enable Thunderbolt path
for TB MUX.
AUXIO_EN
24
CMOS input
The control signal for TB MUX.
DP_PD
6
CMOS input
The control signal for DP MUX. This MUX must
work during initial power-up that might have
VDD = 2.3 V.
Power
3.3 V supply. Pin 3 must be connected to system
power supply.
3.3 V supply option
VDD
3
Ground connections
CBTL05024
Product data sheet
GND
9, 21
Ground
Supply ground (0 V).
GND
center
pad
Ground
The center pad must be connected to GND plane
for both electrical grounding and thermal relief.
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Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
6. Functional description
Refer to Figure 1 “Block diagram of CBTL05024”.
The following sections describe the individual block functions and capabilities of the
device in more detail.
6.1 Buffer function tables
Table 4.
HPD buffer
HPD input
HPDOUT output
0
0
1
1
Table 5.
CA_DET buffer
CA_DET input
CA_DETOUT output
0
0
1
1
6.2 AUX MUX function table
Table 6.
2 : 1 AUX MUX function
CA_DET input
AUXIO
0
AUX
1
DDC
6.3 Operation modes of both DPML MUX and TB MUX
Table 7.
Operation modes
AUXIO_EN
TB_ENA
DP_PD
CA_DET
AUXIO
DPMLO
Modes
0
0
X
0
X
3-state
3-state
DP Standby mode
ON
ON
X
1
X
3-state
LS
Standby mode
ON
ON
1
0
0
0
AUX input
DP input
DP mode
ON
ON
1
0
0
1
DDC
DP input
DP++ mode
ON
ON
1
0
1
X
3-state
LS
Detect mode
ON
ON
1
1
0
1
TB
DP input
Test mode[1]
OFF
ON
1
1
0
0
3-state
3-state
Sleep mode
OFF
ON
1
1
1
X
TB
LS
TB mode
OFF
ON
[1]
R3
R2
HPD must be LOW during Test mode.
CBTL05024
Product data sheet
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Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
7. Limiting values
Table 8.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Min
Max
Unit
supply voltage
[1]
0.3
+4.6
V
VI
input voltage
[1]
0.3
+5.5
V
Tstg
storage temperature
65
+150
C
HBM
[2]
-
2000
V
CDM
[3]
-
1000
V
VDD
VESD
Parameter
Conditions
electrostatic discharge
voltage
[1]
All voltage values, except differential voltages, are with respect to network ground terminal.
[2]
Human Body Model: ANSI/ESDA/JEDEC JDS-001-2012 (Revision of ANSI/ESDA/JEDEC JS-001-2011),
ESDA/JEDEC Joint standard for ESD sensitivity testing, Human Body Model – Component level;
Electrostatic Discharge Association, Rome, NY, USA; JEDEC Solid State Technology Association,
Arlington, VA, USA.
[3]
Charged Device Model: JESD22-C101E December 2009 (Revision of JESD22-C101D, October 2008),
standard for ESD sensitivity testing, Charged Device Model – Component level; JEDEC Solid State
Technology Association, Arlington, VA, USA.
8. Recommended operating conditions
Table 9.
Operating conditions
Symbol
Parameter
VDD
supply voltage
Conditions
3.3 V supply option
input voltage
Tamb
[1]
CBTL05024
Product data sheet
ambient temperature
Typ
Max
Unit
3.0
3.3
3.6
V
2.3
-
-
V
CMOS inputs
0.3
-
+5.5
V
MUX I/O pins
0.3
-
VDD + 0.3
V
operating in free air
20
-
+85
C
initial supply voltage
before power supply
negotiation done
VI
Min
[1]
During power supply negotiation only a limited supply voltage is available. The control logic and
multiplexers must be in full function with degraded performance. The channel between LSTX/LSRX and
DPMLO+/ must work. The initial Ron of DP MUX in Table 14 should be < 50 .
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Rev. 4 — 27 March 2014
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CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
9. Characteristics
9.1 Device general characteristics
Table 10.
Symbol
IDD
Pcons
General characteristics
Parameter
Conditions
Min
Typ
Max
Unit
supply
current[1]
TB mode; VDD = 3.6 V
-
0.25
0.35
mA
power
consumption[1]
TB mode; VDD = 3.6 V; AUXIO_EN = 1,
TB_ENA = 1 and DP_PD = 1
-
0.825
1.26
mW
DP or DP++ modes; AUXIO_EN = 1,
TB_ENA = 0 and DP_PD = 0
-
0.66
1.00
mW
Sleep or DP Standby modes;
(AUXIO_EN = 1, TB_ENA = 1 and
CA_DET = DP_PD = 0) for Sleep mode
or (AUXIO_EN = 0 and DP_PD = 0) for
DP Standby mode
-
1
18
W
Detect mode; AUXIO_EN = 1,
TB_ENA = 0 and DP_PD = 1
-
1
18
W
Standby mode; AUXIO_EN = 0,
TB_ENA = X and DP_PD = 1
-
1
18
W
-
100
500
s
-
50
100
s
tstartup
start-up time
supply voltage valid to channel specified
operating characteristics
trcfg
reconfiguration time
DP_PD, AUXIO_EN, TB_ENA or
CA_DET state change to channel
specified operating characteristics
[2]
[1]
Do not include current through R4.
[2]
Outputs are undefined during reconfiguration, including enable and disable time of the multiplexers.
9.2 3 : 1 TB MUX channel characteristics
Table 11.
TB channel of 2 : 1 10G MUX dynamic and static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DDIL
differential insertion loss
channel is OFF
f = 5 GHz
-
20
-
dB
f = 100 MHz
-
55
-
dB
f = 5 GHz
-
1.3
-
dB
f = 100 MHz
-
1
-
dB
f = 5 GHz
-
20
-
dB
f = 100 MHz
-
22
-
dB
f = 5 GHz
-
18
-
dB
f = 2.7 GHz
-
25
-
dB
f = 100 MHz
-
60
-
dB
f = 1 MHz
-
70
-
dB
-
8.5
12
channel is ON
DDRL
DDNEXT
Ron
differential return loss
differential near-end crosstalk
ON-state resistance
CBTL05024
Product data sheet
adjacent channels are ON
VDD = 3.3 V; VI = 3.3 V;
II = 5 mA
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Rev. 4 — 27 March 2014
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CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
Table 11.
TB channel of 2 : 1 10G MUX dynamic and static characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
B3dB
3 dB bandwidth
differential
-
10
-
GHz
tPD
propagation delay
between AUXIO and TB
-
70
-
ps
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
VI
input voltage
TB+/TB and AUXIO+/AUXIO
0
-
VDD + 0.3
V
VID
differential input voltage
TB+/TB and AUXIO+/AUXIO
-
-
1.2
V
Table 12.
AUX - AUXIO channel of AUX MUX dynamic and static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DDIL
differential insertion loss
channel is OFF
f = 5 MHz
-
80
-
dB
f = 360 MHz
-
60
-
dB
f = 5 MHz
-
1.1
-
dB
f = 360 MHz
-
1.2
-
dB
f = 5 MHz
-
19
-
dB
f = 360 MHz
-
18
-
dB
f = 5 GHz
-
18
-
dB
f = 2.7 GHz
-
25
-
dB
f = 100 MHz
-
60
-
dB
f = 1 MHz
-
70
-
dB
-
13
16
channel is ON
DDRL
DDNEXT
differential return loss
differential near-end crosstalk
adjacent channels are ON
Ron
ON-state resistance
B3dB
3 dB bandwidth
differential
-
3
-
GHz
tPD
propagation delay
between AUX and AUXIO
-
70
-
ps
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
VI
input voltage
AUX+/AUX and AUXIO+/AUXIO
0
-
VDD
V
VIC
common-mode input voltage
AUX+/AUX and AUXIO+/AUXIO
0
-
VDD
V
VID
differential input voltage
AUX+/AUX and AUXIO+/AUXIO
-
-
1.4
V
ILIH
HIGH-level input leakage current
AUX+/AUX pins;
VDD = max; VI = VDD
-
-
1
A
ILIL
LOW-level input leakage current
AUX+/AUX pins;
VDD = max; VI = GND
-
-
1
A
CBTL05024
Product data sheet
VDD = 3.3 V; II = 10 mA;
VIC = 0.9VDD for AUXIO;
VIC = 0.1VDD for AUXIO+
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Rev. 4 — 27 March 2014
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CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
Table 13.
DDC - AUXIO channel of AUX MUX dynamic and static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ron
ON-state resistance
VDD = 3.3 V; II = 10 mA
-
35
50
Cin
input capacitance
VDD = 3.3 V; VI = 3.3 V
-
0.2
-
pF
tPD
propagation delay
between DDC and AUXIO
-
70
-
ps
ILIH
HIGH-level input leakage current
DDC_DAT and DDC_CLK pins;
VDD = max; VI = VDD
-
-
1.5
A
ILIL
LOW-level input leakage current
DDC_DAT and DDC_CLK pins;
VDD = max; VI = GND
-
-
1.5
A
9.3 DP MUX channel characteristics
Table 14.
Channel dynamic and static characteristics
Symbol
Parameter
Conditions
DDIL
differential insertion loss
DP-DPMLO path; channel is OFF
f = 2.7 GHz
Min
Typ
Max
Unit
-
20
-
dB
f = 1.35 GHz
-
35
-
dB
f = 100 MHz
-
50
-
dB
-
1.2
-
dB
DP-DPMLO path; channel is ON
f = 2.7 GHz
il(se)
DDRL
single-ended insertion loss
differential return loss
f = 1.35 GHz
-
1.1
-
dB
f = 100 MHz
-
0.8
-
dB
LS-DPMLO path; channel is OFF;
f = 5 MHz
-
60
-
dB
LS-DPMLO path; channel is ON;
f = 5 MHz
-
1
-
dB
f = 2.7 GHz
-
15
-
dB
f = 100 MHz
-
20
-
dB
-
18
-
dB
-
18
-
dB
DP-DPMLO path
rl(se)
single-ended return loss
DDNEXT
differential near-end crosstalk adjacent channels are ON
LS-DPMLO path; f = 5 MHz
f = 5 GHz
Ron
B3dB
ON-state resistance
3 dB bandwidth
f = 2.7 GHz
-
25
-
dB
f = 100 MHz
-
60
-
dB
f = 1 MHz
-
70
-
dB
-
9
12
DP-DPMLO path; VDD = 3.3 V; II = 5 mA
LS-DPMLO path; VDD = 3.3 V; II = 5 mA
-
16
22
initial ON-state resistance before
power supply negotiation done;
VDD = 2.3 V; II = 5 mA
-
35
50
differential; DP-DPMLO path
-
5.5
-
GHz
single-ended; LS-DPMLO path
-
1
-
GHz
tPD
propagation delay
between DP+/DP and
DPMLO+/DPMLO
-
100
-
ps
tsk(dif)
differential skew time
intra-pair
-
5
-
ps
CBTL05024
Product data sheet
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Rev. 4 — 27 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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CBTL05024
NXP Semiconductors
High performance MUX/deMUX switch for Thunderbolt applications
Table 14.
Channel dynamic and static characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VI
input voltage
LSTX/LSRX to DPMLO+/DPMLO
channel
0.3
-
VDD + 0.3
V
VIC
common-mode input voltage
DP+/DP and DPMLO+/DPMLO
0
-
VDD
V
VID
differential input voltage
DP+/DP to DPMLO+/DPMLO
channel
-
-
1.4
V
ILIH
HIGH-level input leakage
current
DP+/DP and DPMLO+ pins;
VDD = max; VI = VDD
-
-
1
A
DPMLO pins; VDD = max; VI = VDD
-
-
5
A
ILIL
LOW-level input leakage
current
DP+/DP and DPMLO+/DPMLO pins;
VDD = max; VI = GND
-
-
1
A
9.4 Control signals characteristics
Table 15.
CA_DET input buffer characteristics
Symbol
Parameter
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
ILI
input leakage current
[1]
Conditions
measured with input at VIH = VDD
and VIL = 0 V
[1]
Min
Typ
Max
Unit
2
-
-
V
-
-
0.8
V
-
-
0.1
A
Min
Typ
Max
Unit
The leakage current on CA_DET pin must not drive the 1 M pull-down to a HIGH level.
Table 16.
HPD input buffer characteristics
Symbol
Parameter
VIH
HIGH-level input voltage
2
-
5
V
VIL
LOW-level input voltage
-
-
0.8
V
Table 17.
Conditions
TB_ENA, DP_PD or AUXIO_EN input characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage
CMOS inputs
0.7 VDD
-
-
V
VIL
LOW-level input voltage
CMOS inputs
-
-
0.3 VDD
V
ILI
input leakage current
measured with input at VIH = VDD
and VIL = 0 V
-
1
10
A
Table 18.
CA_DETOUT and HPDOUT output buffer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
IOL = 2 mA; VDD = 3 V
0
-
0.4
V
VOH
HIGH-level output voltage
pull-up voltage; IOH = 2 mA;
VDD = 3 V
2.5
-
-
V
tPD
propagation delay
load capacitance CL = 5 pF
-
50
100
ns
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9.5 Integrated LSRX buffer characteristics
Table 19.
LSRX buffer characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth(LH)
positive-going threshold voltage
input; VDD = 3.3 V 10 %
0.9
1.1
1.24
V
input; VDD = 2.3 V
0.8
0.9
1.02
V
input; VDD = 3.3 V 10 %
0.58
0.7
0.84
V
input; VDD = 2.3 V
0.5
0.57
0.63
V
IOL = 2 mA; VDD = 3 V
-
0.2
0.4
V
IOL = 0.5 mA; VDD = 2.3 V
-
0.1
0.2
V
pull-up voltage; IOH = 2 mA;
VDD = 3 V
2.5
-
-
V
pull-up voltage; IOH = 0.5 mA;
VDD = 2.3 V
2.1
-
-
V
load capacitance CL = 8 pF
-
2
10
ns
Vth(HL)
VOL
VOH
tPD
negative-going threshold voltage
LOW-level output voltage
HIGH-level output voltage
propagation delay
9.6 Bias resistor characteristics
Table 20.
Characteristics of AUXIO+ pin in DP/DP++ mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rpd
pull-down resistance
resistor R2;
AUXIO_EN = 1, TB_ENA = DP_PD = 0
68
85
102
k
Table 21.
Characteristics of AUXIO pin in DP/DP++ mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
pull-up resistance
resistor R3;
AUXIO_EN = 1, TB_ENA = DP_PD = 0
68
85
102
k
Table 22.
Characteristics of DPMLO pin in TB mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rpd
pull-down resistance
resistor R1;
AUXIO_EN = TB_ENA = DP_PD = 1
0.8
1
1.2
M
Table 23.
Characteristics of LSTX pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
pull-up resistance
resistor R4
7
8.75
10.5
k
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11. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
11.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
11.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
11.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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11.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 4) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 24 and 25
Table 24.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 25.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 4.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 4.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
12. Abbreviations
Table 26.
CBTL05024
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DP
DisplayPort
ESD
ElectroStatic Discharge
HBM
Human Body Model
HPD
Hot Plug Detect
I/O
Input/Output
MUX
multiplexer
PCB
Printed-Circuit Board
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13. Revision history
Table 27.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTL05024 v.4
20140327
Product data sheet
-
CBTL05024 v.3
Modifications:
•
The security status of this data sheet has been altered from company confidential to company
public.
CBTL05024 v.3
20131014
Product data sheet
-
CBTL05024 v.2
CBTL05024 v.2
20130715
Product data sheet
-
CBTL05024 v.1
CBTL05024 v.1
20121116
Product data sheet
-
-
CBTL05024
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
CBTL05024
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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16. Contents
1
2
2.1
2.2
2.3
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
7
8
9
9.1
9.2
9.3
9.4
9.5
9.6
10
11
11.1
11.2
11.3
11.4
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
TB MUX 3 : 1 switch . . . . . . . . . . . . . . . . . . . . . 1
DP MUX 2 : 1 switch. . . . . . . . . . . . . . . . . . . . . 2
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Buffer function tables . . . . . . . . . . . . . . . . . . . . 7
AUX MUX function table . . . . . . . . . . . . . . . . . . 7
Operation modes of both DPML MUX and
TB MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device general characteristics . . . . . . . . . . . . . 9
3 : 1 TB MUX channel characteristics. . . . . . . . 9
DP MUX channel characteristics . . . . . . . . . . 11
Control signals characteristics . . . . . . . . . . . . 12
Integrated LSRX buffer characteristics . . . . . . 13
Bias resistor characteristics . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering of SMD packages . . . . . . . . . . . . . . 15
Introduction to soldering . . . . . . . . . . . . . . . . . 15
Wave and reflow soldering . . . . . . . . . . . . . . . 15
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 March 2014
Document identifier: CBTL05024
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