FS32V234BMN1VUB

NXP Semiconductors Data Sheet: Technical Data Document Number S32V234 Rev. 9, 03/2020 S32V234 S32V234 Data Sheet Features • ARM® Cortex®-A53, 64-bit CPU – Up to 1000 MHz Quad ARM Cortex-A53 – 32 KB/32 KB I-/D- L1 Cache – NEON MPE co-processor – Dual precision FPU – 2 clusters with 2 CPUs and 256 KB L2 cache each – Memory Management Unit – GIC Interrupt Controller – ECC/parity error support for its memories – Generic timers – Fault encapsulation by hardware for redundant executed application software on multiple core cluster • ARM Cortex-M4, 32-bit CPU – Up to 133 MHz – 16 KB/16 KB I-/D- L1 Cache – 32+32 KB tightly coupled memory (TCM) – ECC/parity support for its memories • Clocks – Phase Locked Loops (PLLs) – 1 external crystal oscillator (FXOSC) – 1 FIRC oscillator • System protection and power management features – Flexible run modes to consume low power based on application needs – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents – Power gating of unused A53 cores and GPU – Low and high voltage warning and detect – Hardware CRC module to support fast cyclic redundancy checks (CRC) – 120-bit unique chip identifier – Hardware watchdog – eDMA controller with 32 channels (with DMAMUX) – Extended Resource Domain Controller • Safety concept – ISO 26262, ASIL level target – Measures to detect faults in memory and logic – Measures to detect single point and latent faults – Quantitative out of context analysis of functional safety (FMEDA) tailored to application specifics – Safety manual and FMEDA report available • Security – CSE with 16 KB of on-chip Secure RAM and ROM. – ARM TrustZone (TZ) architecture support – Boot from NOR flash with AES-128 (CTR) – On-Chip One-Time Programmable element Controller (OCOTP_CTRL) with on chip electrical fuse array. – System JTAG Controller (SJC) • Debug functionality – Standard JTAG and Compact JTAG – 16-bit Trace port, Serial Wire Output port • Timers – General purpose timers (FTM) – Two Periodic Interrupt Timer (PIT) – IEEE 1588 Timers (part of Ethernet Subsystem) • Analog – 1x 12-bit 1.8 V SAR ADC with self-test • Communications – UART(w/ LIN2.1l) – Serial peripheral interface (SPI) – I2C blocks – PCI express 2.0 with endpoint and root complex support – LFAST serial link – 1 GBit Ethernet with PTP IEEE 1588 – FD-CAN – FlexRay Dual Channel, Version 2.1 RevA NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. • Memory interfaces – 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock frequency with ECC (SEC-DED-TED) triple error detection support for subregion – QuadSPI supporting Execute-In-Place (XIP) – Boot flash fault detection and correction using two-dimensional parity. – Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection. • Video input interfaces, Image processing, graphics processing, display – Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding – GPU GC3000 with frame buffer compression – 2x VIU (Video interface unit) for camera input – 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps) – Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions (exposure control, gamma correction) – 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) cores configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMD engines with 32 16-bit CUs each. – CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter – JPEG video decoder (8/12-bit) – H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats – H.264 video encode (8/10/12-bit), High-intra only – Fast DMA for data transfers between DRAM and System RAM with CRC • Human-Machine Interface (HMI) – GPIO pins with interrupt support, DMA request capability, digital glitch filter – Configurable slew rate and drive strength on all output pins • System RAM – 4 MB On-Chip System RAM with ECC S32V234 Data Sheet, Rev. 9, 03/2020 2 NXP Semiconductors Table of Contents 1 Block diagram.................................................................................... 5 2 Family comparison.............................................................................5 2.1 3 4 5 Feature Set...............................................................................5 Memory interfaces...................................................................26 6.3.1 6.4 QuadSPI AC specifications....................................... 26 DDR SDRAM Specific Parameters (DDR3, DDR3L, and Ordering parts.....................................................................................8 LPDDR2)................................................................................ 31 3.1 Ordering information...............................................................8 6.4.1 DDR3 and DDR3L timing parameters ..................... 31 General............................................................................................... 8 6.4.2 DDR3 and DDR3L read cycle...................................33 4.1 Operation above maximum operating conditions................... 8 6.4.3 DDR3 and DDR3L write cycle................................. 34 4.2 Recommended operating conditions....................................... 9 6.4.4 LPDDR2 timing parameter........................................35 4.3 Power Management Controller (PMC) electrical 6.4.5 LPDDR2 read cycle...................................................37 specifications...........................................................................10 6.4.6 LPDDR2 write cycle................................................. 38 4.4 Power consumption................................................................. 11 4.5 Electrostatic discharge (ESD) specifications.......................... 13 6.5.1 DSPI timing............................................................... 39 4.6 Electromagnetic Compatibility (EMC) specifications............ 13 6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface 4.7 PCB routing guidelines........................................................... 13 6.5 Communication modules.........................................................39 (uSDHC)....................................................................43 I/O parameters....................................................................................15 6.5.2.1 SDR mode timing specifications........... 43 5.1 6.5.2.2 DDR mode timing specifications...........45 5.2 General purpose I/O parameters..............................................15 5.1.1 GPIO speed at various voltage levels........................ 15 5.1.2 DC electrical specifications....................................... 17 6.5.3.1 LFAST interface timing diagrams......... 48 DDR pads................................................................................ 18 6.5.3.2 LFAST Interface electrical 5.2.1 5.2.2 5.2.3 characteristics........................................ 49 DDR3 mode DC electrical 6.5.4 FlexRay timing parameters....................50 DDR3L mode............................................................ 18 6.5.4.2 TxEN......................................................50 5.2.2.1 DDR3L mode DC electrical 6.5.4.3 TxD........................................................ 51 specifications......................................... 18 6.5.4.4 RxD........................................................52 LPDDR2 mode.......................................................... 19 6.5.5 Ethernet Controller (ENET) Parameters................... 53 LPDDR2 mode DC electrical 6.5.5.1 Ethernet Switching Specifications......... 53 specifications......................................... 19 6.5.5.2 Receive and Transmit signal timing Boot Configuration Pins Specification....................................20 specifications for RMII interfaces......... 53 6.5.5.3 Analog modules.......................................................................20 6.1.1 6.1.2 Receive and Transmit signal timing specifications for MII interfaces............ 54 ADC electrical specifications.................................... 20 6.1.1.1 6.2 FlexRay......................................................................50 6.5.4.1 Peripheral operating requirements and behaviors.............................. 20 6.1 LFAST electrical characteristics............................... 48 specifications......................................... 18 5.2.3.1 5.3 6.5.3 DDR3 mode...............................................................18 5.2.1.1 6 6.3 6.5.5.4 Input equivalent circuit.......................... 21 Receive and Transmit signal timing specifications for RGMII interfaces...... 56 Thermal Monitoring Unit (TMU)..............................23 6.5.5.5 Clocks and PLL interfaces modules........................................23 MII/RMII Serial Management channel timing (MDC/MDIO)............................ 57 6.2.1 Main oscillator electrical characteristics................... 23 6.5.6 PCI Express specifications........................................ 58 6.2.2 48 MHz FIRC electrical characteristics.................... 24 6.5.7 IIC timing.................................................................. 59 6.2.3 PLL electrical specifications..................................... 24 6.5.8 LINFlex timing.......................................................... 60 6.2.4 DFS electrical specifications..................................... 25 6.2.5 LFAST PLL Electrical Specifications.......................25 6.6 Display modules......................................................................61 6.6.1 Display Control Unit (2D-ACE) Parameters.............61 S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 3 6.6.1.1 Interface to TFT panels..........................61 6.6.1.2 Interface to TFT LCD Panels—Pixel 6.10 External interrupt timing (IRQ pin)........................................ 74 7 Level Timings........................................ 62 6.6.1.3 Interface to TFT LCD panels—access 7.1 8 level........................................................63 6.6.2 Video input unit (VIU) timing specifications............64 6.6.3 MIPICSI2 D-PHY electrical and timing parameters.65 6.6.3.6 Thermal attributes.............................................................................. 75 Dimensions.........................................................................................76 8.1 9 Thermal attributes................................................................... 75 Obtaining package dimensions ...............................................76 Pinouts................................................................................................76 9.1 Package pinouts and signal descriptions................................. 76 NOTICE OF DISCLAIMER................. 68 10 Reset sequence................................................................................... 76 Debug specifications............................................................... 69 10.1 Reset sequence duration.......................................................... 76 6.7.1 JTAG interface timing............................................... 69 10.2 Boot performance matrix........................................................ 77 6.7.2 Debug trace timing specifications............................. 73 10.3 Reset sequence description......................................................78 6.8 Wakeup Unit (WKPU) AC specifications.............................. 74 11 Power sequencing requirements.........................................................80 6.9 RESET pin glitch filter specifications.....................................74 12 Revision history................................................................................. 81 6.7 S32V234 Data Sheet, Rev. 9, 03/2020 4 NXP Semiconductors Block diagram 1 Block diagram XRDC SEQ 128bits MC XRDC 128bits 4KB PRAM 64KB CRAM 16KB KRAM MC Sequencer Debug MIPI-CSI2 MIPI-CSI2 ISP0 ISP1 ISP2 ••• ISPN H.264 Encoder H.264 Decoder JPEG Decoder 128bits 64bits 128-bits 128-bits 128bits 64bits Hierarchical NIC 301 AXI Bus System incl. EDC XRDC XRDC 128-bits 128bits SRAM - all others 64-bits AHB Cortex-A53 16KB 16KB I-Cache D-Cache 64-bits AHB 32-bits 64-bits AHB AHB 64-bits AHB CSE-FL Security Engine 16KB DRAM 1KB FUSE IF ROM Sideband BIU Outputs 64-bits AHB 64-bits AXBS Bus System incl. EDC XRDC 64-bits DRAM - SRAM all others all others 64-bits 64-bits Debug DRAM-ECC DRAM-ECC 32-bit MMDC_0 LPDDR2 DDR3(L) 32-bit MMDC_1 LPDDR2 DDR3(L) DDR-PHY DDR-PHY 533 MHz 1066 MT/s DDR 64-bits 64-bits AHB 64-bits 64-bits OTFAD Peripheral Bridge 1 32-bits QuadSPI NOR Flash Ctrl 2x4-bits ROM Ctrl 32-bits 4/2x4/8-bits QSPI Flash External NOR Flash Off-Chip 64 KB ROM (boot) Peripheral Bridge 0 32-bits SWT_0 SWT_1 STM_0 PIT_0 STCU MC CGM, RGM, PCU, ME 533 MHz 1066 MT/s DDR MEMU SEMA4 MSCM ERM + EIM PMC TSENS SSE PIT_1 CGM-CMUs INTC_MON STM_1 SWT_2 SWT_3 SWT_4 FlexTimer_1 IIC_1 IIC_2 Linflex_1 CAN_FD_1 DSPI_1 DSPI_3 CRC_1 FCCU 4MB SRAM 24+Banks ECC x64 Internal 64-bits AHB 32-bits QoS 301 incl. EDC XRDC SRAM Controller Multi Ported Multi Banked DMA MEM eDMA Debug Concentrator 64-bits AHB NVIC 64KB CoreP 133MHz TCM CortexM4 Debug ChanMux 128-bits CCI-400 incl. EDC ChanMux 128-bits 320 Mbps 10 Mbps 5 Gbps 1 Gbps DEC200 DEC200 Decoder Encoder SCU SIPI+LFAST FlexRay SDHC SCU PCIe Ethernet AVB CDC420 Encoder Fast DMA Core3 Debug 1000MHz Cortex-A53 NEON/FPU 32KB 32KB 256KB I-Cache D-Cache L2Cache SIUL Wake Up OCOTP_CTRL SARADC_0 FlexTimer_0 IIC_0 Linflex_0 CAN_FD_0 DSPI_0 DSPI_2 CRC_0 MC CRC Display Control Unit GPU GC3000 (2D-ACE) Core1 Debug Core2 Debug 1000MHz 1000MHz Cortex-A53 Cortex-A53 NEON/FPU NEON/FPU 32KB 32KB 256KB 32KB 32KB I-Cache D-Cache L2- I-Cache D-Cache Cache H.264 Dec GPU DCU APEX-2_0 APEX-2_1 FastDMA all others PCIe/ENET Cores 64bits Debug APEX-2_1 (2xAPU) CMEM 16x 2Kx64 32KB 32KB IMEM DMEM Seq MEMIF BlkDMA DMA VIU_H264 APEX-2_0 APEX-2_1 FastDMA all others PCIe/ENET Cores MC Debug APEX-2_0 (2xAPU) CMEM 16x 2Kx64 32KB 32KB IMEM DMEM MEMIF Seq BlkDMA DMA MPU 16-bit VIU 16-bit VIU 4 Lanes 4 Lanes 100MHz 100MHz 24-bit RGB Display IF GIC-400 Core0 Debug 1000MHz Cortex-A53 NEON/FPU 32KB 32KB I-Cache D-Cache Figure 1. Block diagram 2 Family comparison 2.1 Feature Set This family of devices supports the following features: Table 1. Feature Set Feature ARM Cortex-A53 Core S32V234 • • • • • • • Up to 1000 MHz Quad ARM Cortex-A53 32 KB/32 KB I-/D- L1 Cache NEON MPE co-processor Dual precision FPU 256 KB L2 Cache per cluster MMU GIC interrupt controller S32V232 • Up to 1000 MHz Dual ARM Cortex-A53 (single cluster) • The remaining features are same as S32V234 Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 5 Family comparison Table 1. Feature Set (continued) Feature S32V234 S32V232 • ECC/parity error support for its memories • Generic timers ARM Cortex-M4 Core • Up to 133 MHz • 16 KB/16 KB I-/D- L1 Cache • 32+32 KB tightly coupled memory (TCM) • ECC/parity support for its memories • Same as S32V234 Clocks • Phase Locked Loops (PLLs) • 1 external crystal ocillators (FXOSC) • 1 FIRC • Same as S32V234 System, protection and power management features • Flexible run modes to consume lower power based on application needs. • Peripheral clock enable registers can disable clocks to unused modules, thereby reducing currents • Low and high voltage warning and detect • Hardware CRC module to support fast cyclic redundancy checks (CRC) • 120-bit unique chip identifier • Hardware watchdog • Safe eDMA controller with 32 channels (with DMAMUX) • Extended Resource Domain Controller • Same as S32V234 Safety concept • ISO 26262, ASIL level target as per safety concept • Measures detecting faults in memory and logic • Measures to detect single point and latent faults • Quantitative out of context analysis of functional safety (FMEDA) tailored to application specifics • Safety manual and FMEDA report available • Boot flash authentication and fault detection and correction using AES-128 and two-dimensional parity. • Double and triple fault detection and single fault correction scheme for external DDR-RAM including address/ page fault detection. • Fault encapsulation by hardware for redundant executed application software on multiple core cluster. • Structural software based self test routines providing high diagnostic coverage. • Same as S32V234 Debug • Standard JTAG • 16-bit Trace port, Serial Wire Output port • Same as S32V234 Timers • General purpose timers (FTM) • Same as S32V234 Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 6 NXP Semiconductors Family comparison Table 1. Feature Set (continued) Feature S32V234 S32V232 • Two Periodic Interrupt Timer (PIT) • IEEE 1588 Timers (part of Ethernet Subsystem) Communications • • • • UART(w/ LIN2.1l) Serial peripheral interface (SPI) I2C blocks PCI express 2.0 with endpoint and root complex support LFAST serial link 1 GBit Ethernet with PTP IEEE 1588 FD-CAN Flexray Dual Channel, Version 2.1 RevA • Same as S32V234 Memory Interfaces • 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock frequency with ECC (SEC-DED-TED) single error correction, double error detection, and triple error detection support for subregion • Dual QuadSPI supporting Execute-InPlace (XIP) • Same as S32V234 Video input interfaces, Image processing, graphics processing, display • Display Control Unit (2D-ACE) with 24bit RGB, GPU framebuffer decoding • GPU GC3000 with frame buffer compression • 2x Video interface unit (VIU) for camera input • 2x CSI with 4 lanes for camera input (support 1080p @ 30fps) • Image signal processor (ISP), supporting 2x1 or 1x2 MPixel @ 30fps and 4x1 MPixel for subset of functions (exposure control, gamma correction) • 2x APEX2-CL Image cognition processor (dual 32-bit array processor) • JPEG video decoder (8/12-bit) • H.264 video decoder (8/10/12-bit), Highintra and constrained baseline formats • H.264 video encoder (8/10/12-bit), Iframes only • Safe Fast DMA for data transfers between DRAM and System RAM with CRC • Same as S32V234 Analog • 1x 12-bit SAR ADC with self-test • Same as S32V234 Human-Machine Interface (HMI) • SIUL, GPIO pins with interrupt support, DMA request capability, digital glitch filter. • Configurable slew rate and drive strength on all output pins • Same as S32V234 System RAM • 4 MB On-Chip System RAM with ECC • 3 MB On-Chip System RAM with ECC Power Consumption • Run modes: • Same as S32V234 • • • • S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 7 Ordering parts Table 1. Feature Set Feature S32V234 S32V232 • Frequency scaling and clock gating for processing blocks and peripherals in run mode 3 Ordering parts 3.1 Ordering information FS32V23 4 B K N1 V UB R Device Family Core configuration Speed configuration Device configuration Temeprature options Shipping method Temperature options Core configuration Shipping method Speed configuration C = -40 to 105°C V = -40 to 125 °C 2 = Dual Arm Cortex - A53 4 = Quad Arm Cortex - A53 R = Tape and reel (blank) = Trays B = Arm Cortex - A53 @800 MHz C = Arm Cortex - A53 @1 GHz Device configuration* ISP 3D GPU CSE Low power (leakage based) eIQ Auto K Yes No Yes No K becomes Q L Yes No Yes Yes L becomes R M Yes Yes No No M becomes S O Yes Yes Yes No O becomes T J Yes No No Yes J becomes U * All combinations are not orderable NOTE Not all combinations are orderable. For the latest information on orderable parts check https:// www.nxp.com/s32v234 Buy/ Parametrics section. 4 General 4.1 Operation above maximum operating conditions S32V234 Data Sheet, Rev. 9, 03/2020 8 NXP Semiconductors General Table 2. Operation above maximum operating conditions 1.8 V DGO Voltage Domain Electrical Specifications Value Conditions Junct Temp Absolute Maximum Supply Voltage 3.0 V < 60 s 25 °C Absolute Maximum Supply Voltage 2.3 V < 10 hr 25 °C Electrical Specifications Value Conditions Junct Temp Absolute Maximum Supply Voltage 1.29 V < 60 s 25 °C Absolute Maximum Supply Voltage 1.1 V < 10 hr 25 °C Electrical Specifications Value Conditions Junct Temp Absolute Maximum Supply Voltage 4.95 V < 60 s 25 °C Absolute Maximum Supply Voltage 4.29 V < 10 hr 25 °C Core Voltage Domain 3.3 V DGO Voltage Domain 4.2 Recommended operating conditions Table 3. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VDD_GPIO0 3.3 V I/O segment GPIO0 supply voltage — 3.15 3.6 V VDD_GPIO 1.8 V input/output supply voltage — 1.71 1.95 V VDD_HV_IO_VIU0 3.3 V input/output supply voltage — 3.15 3.6 V 1.5 V I/O supply voltage — 1.425 1.575 V 1.8 V I/O supply voltage — 1.71 1.95 V 2.5 V I/O supply voltage — 2.375 2.625 V 3.3 V I/O supply voltage — 3.15 3.6 V — 0 0 V — 0.95 1.05 V VDD_HV_IO_VIU1 VDD_HV_IO_DIS VDD_HV_IO_FLA VDD_HV_IO_ETH VSS Common ground voltage1 voltage2 VDD_LV_CORE_SOC, VDD_LV_CORE_ARM, VDD_LV_CORE_GPU 1.0 V core domain supply VDD_HV_CSI 1.8 V supply voltage (for MIPICSI2 D PHY) — 1.71 1.95 V VDD_LV_CSI 1.0 V supply voltage (for MIPICSI2 D PHY) — 0.95 1.05 V VDD_HV_PLL, 1.8 V supply voltage (for analog circuits, PLLs) — 1.71 1.95 V Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 9 General Table 3. Recommended operating conditions (continued) Symbol Parameter Conditions Min Max Unit VDD_HV_LFASTPLL, VDD_HV_FXOSC, VDD_HV_PMC, VDDIO_LFAST, VDD_HV_EFUSE, VDD_HV_DDR VDD_LV_PLL 1.0 V supply voltage (for analog circuits, PLLs) — 0.95 1.05 V VREFH_ADC 1.8 V ADC high reference voltage — 1.71 1.95 V VDD_HV_ADV 1.8 V ADC supply voltage — 1.71 1.95 V VSS_HV_ADV ADC ground and low reference voltage — 0 0 V VREFL_ADC 1.8 V ADC supply ground — 0 0 V VDD_DDR_IO DDR I/O supply voltage LPDDR2 — 1.14 1.30 V DDR I/O supply voltage DDR3 — 1.425 1.575 V DDR I/O supply voltage DDR3L — 1.283 1.45 V PCIe supply voltages — 0.95 1.05 V — 1.71 1.95 V °C VDD_LV_POST PCIE_VP PCIE_VPH TA Ambient temperature — -40 1053 TJ Junction temperature under bias — -40 125 °C TVDD Supply ramp rate for all supplies on the device — 0.05 25 V/ms 1. All the grounds viz. VSS, VSS_FXOSC, and VSS_HV_ADV are tied together at the package level. 2. VDD_LV_CORE_SOC, VDD_LV_CORE_ARM, and VDD_LV_CORE_GPU supply balls should all be connected together to one power plane and one regulator to avoid voltage level differences. If the GPU is power gated as it is not used, the VDD_LV_CORE_GPU supply balls have to be statically connected to the ground plane. If the second ARM CPUs per cluster is power gated as they are not used, the VDD_LV_CORE_ARM supply balls have to be statically connected to the ground plane. 3. Maximum ambient temperature requires management of the heat dissipation to ensure the device junction temperature does not exceed the maximum. 4.3 Power Management Controller (PMC) electrical specifications PMC is composed of the following blocks: • Low voltage detector (LVD_33_PMC) for 3.3 V VDD_GPIO0 supply (GPIO segment and PMC) and Low Voltage Detector for FIRC (VDD_HV_FXOSC) • Low voltage detector (LVD_18) for VDD_HV_PMC • Low voltage detector (LVD_18) for VDD_HV_FXOSC • High voltage detector (HVD_18) for VDD_HV_PMC • Low voltage detector (LVD_CORE) for VDD_LV_CORE_SOC • High voltage detector (HVD_CORE) for VDD_LV_CORE_SOC • Power on Reset (POR) S32V234 Data Sheet, Rev. 9, 03/2020 10 NXP Semiconductors General Table 4. PMC electrical specifications Supply Parameter Conditions VDD_LV_CORE_SOC VDD_HV_PMC VDD_HV_PMC VDD_GPIO0 PMC_BGREF Typical Max 836 880 924 VTH2 850 895 940 VTL 896 910 924 VTH 911 925 946 VTL 1049 1065 1093 VTH 1064 1080 1093 VTL 1511 1590 1670 VTH 1525 1605 1685 VTL 1620 1650 1680 VTH 1635 1665 1695 PMC Trimmed supply high voltage monitor VTL 2004 2045 2086 VTH 2019 2060 2101 low voltage Native monitor VTL 2727 2870 3014 VTH 2746 2890 3035 VTL 2857 2915 2973 VTH 2876 2935 2994 VTL 1511 1590 1670 VTH 1525 1605 1685 VTL 1620 1650 1680 VTH 1635 1665 1695 – 1176 1200 1224 high voltage monitoring Trimmed PMC supply low voltage monitor Native Trimmed Trimmed VDD_HV_FXOSC Min VTL1 low voltage Native monitoring Trimmed VDD_LV_CORE_SOC Threshold FXOSC supply low voltage monitor Native Trimmed PMC Band Trimmed Gap Reference value Status during power-up Unit Enabled mV Disabled mV Enabled mV Disabled mV Enabled mV Enabled mV Enabled mV 1. Lower threshold/assert point 2. Upper threshold/release point 4.4 Power consumption The following table shows the power consumption data. These specifications are subject to change per device characterization. Table 5. Power consumption Parameter Description Max Values 125C Tj VDD_LV_CORE (Static)1, 2 32V234BL Device in reset 3A 105C Tj 2.3 A Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 11 General Table 5. Power consumption (continued) Parameter Description Max Values 125C Tj 105C Tj S32V232BM Device in reset 6.0 A 4.5 A S32V234CO Device in reset 6.4 A 4.8 A S32V234CK Device in reset 4.8 A 3.5 A S32V232BL Device in reset 2.7 A 2.0 A S32V232CK Device in reset 4.4 A 3.2 A VDD_LV_CORE (Dynamic) 4x A53 CPU with Dhrystone MIPS running on each CPU @1 GHz3 1.4 A VDD_HV_CSI Current for both MIPICSI2 interfaces operating as per 1) 10 mA 2) 1 mA 1) RX Operation at 1.5 Gbps per MIPICSI2 2) MIPICSI2 not used (IP Powered and Disabled) VDD_LV_CSI Current for both MIPICSI2 interfaces operating as per 1) 40 mA 2) 13 mA 1) RX Operation at 1.5 Gbps per MIPICSI2 2) MIPICSI2 not used (IP Powered and Disabled) VDD_HV_PLL All five PLLs operating at 1 GHz VCO frequency 35 mA VDD_HV_LFASTPLL Use case: 1) 26 mA 1) PLL operating with 320 MHz (LFAST used) 2) .1 mA 2) PLL not operational (LFAST not used) VDD_HV_FXOSC Shared supply for FXOSC operating with 40 MHz crystal and FIRC oscillator 5 mA VDD_HV_PMC As per default usage (no use case differentiation) 10 mA VDD_HV_EFUSE Use case: 1) 10 mA 1) eFuse programming happening VDD_LV_PLL All five PLLs operating at 1 GHz VCO frequency 80 mA PCIE_VP Use case: 1) 80 mA 1) 5 GHz operation (PCIe 2.0) 2) 30 mA 2) Reset/idle PCIE_VPH Use case: 1) 50 mA 1) 5 GHz operation (PCIe 2.0) 2) 20 mA Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 12 NXP Semiconductors General Table 5. Power consumption (continued) Parameter Description Max Values 125C Tj 105C Tj 2) Reset/idle VDD_HV_ADV ADC operational 1 mA VDD_REFH_ADC Voltage reference for ADC 80 μA 1. Data represented is at 125 °C Tj and 1.01 V vdd conditions 2. Includes SoC, GPU, and ARM supply combinations depending on use case description. 3. Adder to the static idd current component. 4xCortex A53 executing Dhrystone MIPS in AArch64 and the interconnect, System RAM, FastDMA, Cortex M4, peripheral bridges, FCCU, CSE, MEMU, PCIe, and STCU are clocked - static power consumption excluded. 4.5 Electrostatic discharge (ESD) specifications Electrostatic discharges are applied to the pins of each sample in conformity with AECQ100-002/-011 to meet the HBM and CDM ratings described below. Table 6. ESD ratings1 Symbol Parameter Conditions Class Max value2 Unit VESD(HBM) Electrostatic discharge (Human Body Model) TA = 25 °C conforming to AECQ100-002 H1C 2000 V VESD(CDM) Electrostatic discharge (Charged Device Model) TA = 25 °C conforming to AECQ100-011 C3A 500 V 1. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 2. Data based on characterization results, not tested in production. 4.6 Electromagnetic Compatibility (EMC) specifications EMC measurements to IC-level IEC standards are available from NXP on request. 4.7 PCB routing guidelines DDR3/DDR3L PCB design • CLK/Addess/Commands • Route with 50 ohm controlled impedance and differential pair (CLK) with 100 ohm controlled impedance • Use Fly by topology in case of multiple memory components • Address and command lines Terminated to VTT with 50 ohm • To be referenced with Power, not Ground S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 13 General • Address/Cmd to be routed within 66 mils with respect to CLK and to be matched from controller to memory; memory to memory as well • All traces to be routed in internal layers • Preference is to use only two layers for routing this group • Limit the via number to less than three NOTE The differential clock lines on the DDR3 interface should use AC termination scheme, with a 0.1 µF series capacitor and referenced to DDR IO supply (VDD_DDR_IO). • Data/Strobe • Route with 50 ohm controlled impedance and differential pair (DQS strobe) with 100 ohm controlled impedance • Data to be routed within 33 mils with respect to respective strobe • To be referenced with Ground • All traces to be routed in internal layers • Strictly to be routed in only two layers • Avoid more than two vias LPDDR2 PCB design • CLK/Addess/Commands • Route with 50 ohm controlled impedance and differential pair (CLK) with 100 ohm controlled impedance • To be referenced with Power, not Ground • Address/Cmd to be routed within 66 mils with respect to CLK and to be matched from controller to memory • All traces to be routed in internal layers and delay should be less than 150 ps • Preference is to use only two layers for routing this group • Limit the via number to less than three • Data/Strobe • Route with 50 ohm controlled impedance and differential pair (DQS strobe) with 100 ohm controlled impedance • Data to be routed within 33 mils with respect to respective strobe • To be referenced with Ground • All traces to be routed in internal layers and delay should be less than 150 ps • Strictly to be routed in only two layers • Avoid more than two vias GPIO Interfaces • QuadSPI • Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 S32V234 Data Sheet, Rev. 9, 03/2020 14 NXP Semiconductors I/O parameters • TRACE • Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 • ENET • Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 5 I/O parameters 5.1 General purpose I/O parameters 5.1.1 GPIO speed at various voltage levels NOTE Rise/fall times numbers in Datasheet are guaranteed by design; to obtain actual rise/fall times parameters with specific packages and boards, use appropriate I/O IBIS model. Table 7. GPIO rise/fall times (1.8 V range) Parameter Symbol IO output tpr transition time, rise/fall1 Drive strength SIUL2_MSCRn[D SE] 001 Slew rate slow fast 010 011 100 101 111 Test conditions 15 pF Cload on pad Typ Max 7.17/7.55 Unit ns 7.13/7.52 slow 3.14/3.31 fast 2.66/3.04 slow 2.56/2.51 fast 1.97/2.20 slow 3.08/3.02 fast 2.59/2.58 slow 2.56/2.42 fast 1.84/1.96 slow 1.82/1.67 fast 1.13/1.24 1. Max condition: wcs model, 0.9 V vddi, 1.62 V ovdd, and 125 °C. Input transition time is 120 ps. Slow slew rate means SIUL2_MSCRn[SRE] = ‘00’, fast slew rate means SIUL2_MSCRn[SRE] = ‘11’ S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 15 General purpose I/O parameters Table 8. GPIO rise/fall times (2.5 V range) Parameter Symbol IO output tpr transition time, rise/fall1 Drive strength SIUL2_MSCRn[D SE] 001 Slew rate slow fast 010 011 100 101 111 Test conditions Typ 15 pF Cload on pad Max 7.41/8.22 Unit ns 7.36/8.16 slow 3.30/3.74 fast 2.76/3.38 slow 3.44/3.04 fast 2.75/2.55 slow 4.05/3.54 fast 3.56/2.97 slow 3.39/2.93 fast 2.72/2.47 slow 2.31/2.03 fast 1.80/1.75 1. Max condition for tpr: wcs model, 0.9 V vddi, 2.25 V ovdd, and 125 °C. Input transition time is 125 ps. Slow slew rate means SIUL2_MSCRn[SRE] = ‘00’, fast slew rate means SIUL2_MSCRn[SRE] = ‘11’ Table 9. GPIO rise/fall times (3.3 V range) Parameter IO output tpr transition time, rise/fall1 Symbol Drive strength SIUL2_MSCRn[D SE] 001 Slew rate slow fast 010 011 100 101 111 Test conditions 15 pF Cload on pad Typ Max 7.75/8.45 Unit ns 7.65/8.39 slow 3.49/3.89 fast 2.84/3.52 slow 3.47/3.16 fast 2.90/2.73 slow 4.09/3.58 fast 3.73/3.07 slow 3.29/3.00 fast 2.68/2.37 slow 2.23/2.18 fast 1.47/1.57 1. Max condition for tpr: wcs model, 0.9 V vddi, 2.97 V ovdd, and 125 °C. Input transition time is 120 ps. slow slew rate means SIUL2_MSCRn[SRE] = ‘00’, fast slew rate means SIUL2_MSCRn[SRE] = ‘11’ S32V234 Data Sheet, Rev. 9, 03/2020 16 NXP Semiconductors General purpose I/O parameters NOTE The maximum rise time for all GPIO pins is 1 ms. Input pins do not support hysteresis, therefore very slow ramps (like the ones generated by an RC circuit with a large RC value) can induce bounces in the input read state during the transition from logic low to logic high or vice versa. 5.1.2 DC electrical specifications Table 10. DC electrical specifications Symbol Parameter Test conditions Min Typ Max Unit Voh High-level output voltage Ioh=-100 μA ovdd1-0.15 — — V Vol Low-level output voltage Iol=100 μA — — 0.15 V Vihf High-Level DC input voltage — 0.7*ovdd — ovdd V Vil Low-Level DC input voltage — 0 — 0.2*ovdd V Iin2 Input current (no pull-up/down) Vin = ovdd or 0 — — 8 μA Iin_33pu2 Input current (33 kilohm PU) — — 220 μA Vin = 0 Vin = ovdd Iin_50pu2 Input current (50 kilohm PU) Vin = 0 6 — — 150 Vin = ovdd Iin_100pu2 Input current (100 kilohm PU) Vin = 0 6 — — 60 Vin = ovdd Iin_100pd2 Input current (100 kilohm PD) Vin = 0 μA μA 6 — — 8 Vin = ovdd μA 50 1. ovdd is the IO supply for the pads. 2. Max condition: bcs model, 3.6 V, and 125 °C. These values are for I/O buffers. NOTE After bootup, application software should switch to manual voltage detect mode using VSEL_x settings of SRC_GPR14 register to ensure optimum performance of the GPIO pads. Please refer to SRC chapter in the Reference Manual for the register details. Table 11. Current-draw Characteristics for DDR_VREF Symbol DDR_VREF Parameter Current-draw characteristics for DDR_VREF Min — Max 1 Unit mA S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 17 General purpose I/O parameters 5.2 DDR pads 5.2.1 DDR3 mode 5.2.1.1 DDR3 mode DC electrical specifications Table 12. DDR3 mode DC electrical specifications Parameter Symbol Test conditions Min Typ Max Unit High-level output voltage Voh Ioh=-100 μA 0.8*ovdd — — V Low-level output voltage Vol Iol=100 μA — — 0.2*ovdd V High-level DC input voltage Vih (DC) — Vref + 0.2 — ovdd V High-level DC input voltage Vil (DC) — ovss — Vref - 0.2 V Input reference voltage Vref — 0.49*ovdd 0.5*ovdd 0.51*ovdd V Vtt2 — — 0.5*ovdd — V Iin Vi = 0 or ovdd — — 5 μA Pullup/pulldown impedance mismatch MMpupd 34 Ohm full strength driver -10 — +10 % Driver 240 Ohm unit calibration resolution Rres — — — 10 Ω Rkeep4 Pad keeper resistance — 20 — 50 kΩ Termination Input current (no voltage1 pullup/pulldown)3 1. Vtt is expected to track ovdd/2. 2. Vtt is not applied directly to the device. Minimum and Maximum values are system dependant. 3. Typ condition: typ model, 1.5V, and 25 °C. Max condition: bcs model, 1.575V, and -40 °C. Min condition: wcs model, 1.425V, and 125 °C. 4. Typ condition: typ model, 1.5 V, and 25 °C, max condition: wcs model, 1.425 V, and 125 °C, min condition: bcs model, 1.575 V, and -40 °C. 5.2.2 DDR3L mode 5.2.2.1 DDR3L mode DC electrical specifications Table 13. DDR3L mode DC electrical specifications Parameter Symbol Test conditions Min Typ Max Unit High-level output voltage Voh Ioh = -100 μA 0.8*ovdd — — V Low-level output voltage Vol Iol = 100 μA — — 0.2*ovdd V High-level DC input voltage Vih (DC) — Vref + 0.2 — ovdd V Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 18 NXP Semiconductors LPDDR2 mode Table 13. DDR3L mode DC electrical specifications (continued) Parameter Symbol Test conditions Min Typ Max Unit High-level DC input voltage Vil (DC) — ovss — Vref - 0.2 V Input reference voltage Vref — 0.49*ovdd 0.5*ovdd 0.51*ovdd V Vref current draw Icc-vref — — — 1 mA Termination voltage Vtt1 — — 0.5*ovdd — V Input current (no pullup/pulldown) Iin Vi = 0 or ovdd — — 5 μA Pullup/pulldown impedance mismatch (full strength driver) MMpupd — -10 — +10 % Driver unit (240 Ohm) calibration resolution Rres — — — 10 Ω Rkeep Pad keeper resistance — 20 — 50 kΩ Max Unit 1. Vtt is not applied directly to the device. Minimum and Maximum values are system dependant. 5.2.3 LPDDR2 mode 5.2.3.1 LPDDR2 mode DC electrical specifications Table 14. LPDDR2 mode DC electrical specifications Parameter Symbol Test conditions Min Typ High-level output voltage Voh Ioh = -100 μA 0.9*ovdd — — V Low-level output voltage Vol Iol = 100 μA — — 0.1*ovdd V Input reference voltage Vref — 0.49*ovdd 0.5*ovdd 0.51*ovdd V High-level DC input voltage Vih (DC) — Vref + 0.17 — ovdd V High-level DC input voltage Vil (DC) — ovss — Vref - 0.17 V Input current (no pullup/ pulldown)1 Iin Vi = ovdd or 0 — — 5 μA Pullup/pulldown impedance mismatch MMpupd 34 Ohm full strength driver -15 — +15 % Driver 240 Ohm unit calibration resolution Rres — — — 10 Ω Rkeep2 Pad keeper resistance — 20 — 50 kΩ 1. Typ condition: typ model, 1.2 V, and 25 °C. Max condition: bcs model, 1.32 V, and -40 °C. Min condition: wcs model, 1.14 V, and 125 °C. 2. Typ condition: typ model, 1.2 V, and 25 °C, max condition: wcs model, 1.14 V, and 125 °C, min condition: bcs model, 1.32 V, and -40 °C. S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 19 Peripheral operating requirements and behaviors 5.3 Boot Configuration Pins Specification Value driven on RCON and BOOTMOD pins should be stable for at least 1 µs after RESET pin is deasserted. NOTE External pull up/down resistors must be used on the BOOTMOD pins in order to ensure latching at the correct state. NOTE NXP would anticipate that most customers would use the boot from fuses option in a production environment. However, there is no reliability impact if the device is configured by RCON rather than fuses. 6 Peripheral operating requirements and behaviors 6.1 Analog modules 6.1.1 ADC electrical specifications The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter. S32V234 Data Sheet, Rev. 9, 03/2020 20 NXP Semiconductors Analog modules Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB ideal = (VrefH-VrefL)/4096 = 1.8V/4096 = . 439mV Total Unadjusted Error TUE = +/-10 LSB = +/-4.39 mV (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 1 LSB (ideal) 0 1 2 3 Offset Error OSE 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Figure 2. ADC characteristics and error definitions NOTE While measuring scaled supply voltages on ADC Channels, Maximum (+5/-10%) variation can be expected . S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 21 Analog modules 6.1.1.1 Input equivalent circuit EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CS CP2 RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 3. Input equivalent circuit Table 15. ADC conversion characteristics Symbol Parameter Conditions fCK ADC Input Clock frequency (Bus clock) fAD_clk ADC Conversion clock frequency1 fs Sampling frequency tsample Sample — Min 20 Typ — 20 — time2 time3 Max Unit 80 MHz 40 MHz — — 0.5 MHz 500 — — ns tconv Conversion 1400 — — ns CS ADC input sampling capacitance — — — 5 pF CP1 ADC input pin capacitance 1 — — — 5 pF CP2 ADC input pin capacitance 2 — — — 0.8 pF RSW1 Internal resistance of analog source — — — 875 Ω RAD Internal resistance of analog source — — — 825 Ω INL4 Integral non linearity — –3 — 3 LSB DNL Differential non linearity — –2 — 2 LSB OFS Offset error — –6 — 6 LSB GNE Gain error — –6 — 6 LSB Input (single ADC Max leakage channel) 125C — — 2000 nA TUE — –8 — 8 LSB Total unadjusted error S32V234 Data Sheet, Rev. 9, 03/2020 22 NXP Semiconductors Clocks and PLL interfaces modules 1. Please see description of Clock & reset section in ADC chapter in Reference Manual for details. User need to generate AD_clk = 40 MHz for 0.5 MSPS operation. For example, if fck = 80 MHz, configure MCR[8].ADCLKSE = 0 and MCR[4].ADCLKDIV = 0 (default). 2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. For internal ADC channels, the minimum sampling time required is 3 microsecond. 3. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 4. Specifications are quoted here for input signal ranging from 150 mV to VDD_HV_ADC - 150 mV. For signals outside this range, the Specifications may degrade beyond limits specified in this table. 6.1.2 Thermal Monitoring Unit (TMU) The following table describes TMU electrical characteristics. Table 16. TMU electrical characteristics Symbol Parameter Conditions Value Min Unit Typ Max Tj Temperature monitoring range — -40 — 125 °C TSENS Sensitivity — — 2.5 — mV/°C TACC Accuracy TJ = -40 °C to 40 °C -10 — +10 °C TJ = 40 °C to 125 °C -6 — +6 °C 6.2 Clocks and PLL interfaces modules 6.2.1 Main oscillator electrical characteristics The device provides an oscillator/resonator driver of a Pierce-type structure. Table 17. Main oscillator electrical characteristics Symbol Parameter Conditions Value Min fFXOSCHS Oscillator frequency — — Unit Typ Max 40.0 n/a MHz ms TFXOSCHSSU Oscillator start-up time fFXOSCHS = 40 MHz — — 21 VIH Input high level CMOS Schmitt Trigger Vref = 0.5*VDD_HV_FXOSC where VDD_HV_FXOSC is FXOSC HV Supply Vref+0.5 — VDD_HV_FXOS V C VIL Input low level CMOS Schmitt Trigger Vref = 0.5*VDD_HV_FXOSC where VDD_HV_FXOSC is FXOSC HV Supply 0 — Vref – 0.5 V S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 23 Clocks and PLL interfaces modules 1. The start-up time is dependent upon crystal characteristics, board leakage, etc, high ESR and excessive capacitive loads can cause long start-up time Following crystals are used in internal crystal oscillator validation: • NX3225 – 40 MHz; Load capacitance = 8 pF • NX5032 – 40 MHz; Load capacitance = 8 pF 6.2.2 48 MHz FIRC electrical characteristics Table 18. FIRC electrical specifications Symbol Parameter Conditions Value Min FTarget FIRC target frequency (trimmed) — δFvar_T FIRC frequency — variation with respect to supply and temperature after process trimming Unit Typ Max — 48 — MHz -10 — +10 % 6.2.3 PLL electrical specifications Table 19. PLL electrical characteristics 1 Symbol Parameter Conditions Value Min fPLLIN PLL input clock2 — 203 — Unit Typ Max — 403 MHz 40 — 60 % ΔPLLIN PLL input clock duty cycle tPLLLOCK PLL lock time — — — 100 µs ΔPLLT Period jitter — — — 150 ps ΔPLLTIE TIE — — — 560 ps fPLLMOD SSCG modulation frequency — — — 32 kHz — 2.74 % δPLLMOD 2 SSCG modulation depth (Down — Spread) 0.50 1. The jitter values are gauranteed for following conditions: 1. Measurement being done on LFAST TX pad with observed frequency greater than 250 M and less than 320 M 2. Minimum SOC activity - Operations required to observe clock must be functional. 3. Maximum frequency change in SSCG modulation is limited by following relation: Modulation Depth * VCO Frequency < PLL Reference (PFD) Frequency 2. PLL0IN clock retrieved from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode. 3. The PLLIN clock is the frequency after the PREDIV(Pre-divider) value division, and before the Phase detector block. Please refer to the PLLs section of clocking chapter in the Reference Manual. S32V234 Data Sheet, Rev. 9, 03/2020 24 NXP Semiconductors Clocks and PLL interfaces modules 4. STEPSIZE x STEPNO < 18432 For the PLL frequencies supported by this device, refer to the Table - "PLL frequencies" in the "Clocking" chapter of the Reference Manual. 6.2.4 DFS electrical specifications DFS takes input clock from PLL output. Here is relation between input and output clock of each phase divider: F(dfsclkout) = F(dfsclkin)/[mfi+(mfn/256)] mfi : integer part of division [1:255] mfn: Fractional part of division [1:255] Table 20. DFS electrical specification1 Parameter Min Typical Max Unit Input Frequency 800 — 1066 MHz Period jitter — — 300 ps TIE — — 600 ps 1. DFSes mfi, mfn and frequencies are defined and restricted as per Reference Manual. See the table "DFS (mfi, mfn) settings" in the "Clocking" chapter of the Reference Manual for the supported mfi and mfn combinations. 6.2.5 LFAST PLL Electrical Specifications The following table lists AC specification of the LFAST PLL block. Table 21. LFAST PLL Interface AC Specifications Parameter Min Typical Max Unit PLL input clock 10 — 26 MHz PLL VCO Frequency 312 — 320 MHz Phase Lock time — — 50 µs RMS Period Jitter — — 401 ps Jitter2 — 84 — ps — 80 — ps 1.09 1.313 ns Long Term Random Jitter Deterministic Jitter Total Jitter @ BER 10-9 — 1. When SysClk = 26 MHz 2. VCO clock measured over 100 µs acquisition at ZipWire TX LVDS across 100 ohm load 3. Only Total Jitter is given a maximum specification as variation of Random and Deterministic jitter is not critical. Any combined Random and Deterministic jitter yielding a Total Jitter @ 10-9 BER is within maximum specification and is acceptable S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 25 Memory interfaces 6.3 Memory interfaces 6.3.1 QuadSPI AC specifications • Measurements are with a load of 35 pF on output pins. Input slew: 1 ns, SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11 • QuadSPI input timing is with 15 pF load on flash output. • QuadSPI_MCR[DQS_EN] must be set as 1 for SDR READ NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. The following table lists various QuadSPI modes and their corresponding configurations. Please refer to the device Reference Manual for register and bit descriptions. Table 22. QuadSPI read/write settings Modes supported by QuadSPI QuadSPI_ QuadSPI_ MCR[DDR MCR[DQS _EN] _EN] SDR mode Internal 0 DQS mode 1 DDR mode Internal 1 DQS mode 1 External 1 DQS mode (supported by HyperFlas h) 1 QuadS PI_MC R [DQS_ CD] 000 000 000 Quad QuadSP SPI_M I_MCR CR [DQS_M [REF DSL] CLK_ SEL] 1 0 0 1 1 0 QuadSPI_SO CCR [FDCC_FB] QuadSPI_SO CCR [FDCC_FA] 39h @ 3.3 V 39h @ 3.3 V 3Fh @ 1.8 V 3Fh @ 1.8 V 4Ah @ 3.3 V 4Ah @ 3.3 V 50h @ 1.8 V 50h @ 1.8 V 00h 00h QuadSPI_ FLSHCR[ TDH] 00 01 01 SDR mode For SDR mode, QuadSPI_MCR[DQS_EN] must be set as '1'. S32V234 Data Sheet, Rev. 9, 03/2020 26 NXP Semiconductors Memory interfaces 1 2 3 Clock Tck SCK CS Tis Tih Data in Figure 4. QuadSPI input timing (SDR mode) diagram NOTE • A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. • All board delays need to be added appropriately • Input hold time being negative does not have any implication or max achievable frequency Table 23. QuadSPI input timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tis Setup time for incoming data 2.5 — ns Tih Hold time for incoming data 1 — ns FSCK SCK clock frequency — 104 MHz S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 27 Memory interfaces 1 2 3 Clock Tck SCK Tcsh Tcss CS Toh Tov Data out Figure 5. QuadSPI output timing (SDR mode) diagram Table 24. QuadSPI output timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tov Output Data Valid — 1.5 ns Toh Output Data Hold –1.5 — ns FSCK SCK clock frequency — 104 MHz Tcss Chip select output setup time 2 — ns Tcsh Chip select output hold time 1 — ns NOTE For any frequency setup and hold specifications of the memory should be met. DDR mode 1 2 3 Clock Tck SCK CS Tis Tih Data in Figure 6. QuadSPI input timing (DDR mode) diagram S32V234 Data Sheet, Rev. 9, 03/2020 28 NXP Semiconductors Memory interfaces Table 25. QuadSPI input timing (DDR mode) specifications Symbol Parameter Value Unit Min Tis Setup time for incoming data Tih Hold time for incoming data FSCK SCK Clock Frequency Configuration Max 2.5 @ 3.3 V — ns — — ns — 2 @ 1.8 V 1.5 — 50 (Internal DQS) MHz @ 3.3 V See Table 22 56 (Internal DQS) @ 1.8 V 1 2 3 Clock Tck SCK CS Tov Toh Data out Figure 7. QuadSPI output timing (DDR mode) diagram Table 26. QuadSPI output timing (DDR mode) specifications Symbol Parameter Value Min Unit Max Tov Output Data Valid — Toh Output Data Hold 1/(4*FSCK) — - 1.5 1/(4*FSCK) + 1.5 ns ns HyperFlash mode Maximum clock frequency = 100 MHz. S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 29 Memory interfaces RDS TsMIN ThMIN DI[7:0] Figure 8. QuadSPI input timing (HyperFlash mode) diagram Table 27. QuadSPI input timing (HyperFlash mode) specifications Symbol Parameter Value Min Unit Max TsMIN Setup time for incoming data 0.950 — ns ThMIN Hold time for incoming data 0.950 — ns CK CK 2 Tclk SKMAX Tclk SKMIN THO TDVO Output Invalid Data Figure 9. QuadSPI output timing (HyperFlash mode) diagram Table 28. QuadSPI output timing (HyperFlash mode) specifications Symbol Parameter Value Min Unit Max TdvMAX Output Data Valid — 3.7 ns Tho Output Data Hold 1 — ns Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 30 NXP Semiconductors Memory interfaces Table 28. QuadSPI output timing (HyperFlash mode) specifications (continued) Symbol Parameter Value Min Unit Max TclkSKMAX Ck to Ck2 skew max — T/4 + 0.150 ns TclkSKMIN Ck to Ck2 skew min T/4 – 0.150 — ns 6.4 DDR SDRAM Specific Parameters (DDR3, DDR3L, and LPDDR2) 6.4.1 DDR3 and DDR3L timing parameters NOTE Operating voltages of DDR3 and DDR3L are different. S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 31 Memory interfaces Figure 10. DDR3 and DDR3L command and address timing parameters NOTE RESET pin has an external weak pull DOWN requirement if DDR3 memory is NOT required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on. NOTE RESET pin has an external weak pull UP requirement if DDR3 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on. NOTE CKE pin has an external weak pull down requirement. S32V234 Data Sheet, Rev. 9, 03/2020 32 NXP Semiconductors Memory interfaces NOTE DDR3 and DDR3L timing parameters are compliant with JESD79-3F and JESD79-3-1A.01 specifications respectively. Table 29. DDR3 and DDR3L timing parameter ID Parameter Symbol CK = 533 MHz Unit Min Max DDR1 CK clock high-level width tCH 0.47 0.53 tCK (avg) DDR2 CK clock low-level width tCL 0.47 0.53 tCK (avg) DDR4 CS, RAS, CAS, CKE, WE, ODT setup time tIS 280 — ps DDR5 CS, RAS, CAS, CKE, WE, ODT hold time tIH 300 — ps DDR6 Address output setup time tIS 280 — ps DDR7 Address output hold time tIH 300 — ps NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF. S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 33 Memory interfaces 6.4.2 DDR3 and DDR3L read cycle Figure 11. DDR3 and DDR3L read cycle Table 30. DDR3 and DDR3L read cycle ID DDR26 Parameter Minimum required DQ valid window width Symbol — CK = 533 MHz Unit Min Max 563 — ps NOTE To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle of DQ window. NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF S32V234 Data Sheet, Rev. 9, 03/2020 34 NXP Semiconductors Memory interfaces 6.4.3 DDR3 and DDR3L write cycle Figure 12. DDR3 and DDR3L write cycle Table 31. DDR3 and DDR3L write cycle ID Parameter Symbol CK = 533 MHz Min Max Unit DDR17 DQ and DQM setup time to DQS (differential strobe) tDS 206 — ps DDR18 DQ and DQM hold time to DQS (differential strobe) tDH 280 — ps DDR21 DQS latching rising transitions to associated clock edges tDQSS -0.25 +0.25 tCK (avg) DDR22 DQS high level width tDQSH 0.45 0.55 tCK (avg) DDR22 DQS low level width tDQSL 0.45 0.55 tCK (avg) NOTE To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window. NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF. S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 35 Memory interfaces 6.4.4 LPDDR2 timing parameter Figure 13. LPDDR2 command and address timing parameter NOTE RESET pin has a external weak pull DOWN requirement if LPDDR2 memory is NOT required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on. NOTE RESET pin has a external weak pull UP requirement if LPDDR2 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on. NOTE CKE pin has a external weak pull down requirement. NOTE LPDDR2 timing parameters are compliant with JESD209-2B specification. Table 32. LPDDR2 timing parameter ID Parameter Symbol CK = 533 MHz Unit Min Max LP1 SDRAM clock high-level width tCH (avg) 0.45 0.55 tCK (avg) LP2 SDRAM clock LOW-level width tCL (avg) 0.45 0.55 tCK (avg) LP3 CS, CKE setup time tIS 235 — ps LP4 CS, CKE hold time tIH 250 — ps LP3 CA setup time tIS 235 — ps LP4 CA hold time tIH 250 — ps S32V234 Data Sheet, Rev. 9, 03/2020 36 NXP Semiconductors Memory interfaces NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF. 6.4.5 LPDDR2 read cycle Figure 14. LPDDR2 read cycle Table 33. LPDDR2 read cycle ID Parameter LP26 Minimum required DQ valid window width for LPDDR2 Symbol — CK = 533 MHz Unit Min Max 364 — ps NOTE To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle of DQ window. NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 37 Memory interfaces 6.4.6 LPDDR2 write cycle Figure 15. LPDDR2 write cycle Table 34. LPDDR2 write cycle ID Parameter Symbol CK = 533 MHz Unit Min Max LP17 DQ and DQM setup time to DQS (differential strobe) tDS 280 — ps LP18 DQ and DQM hold time to DQS (differential strobe) tDH 220 — ps LP21 DQS latching rising transitions to associated clock edges tDQSS 0.75 1.25 tCK (avg) LP22 DQS high level width tDQSH 0.4 — tCK (avg) LP23 DQS low level width tDQSL 0.4 — tCK (avg) NOTE To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window. NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF. S32V234 Data Sheet, Rev. 9, 03/2020 38 NXP Semiconductors Communication modules 6.5 Communication modules 6.5.1 DSPI timing Measurements are with a load of 45 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. Table 35. DSPI timing No. 1 Symbol tSCK Parameter DSPI cycle time Conditions PCS to SCK delay Unit - 40 - 16 - - 163 - ns - ns Slave Receive Only tCSC Max 401 Master (MTFE = 0) Slave (MTFE = 0) 2 Min Mode2 ns 3 tASC After SCK delay - 164 4 tSDC SCK duty cycle - tSCK/2 - 1.5 tSCK/2 + 1.5 ns 5 tA Slave access time SS active to SOUT valid - 40 ns 6 tDIS Slave SOUT disable time SS inactive to SOUT High-Z or invalid - 15 ns 7 tPCSC PCSx to PCSS time - 13 - ns 8 tPASC PCSS to PCSx time - 13 - ns 9 tSUI Data setup time for inputs Master (MTFE = 0) 15 - ns Slave 2 - Master (MTFE = 1, CPHA = 0) 6 - Master (MTFE = 1, CPHA = 1) 20 - Master (MTFE = 0) -4 - Slave 4 - 10 11 12 tHI tSUO tHO Data hold time for inputs Data valid (after SCK edge) Data hold time for outputs Master (MTFE = 1, CPHA = 0) 11 - Master (MTFE = 1, CPHA = 1) -4 - Master (MTFE = 0) - 4 Slave - 16 Master (MTFE = 1, CPHA = 0) - 12 Master (MTFE = 1, CPHA = 1) - 4 Master (MTFE = 0) -2 - Slave 3 - Master (MTFE = 1, CPHA = 0) 5 - Master (MTFE = 1, CPHA = 1) -2 - ns ns ns S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 39 Communication modules 1. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3. 2. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on SIN, but no valid data is transmitted on SOUT. 3. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler" configuration is "3" (01h) and SPI_CTARn[CSSCK] - "PCS to SCK Delay Scaler" configuration is "2" (0000h). 4. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PASC] - "After SCK Delay Prescaler" configuration is "3" (01h) and SPI_CTARn[ASC] - "After SCK Delay Scaler" configuration is "2" (0000h). NOTE DSPI Timing specs on this chip are valid with Slave in Classic Mode only. 2 3 PCSx 1 4 SCK Output (CPOL=0) 4 SCK Output (CPOL =1) 9 SIN 10 First Data Data 12 SOUT First Data Last Data 11 Data Last Data Figure 16. DSPI classic SPI timing — master, CPHA = 0 S32V234 Data Sheet, Rev. 9, 03/2020 40 NXP Semiconductors Communication modules PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL =1) 9 Data First Data SIN Last Data 12 SOUT First Data 11 Data Last Data Figure 17. DSPI classic SPI timing — master, CPHA = 1 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 12 11 Data Last Data Data Last Data 6 10 First Data Figure 18. DSPI classic SPI timing — slave, CPHA = 0 S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 41 Communication modules SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Figure 19. DSPI classic SPI timing — slave, CPHA = 1 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Figure 20. DSPI modified transfer format timing — master, CPHA = 0 S32V234 Data Sheet, Rev. 9, 03/2020 42 NXP Semiconductors Communication modules PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Data 12 First Data SOUT Data Last Data 11 Last Data Figure 21. DSPI modified transfer format timing — master, CPHA = 1 7 8 PCSS PCSx Figure 22. DSPI PCS strobe (PCSS) timing 6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) Booting from eMMC must be at voltage of 3.3 V. The operation at 1.8 V is possible only during run-time, that is after the boot has completed. This voltage restriction during booting does not apply to SD/SDIO/SDHC/SDXC modes. Measurements are with a load of 40 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11. uSDHC_VEND_SPEC[CMD_OE_PRE_EN] field should be programmed to 1 for proper functioning of uSDHC external interface. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 43 Communication modules 6.5.2.1 SDR mode timing specifications Figure 23. SDR CMD-DATx Read Timing Figure 24. SDR CMD-DATx Write Timing Table 36. SDR mode timing specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 SD2 Clock Frequency (Low Speed) fPP1 0 400 kHz Clock Frequency (SD/ SDIO Full Speed/High Speed) fPP2 0 25/50 MHz Clock Frequency (MMC Full Speed/High Speed) fPP3 0 20/52 MHz Clock Frequency (Identification Mode) fOD 100 400 kHz Clock Duty Cycle tDC 45 55 % eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) Table continues on the next page... S32V234 Data Sheet, Rev. 9, 03/2020 44 NXP Semiconductors Communication modules Table 36. SDR mode timing specification (continued) ID Parameter Symbols Min Max Unit SD3 CLK to Data/CMD Valid tDVO — 3.2 ns SD4 CLK to Data/CMD Invalid tHO -6.3 — ns eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) SD5 DATA/CMD Input Setup time tSUI 4.5 — ns SD6 DATA/CMD Input Hold time tHI 0 — ns 1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode, clock frequency can be any value between 0–50 MHz. 3. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock frequency can be any value between 0–52 MHz. 6.5.2.2 DDR mode timing specifications Figure 25. DDR Data Read timing S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 45 Communication modules Figure 26. DDR DATA Write timing Figure 27. DDR CMD Read Timing Figure 28. DDR CMD Write Timing S32V234 Data Sheet, Rev. 9, 03/2020 46 NXP Semiconductors Communication modules Table 37. DDR mode timing specification ID Parameter Symbols Min Max Unit Card Input Clock DD1 Clock Frequency (eMMC4.4 DDR) fPP 0 52 MHz DD1 Clock Frequency (SD3.0 DDR) fPP 0 50 MHz DD2 Clock Duty Cycle tDC 45 55 % uSDHC Output/Card Inputs CMD, DAT (Reference to CLK) DD3 CLK to Data Valid tDVO — 6.2 ns DD4 CLK to Data Invalid tHO 2.5 — ns DD5 CLK to CMD Valid tDVO — 3.25 ns DD6 CLK to CMD Invalid tHO –6.2 — ns uSDHC Input/Card Outputs CMD, DAT (Reference to CLK) DD7 Data Input Setup Time tSUI 2.3 — ns DD8 Data Input Hold Time tHI 1.5 — ns DD9 CMD Input Setup Time tSUI 4.5 — ns DD10 CMD Input Hold Time tHI 0 — ns S32V234 Data Sheet, Rev. 9, 03/2020 NXP Semiconductors 47 LFAST electrical characteristics 6.5.3 LFAST electrical characteristics 6.5.3.1 LFAST interface timing diagrams Figure 29. LFAST timing definition S32V234 Data Sheet, Rev. 9, 03/2020 48 NXP Semiconductors LFAST electrical characteristics VIH Differential TX Data Lines 90% 10% pad_p/pad_n VIL Tfall Trise Figure 30. Rise/fall time 6.5.3.2 LFAST Interface electrical characteristics Table 38. LFAST electrical characteristics Symbol Parameter Value1 Conditions Min VDDIO_LFAST Unit Typ Max Operating supply conditions — 1.71 — 1.95 V Data rate — — 312/320 Typ+0.1% Mbps Bias startup time2 — — 0.5 3 µs VOS_DRF Common mode voltage — 1.1 1.2 1.475 V |ΔVOD_DRF| Differential output voltage swing (terminated) — 250 350 450 mV TTR_DRF Rise/Fall time (20% - 80% of swing)3 — 0.1 — 0.73 ns COUT_DRF Capacitance4 — — — 5 pF VICOM_DRF Common mode voltage — 0.155 — 1.56 V |ΔVI_DRF| Differential input voltage VICOM_DRF>1.4 V 150 — — mV VICOM_DRF