HEF4014BP,652

HEF4014B 8-bit static shift register Rev. 11 — 24 November 2021 Product data sheet 1. General description The HEF4014B is an 8-bit shift register with synchronous parallel enable. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C 3. Applications • • • Parallel-to-serial converter Serial data queueing General purpose register 4. Ordering information Table 1. Ordering information Type number Package HEF4014BT Temperature range Name Description Version -40 °C to +85 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4014B Nexperia 8-bit static shift register 5. Functional diagram 7 6 5 4 13 14 15 1 D0 D1 D2 D3 D4 D5 D6 D7 9 PE 11 DS 0D CP 10 CP 1D 2D 3D 4D 5D 6D SHIFT REGISTER 8 BITS 7D Q5 Q6 Q7 2 12 3 001aae556 Fig. 1. Functional diagram PE D0 D5 D DS Q FF 0 CP D6 D Q D7 D FF 5 Q D FF 6 CP Q FF 7 CP CP CP Q5 Q6 Q7 001aae558 Fig. 2. Logic diagram HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 2 / 12 HEF4014B Nexperia 8-bit static shift register 6. Pinning information 6.1. Pinning HEF4014B D7 1 16 VDD Q5 2 15 D6 Q7 3 14 D5 D3 4 13 D4 D2 5 12 Q6 D1 6 11 DS D0 7 10 CP VSS 8 9 PE 001aae557 Fig. 3. Pin configuration SOT109-1 (SO16) 6.2. Pin description Table 2. Pin description Symbol Pin Description Q5 to Q7 2, 12, 3 output D0 to D7 7, 6, 5, 4, 13, 14, 15, 1 parallel data input VSS 8 ground supply voltage PE 9 parallel enable input CP 10 clock input (LOW-to-HIGH edge-triggered) DS 11 serial data input VDD 16 supply voltage HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 3 / 12 HEF4014B Nexperia 8-bit static shift register 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. Number of clock transitions Inputs Outputs CP DS PE Q5 Q6 Q7 1 ↑ 1D L X X X 2 ↑ 2D L X X X 3 ↑ 3D L X X X 6 ↑ X L 1D X X 7 ↑ X L 2D 1D X 8 ↑ X L 3D 2D 1D ↓ X X no change no change no change ↑ X H D5 D6 D7 ↓ X X no change no change no change Serial operation Parallel operation 1 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit -0.5 +18 V - ±10 mA VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current - ±10 mA II/O input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature -65 +150 °C Tamb ambient temperature -40 +85 °C Ptot total power dissipation Tamb = -40 °C to +85 °C - 500 mW P power dissipation per output - 100 mW Min Typ Max Unit VI < -0.5 V or VI > VDD + 0.5 V -0.5 VO < -0.5 V or VO > VDD + 0.5 V VDD + 0.5 V 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +85 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 4 / 12 HEF4014B Nexperia 8-bit static shift register 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current II input leakage current IDD supply current CI input capacitance HEF4014B Product data sheet Conditions |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 5V 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 mA VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 μA 5V - 20 - 20 - 150 μA 10 V - 40 - 40 - 300 μA 15 V - 80 - 80 - 600 μA - - - - 7.5 - - pF IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 5 / 12 HEF4014B Nexperia 8-bit static shift register 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C; VSS = 0 V. Symbol Parameter Conditions VDD Extrapolation formula [1] tPHL HIGH to LOW propagation delay CP to Qn; see Fig. 4 5V LOW to HIGH propagation delay CP to Qn; see Fig. 4 tPLH tt transition time tW pulse width tsu set-up time Qn output; see Fig. 4 PE to CP; see Fig. 5 Dn to CP; see Fig. 5 hold time PE to CP; see Fig. 5 DS to CP; see Fig. 5 Dn to CP; see Fig. 5 fclk(max) [1] [2] maximum clock frequency Typ Max Unit 103 ns + (0.55 ns/pF)CL - 130 260 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 88 ns + (0.55 ns/pF)CL - 115 230 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns [2] 10 ns + (1.00 ns/pF)CL - 60 120 ns 5V 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 70 35 - ns 30 15 - ns 24 12 - ns 5V 40 10 - ns 10 V 25 5 - ns 15 V 15 0 - ns 5V +35 -5 - ns 10 V +25 -5 - ns 5V CP input; minimum width; 10 V see Fig. 5 15 V DS to CP; see Fig. 5 th Min see Fig. 5 15 V 25 0 - ns 5V +35 -5 - ns 10 V +25 -5 - ns 15 V 25 0 - ns 5V +25 -5 - ns 10 V 20 0 - ns 15 V 15 0 - ns 5V 30 15 - ns 10 V 20 10 - ns 15 V 15 7 - ns 5V 30 15 - ns 10 V 20 10 - ns 15 V 15 7 - ns 5V 6 13 - MHz 10 V 15 30 - MHz 15 V 20 40 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). tt is the same as tTHL and tTLH. HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 6 / 12 HEF4014B Nexperia 8-bit static shift register Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation VDD Typical formula for PD (μW) Where: 5V PD = 900 × fi + ∑(fo × CL) × VDD 10 V PD = 4300 × fi + ∑(fo × CL) × VDD 15 V PD = 12000 × fi + ∑(fo × CL) × VDD 2 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; ∑(CL × fo) = sum of the outputs. 2 2 11.1. Waveforms and test circuit VI VM CP input VSS tPHL VOH Qn output 90 % VOL tPLH VM 10 % tt tt 001aaj456 Measurement points are given in Table 9. Fig. 4. CP to Qn propagation delays and output transition times VI 50 % CP input VSS tsu th 50 % 50 % tsu th 50 % 50 % 50 % tW VI D input VSS 50 % tr 50 % fclk(max) tf tsu VI PE input th 50 % VSS 50 % tsu th 50 % 50 % VI DS input VSS 001aae559 The shaded areas indicate where change is permitted for predictable output performance. Set-up and hold times are shown as positive values but may be specified as negative values. Measurement points are given in Table 9. Fig. 5. Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 7 / 12 HEF4014B Nexperia 8-bit static shift register VDD G VI VO DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig. 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4014B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 8 / 12 HEF4014B Nexperia 8-bit static shift register 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 9 / 12 HEF4014B Nexperia 8-bit static shift register 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4014B v.11 20211124 Product data sheet - HEF4014B v.10 Modifications: • HEF4014B v.10 20181017 - HEF4014B v.9 Modifications: • • Section 1 and Section 2 updated. Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. HEF4014B v.9 20160321 Modifications: • HEF4014B v.8 20111121 Modifications: • • HEF4014B v.7 20110914 Product data sheet - HEF4014B v.6 HEF4014B v.6 20091102 Product data sheet - HEF4014B v.5 HEF4014B v.5 20090624 Product data sheet - HEF4014B v.4 HEF4014B v.4 20090122 Product data sheet - HEF4014B_CNV v.3 HEF4014B_CNV v.3 19950101 Product specification - HEF4014B_CNV v.2 HEF4014B_CNV v.2 19950101 Product specification - - HEF4014B Product data sheet Product data sheet - HEF4014B v.8 Type number HEF4014BP (SOT38-4) removed. Product data sheet - HEF4014B v.7 Legal pages updated. Changes in "General description" and "Features and benefits". All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 10 / 12 HEF4014B Nexperia 8-bit static shift register 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 11 / 12 HEF4014B Nexperia 8-bit static shift register Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 4 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 7 12. Package outline.......................................................... 9 13. Abbreviations............................................................ 10 14. Revision history........................................................10 15. Legal information......................................................11 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 November 2021 HEF4014B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 12 / 12