HEF4052BP,652

HEF4052B Dual 4-channel analog multiplexer/demultiplexer Rev. 11 — 15 December 2021 Product data sheet 1. General description The HEF4052B is a dual single-pole quad-throw analog switch (2x SP4T) suitable for use in analog or digital 4:1 multiplexer/demultiplexer applications. Each switch features four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S1 and S2) are common to both switches. When E is HIGH, the switches are turned off. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Applications • • • Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4052BT -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4052BTT -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 5. Functional diagram VDD 16 13 12 14 S1 15 10 11 S2 9 LOGIC LEVEL CONVERSION 1 - OF - 4 DECODER 1 5 E 6 2 4 Fig. 1. 8 7 VSS VEE 3 1Z 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 2Z mnb042 Functional diagram nYn VDD VDD nZ VEE 001aak604 Fig. 2. Schematic diagram (one switch) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 2 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 10 9 13 1Z 0 3 G4 MDX 1Y1 14 9 S2 1Y2 15 1Y3 11 2 2Y0 1 3 2Y1 5 2Y2 2 2Y3 4 Logic symbol Product data sheet 12 4× S1 E 2Z 3 HEF4052B 1Y0 1 10 6 Fig. 3. 6 0 3 1 0 5 1 2 4 12 14 13 15 11 001aak605 mnb041 Fig. 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 3 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 1Z 1Y0 S1 LEVEL CONVERTER 1Y1 S2 LEVEL CONVERTER 1Y2 E LEVEL CONVERTER 1Y3 2Y0 2Y1 2Y2 2Y3 2Z 001aak634 Fig. 5. Logic diagram HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 4 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 6. Pinning information 6.1. Pinning HEF4052B 2Y0 1 16 VDD 2Y2 2 15 1Y2 2Z 3 14 1Y1 2Y3 4 13 1Z 2Y1 5 12 1Y0 E 6 11 1Y3 VEE 7 10 S1 VSS 8 9 HEF4052B S2 2Y0 1 16 VDD 2Y2 2 15 1Y2 2Z 3 14 1Y1 2Y3 4 13 1Z 2Y1 5 12 1Y0 E 6 11 1Y3 VEE 7 10 S1 VSS 8 9 001aak606 001aag215 Fig. 6. S2 Pin configuration SOT109-1 (SO16) Fig. 7. Pin configuration SOT403-1 (TSSOP16) 6.2. Pin description Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage VSS 8 ground supply voltage S1, S2 10, 9 select input 1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 12, 14, 15, 11, 1, 5, 2, 4 independent input or output 1Z, 2Z 13, 3 common output or input VDD 16 supply voltage 7. Function table Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Channel on E S2 S1 L L L nY0 to nZ L L H nY1 to nZ L H L nY2 to nZ L H H nY3 to nZ H X X switches off HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 5 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Min Max Unit VDD supply voltage -0.5 +18 V VEE supply voltage referenced to VDD -18 +0.5 V IIK input clamping current pins Sn and E; VI < -0.5 V, or VI > VDD + 0.5 V - ±10 mA VI input voltage -0.5 VDD + 0.5 II/O input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature -65 +150 °C Tamb ambient temperature -40 +125 °C Ptot total power dissipation Tamb = -40 °C to +125 °C - 500 mW P power dissipation per output - 100 mW [1] [2] Conditions [1] [2] V To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit see Fig. 8 3 - 15 V VDD supply voltage VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +125 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V 001aac285 15 VDD - VSS (V) 10 operating area 5 0 Fig. 8. 0 5 10 VDD - VEE (V) 15 Operating area as a function of the supply voltages HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 6 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 10. Static characteristics Table 6. Static characteristics VSS = VEE = 0 V; VI = VSS or VDD, unless otherwise specified. Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage II input leakage current IS(OFF) OFF-state leakage current IDD CI Conditions Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA Z port; 15 V all channels OFF; see Fig. 9 - - - 1000 - - - - nA Y port; per channel; see Fig. 10 15 V - - - 200 - - - - nA 5V - 5 - 5 - 150 - 150 μA 10 V - 10 - 10 - 300 - 300 μA 15 V - 20 - 20 - 600 - 600 μA - - - - 7.5 - - - - pF 5V |IO| < 1 μA |IO| < 1 μA supply current IO = 0 A input capacitance VDD Sn, E inputs 10.1. Test circuits VDD S1 and S2 VDD or VSS nZ nYn E IS VSS = VEE VDD VO VI 001aak635 Fig. 9. Test circuit for measuring OFF-state leakage current Z port HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 7 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer VDD VDD or VSS S1 and S2 nY0 1 nZ nYn 2 switch IS E VSS = VEE VSS VI VO 001aak636 Fig. 10. Test circuit for measuring OFF-state leakage current nYn port 10.2. On resistance Table 7. ON resistance Tamb = 25 °C; ISW = 200 μA; VSS = VEE = 0 V. Symbol Parameter Conditions VDD - VEE Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD - VEE; see Fig. 11 and Fig. 12 5V 350 2500 Ω 10 V 80 245 Ω 15 V 60 175 Ω 5V 115 340 Ω 10 V 50 160 Ω 15 V 40 115 Ω 5V 120 365 Ω 10 V 65 200 Ω 15 V 50 155 Ω 5V 25 - Ω 10 V 10 - Ω 15 V 5 - Ω RON(rail) ON resistance (rail) VI = 0 V; see Fig. 11 and Fig. 12 VI = VDD - VEE; see Fig. 11 and Fig. 12 ΔRON ON resistance mismatch between channels VI = 0 V to VDD - VEE; see Fig. 11 10.2.1. On resistance waveform and test circuit V VDD VDD or VSS VSW S1 and S2 nZ nYn E VSS = VEE VSS ISW VI 001aak637 RON = VSW / ISW. Fig. 11. Test circuit for measuring RON HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 8 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 001aae648 400 RON (Ω) VDD = 5 V 300 200 10 V 100 0 15 V 0 5 10 VI (V) 15 Fig. 12. Typical RON as a function of input voltage 11. Dynamic characteristics Table 8. Dynamic characteristics Tamb = 25 °C; VSS = VEE = 0 V; for test circuit see Fig. 16. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Fig. 13 Sn to nYn, nZ; see Fig. 14 tPLH LOW to HIGH propagation delay Yn, nZ to nZ, nYn; see Fig. 13 Sn to nYn, nZ; see Fig. 14 tPHZ tPZH tPLZ tPZL HIGH to OFF-state propagation delay OFF-state to HIGH propagation delay LOW to OFF-state propagation delay OFF-state to LOW propagation delay HEF4052B Product data sheet E to nYn, nZ; see Fig. 15 E to nYn, nZ; see Fig. 15 E to nYn, nZ; see Fig. 15 E to nYn, nZ; see Fig. 15 All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 VDD Typ Max 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 150 305 ns 10 V 65 135 ns 15 V 50 100 ns 5V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns 5V 150 300 ns 10 V 75 150 ns 15 V 50 100 ns 5V 95 190 ns 10 V 90 180 ns 15 V 85 180 ns 5V 130 260 ns 10 V 55 115 ns 15 V 45 85 ns 5V 100 205 ns 10 V 90 180 ns 15 V 90 180 ns 5V 120 240 ns 10 V 50 100 ns 15 V 35 75 ns © Unit Nexperia B.V. 2021. All rights reserved 9 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 11.1. Waveforms and test circuit VDD nYn or nZ input VM VDD Sn input VEE tPLH tPHL VO nZ or nYn output nYn or nZ output VM VEE VM VSS tPLH VO 90 % 10 % VEE switch OFF 001aac290 Measurement points are given in Table 9. tPHL switch ON switch OFF 001aac291 Measurement points are given in Table 9. Fig. 13. nYn, nZ to nZ, nYn propagation delays Fig. 14. Sn to nYn, nZ propagation delays VDD E input VM VSS tPLZ nYn or nZ output LOW-to-OFF OFF-to-LOW tPZL VO 90 % 10 % VEE tPHZ nYn or nZ output HIGH-to-OFF OFF-to-HIGH VO tPZH 90 % 10 % VEE switch ON switch OFF switch ON 001aac292 Measurement points are given in Table 9. Fig. 15. Enable and disable times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 10 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer VI negative pulse 0V tW 90 % VI positive pulse 0V 10 % VM 10 % VM tf tr tr tf 90 % VM VM tW VDD VDD VI PULSE GENERATOR VI DUT VO RT RL S1 open CL VSS VEE 001aaj903 Test data is given in Table 10. Definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including test jig and probe; RL = Load resistance. Fig. 16. Test circuit for measuring switching times Table 10. Test data Input nYn, nZ Sn and E Load tr, tf VDD or VEE VDD or VSS ≤ 20 ns [1] S1 position VM CL RL tPHL [1] tPLH 0.5VDD 50 pF 10 kΩ VDD or VEE VEE tPZH, tPHZ tPZL, tPLZ other VEE VDD VEE For nYn to nZ propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD. 11.2. Additional dynamic parameters Table 11. Additional dynamic characteristics VSS = VEE = 0 V; Tamb = 25 °C. Symbol Parameter Conditions THD total harmonic distortion see Fig. 17; RL = 10 kΩ; CL = 15 pF; channel ON; VI = 0.5VDD (p-p); fi = 1 kHz f(-3dB) -3 dB frequency response see Fig. 18; RL = 1 kΩ; CL = 5 pF; channel ON; VI = 0.5VDD (p-p) αiso isolation (OFF-state) see Fig. 19; fi = 1 MHz; RL = 1 kΩ; CL = 5 pF; channel OFF; VI = 0.5VDD (p-p) Vct crosstalk voltage digital inputs to switch; see Fig. 20; RL = 10 kΩ; CL = 15 pF; E or Sn = VDD (square-wave) Xtalk crosstalk between switches; see Fig. 21; fi = 1 MHz; RL = 1 kΩ; VI = 0.5VDD (p-p) [1] VDD Typ Max [1] 5 V 0.25 - % 10 V 0.04 - % 15 V 0.04 - % 13 - MHz 10 V 40 - MHz 15 V 70 - MHz [1] 10 V -50 - dB 10 V 50 - mV [1] 10 V -50 - dB [1] 5 V Unit fi is biased at 0.5 VDD; VI = 0.5VDD (p-p). HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 11 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer Table 12. Dynamic power dissipation PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (μW) where: 5V PD = 1300 × fi + Σ(fo × CL) × VDD 10 V PD = 6100 × fi + Σ(fo × CL) × VDD 15 V PD = 15600 × fi + Σ(fo × CL) × VDD 2 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(CL × fo) = sum of the outputs. 2 2 11.2.1. Test circuits VDD VDD VDD or VSS S1 and S2 nZ S1 and S2 VDD or VSS nYn nZ E VSS = VEE VSS nYn E RL D CL VSS = VEE VSS fi RL CL dB fi 001aak638 001aak639 Fig. 17. Test circuit for measuring total harmonic distortion Fig. 18. Test circuit for measuring frequency response VDD VDD or VSS S1 and S2 nY0 1 nZ nYn 2 switch E VSS = VEE VSS RL CL dB fi 001aak657 Fig. 19. Test circuit for measuring isolation (OFF-state) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 12 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 0.5VDD VDD RL G 0.5VDD S1 and S2 nY0 1 nZ nYn 2 RL switch E VSS = VEE VDD or VSS V CL VO 001aak658 a. Test circuit logic input (Sn, E) off on off VO Vct 001aaj908 b. Input and output pulse definitions Fig. 20. Test circuit for measuring crosstalk voltage between digital inputs and switch VDD VDD VDD or VSS S1 and S2 nY0 nZ nYn VDD or VSS S1 and S2 nY0 nZ nYn E E VSS = VEE VSS RL VO RL VSS = VEE VSS RL VI RL VO 001aak660 001aak659 a. Switch closed condition VI b. Switch open condition Fig. 21. Test circuit for measuring crosstalk between switches HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 13 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 22. Package outline SOT109-1 (SO16) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 14 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 23. Package outline SOT403-1 (TSSOP16) HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 15 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4052B v.11 20211215 Product data sheet - HEF4052B v.10 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Table 4: Derating values for Ptot total power dissipation updated. Table 13 updated. HEF4052B v.10 20160325 Modifications: • HEF4052B v.9 20140911 Modifications: • HEF4052B v.8 20111117 Modifications: • • HEF4052B v.7 20100326 Product data sheet - HEF4052B v.6 HEF4052B v.6 20100308 Product data sheet - HEF4052B v.5 HEF4052B v.5 20091127 Product data sheet - HEF4052B v.4 HEF4052B v.4 20090924 Product data sheet - HEF4052B_CNV v.3 HEF4052B_CNV v.3 19950101 Product specification - HEF4052B_CNV v.2 HEF4052B_CNV v.2 19950101 Product specification - - HEF4052B Product data sheet Product data sheet - HEF4052B v.9 Type number HEF4052BP (SOT38-4) removed. Product data sheet - HEF4052B v.8 - HEF4052B v.7 Fig. 20: Test circuit modified Product data sheet Legal pages updated. Changes in Section 1, Section 2, and Section 3. All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 16 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer 15. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 17 / 18 HEF4052B Nexperia Dual 4-channel analog multiplexer/demultiplexer Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................5 6.1. Pinning.........................................................................5 6.2. Pin description............................................................. 5 7. Function table............................................................... 5 8. Limiting values............................................................. 6 9. Recommended operating conditions..........................6 10. Static characteristics..................................................7 10.1. Test circuits................................................................7 10.2. On resistance............................................................ 8 10.2.1. On resistance waveform and test circuit................. 8 11. Dynamic characteristics.............................................9 11.1. Waveforms and test circuit.......................................10 11.2. Additional dynamic parameters................................11 11.2.1. Test circuits........................................................... 12 12. Package outline........................................................ 14 13. Abbreviations............................................................ 16 14. Revision history........................................................16 15. Legal information......................................................17 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 15 December 2021 HEF4052B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 15 December 2021 © Nexperia B.V. 2021. All rights reserved 18 / 18