HEF4094B_10

HEF4094B 8-stage shift-and-store register Rev. 08 — 2 April 2010 Product data sheet 1. General description The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading HEF4094B devices when the clock has a slow rise time. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range −40 °C to +125 °C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number HEF4094BP HEF4094BT HEF4094BTS Package Name DIP16 SO16 SSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm Version SOT38-4 SOT109-1 SOT338-1 NXP Semiconductors HEF4094B 8-stage shift-and-store register 4. Functional diagram 3 CP 1 STR QS1 QS2 2 3 D CP 8-STAGE SHIFT REGISTER QS2 QS1 STR 8-BIT STORAGE REGISTER 10 9 2 D QP3 1 QP4 QP5 15 OE QP6 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 4 5 6 7 14 13 12 11 001aaf119 9 10 4 5 6 7 14 13 12 11 QP0 QP1 QP2 QP7 OE 15 001aaf111 Fig 1. Functional diagram Fig 2. Logic symbol STAGE 0 D D CP FF 0 CP CP Q D STAGES 1 TO 6 Q STAGE 7 D CP FF 7 D LE LATCH Q QS2 Q QS1 D LE Q D LE Q LATCH 0 STR LATCH 7 OE QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 001aag799 Fig 3. Logic diagram HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 2 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 5. Pinning information 5.1 Pinning HEF4094B STR D CP QP0 QP1 QP2 QP3 VSS 1 2 3 4 5 6 7 8 001aae662 16 VDD 15 OE 14 QP4 13 QP5 12 QP6 11 QP7 10 QS2 9 QS1 Fig 4. Pin configuration 5.2 Pin description Table 2. Symbol STR D CP QP0 to QP7 VSS QS1 QS2 OE VDD Pin description Pin 1 2 3 4, 5, 6, 7, 14, 13, 12, 11 8 9 10 15 16 Description strobe input data input clock input parallel output ground supply voltage serial output serial output output enable input supply voltage HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 3 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 6. Functional description Table 3. Inputs CP ↑ ↓ ↑ ↑ ↑ ↓ [1] Function table[1] Parallel outputs OE L L H H H H STR X X L H H H D X X X L H H QP0 Z Z NC L H NC QPn Z Z NC QPn −1 QPn −1 NC Serial outputs QS1 Q6S NC Q6S Q6S Q6S NC QS2 NC Q7S NC NC NC Q7S At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition; Z = HIGH-impedance OFF-state; NC = no change; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition. CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q0S (FF 0) OUTPUT QP0 INTERNAL Q6S (FF 6) OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 001aaf117 Z-state Z-state Fig 5. Timing diagram HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 4 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot P [1] [2] Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation power dissipation Conditions VI < −0.5 V or VI > VDD + 0.5 V VO < −0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +125 750 500 100 Unit V mA V mA mA mA °C °C mW mW mW DIP16 SO16 per output [1] [2] - For DIP16 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K. For SO16 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Symbol VDD VI Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD = 10 V VDD = 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +125 3.75 0.5 0.08 Unit V V °C μs/V μs/V μs/V HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 5 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 μA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 μA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 μA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 μA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V IOZ OFF-state output current input leakage current supply current QPn output is HIGH; VO = 15 V 5V 5V 10 V 15 V 5V 10 V 15 V 15 V Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.64 −1.6 −4.2 0.64 1.6 4.2 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.4 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.5 −1.3 −3.4 0.5 1.3 3.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 0.4 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 12 Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 12 V V V V V V V V V V V V mA mA mA mA mA mA mA μA II IDD 15 V all valid input 5V combinations; 10 V IO = 0 A 15 V - ±0.1 5 10 20 - - ±0.1 5 10 20 7.5 - ±1.0 150 300 600 - - ±1.0 150 300 600 - μA μA μA μA pF CI input capacitance HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 6 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 10. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 10; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions CP to QS1; see Figure 6 VDD 5V 10 V 15 V CP to QS2; see Figure 6 5V 10 V 15 V CP to QPn; see Figure 6 5V 10 V 15 V STR to QPn; see Figure 7 5V 10 V 15 V tPLH LOW to HIGH propagation delay, CP to QS1; see Figure 6 5V 10 V 15 V CP to QS2; see Figure 6 5V 10 V 15 V CP to QPn; see Figure 6 5V 10 V 15 V STR to QPn; see Figure 7 5V 10 V 15 V tt transition time 5V 10 V 15 V tPZH OFF-state to HIGH propagation delay OE to QPn; see Figure 8 5V 10 V 15 V tPZL OFF-state to LOW propagation delay OE to QPn; see Figure 8 5V 10 V 15 V tPHZ HIGH to OFF-state propagation delay OE to QPn; see Figure 8 5V 10 V 15 V [1] [1] [1] Extrapolation formula 108 ns + (0.55 ns/pF) CL 54 ns + (0.23 ns/pF) CL 42 ns + (0.16 ns/pF) CL 78 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 138 ns + (0.55 ns/pF) CL 64 ns + (0.23 ns/pF) CL 47 ns + (0.16 ns/pF) CL 83 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 27 ns + (0.16 ns/pF) CL 78 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 78 ns + (0.55 ns/pF) CL 39 ns + (0.23 ns/pF) CL 32 ns + (0.16 ns/pF) CL 123 ns + (0.55 ns/pF) CL 59 ns + (0.23 ns/pF) CL 47 ns + (0.16 ns/pF) CL 73 ns + (0.55 ns/pF) CL 34 ns + (0.23 ns/pF) CL 27 ns + (0.16 ns/pF) CL 10 ns + (1.00 ns/pF) CL 9 ns + (0.42 ns/pF) CL 6 ns + (0.28 ns/pF) CL Min - Typ 135 65 50 105 50 40 165 75 55 110 50 35 105 50 40 105 50 40 150 70 55 100 45 35 60 30 20 40 25 20 40 25 20 75 40 30 Max 270 130 100 210 100 80 330 150 110 220 100 70 210 100 80 210 100 80 300 140 110 200 90 70 120 60 40 80 50 40 80 50 40 150 80 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 7 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 10; unless otherwise specified. Symbol tPLZ Parameter LOW to OFF-state propagation delay Conditions OE to QPn; see Figure 8 VDD 5V 10 V 15 V tsu set-up time D to CP; see Figure 9 5V 10 V 15 V th hold time D to CP; see Figure 9 5V 10 V 15 V tW pulse width minimum LOW 5 V clock pulse; 10 V see Figure 6 15 V minimum HIGH 5 V strobe pulse; 10 V see Figure 7 15 V fmax maximum frequency see Figure 6 5V 10 V 15 V [1] Extrapolation formula Min 60 20 15 +5 20 20 60 30 24 40 30 24 5 11 14 Typ 80 40 30 30 10 5 −15 5 5 30 15 12 20 15 12 10 22 28 Max 160 80 60 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (μW) PD = 2100 × fi + Σ(fo × CL) × VDD2 PD = 9700 × fi + Σ(fo × CL) × VDD PD = 26000 × fi + Σ(fo × CL) × 2 where: fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(fo × CL) = sum of the outputs. VDD2 HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 8 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 11. Waveforms 1/fmax VI CP input GND tW tPLH VOH QPn, QS1 output VOL tPLH VOH QS2 output VOL VM 001aaf113 VM tPHL VM tPHL Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 9. VDD Clock to outputs propagation delays, and clock pulse width and maximum frequency Measurement points Input VM 0.5VDD Output VM 0.5VDD VX 0.1VDD VY 0.9VDD Supply voltage 5 V to 15 V VI STR input GND tW tPLH VOH QPn output VOL VM 001aaj058 VM tPHL Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Strobe to output propagation delays, and strobe pulse width, set up and hold times HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 9 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register VI OE input GND tPLZ VDD output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM tPZL VM VX tPZH outputs disabled outputs enabled 001aai545 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. 3-state output enable and disable times for OE input VI CP input GND t su th VI D input GND VM t su th VM VOH QPn, QS1, QS2 output VOL 001aaf115 VM Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Data input data set up and hold times HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 10 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW 001aaj781 VM VI positive pulse 0V VM a. Input waveform VEXT VDD VI VO RL G RT DUT CL 001aaj915 b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 10. Test circuit Table 10. VDD 5 V to 15 V Test data Input VI VSS or VDD tr, tf ≤ 20 ns VEXT tPHL, tPLH open tPHZ, tPZH VSS tPLZ, tPZL VDD Load CL 50 pF RL 1 kΩ Supply voltage HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 11 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 12. Application information Some examples of applications for the HEF4094B are: • Serial-to-parallel data conversion • Remote control holding register DIGITALLY CONTROLLED EQUIPMENT (REQUIRES CONTINUOUS DIGITAL CONTROL) QP0 D QP7 DIGITALLY CONTROLLED EQUIPMENT DIGITALLY CONTROLLED EQUIPMENT QP0 D QP7 QP0 D QP7 HEF4094B STR CP QS2 HEF4094B STR CP QS2 HEF4094B STR CP CONTROL AND SYNC CIRCUITRY data clock 001aae666 from remote control panel Fig 11. Remote control holding register HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 12 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 12. Package outline SOT38-4 (DIP16) HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 13 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 8 A1 (A 3) A L wM detail X e bp 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ o 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT109-1 (SO16) HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 14 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index θ Lp L 1 8 (A 3) A detail X wM e bp 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT338-1 (SSOP16) HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 15 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 14. Revision history Table 11. Revision history Release date 20100402 Data sheet status Product data sheet Product data sheet Change notice Supersedes HEF4094B_7 HEF4094B_6 Document ID HEF4094B_8 Modifications: HEF4094B_7 Modifications: • • • Section 4 “Functional diagram” Logic diagram corrected. Section 11 “Waveforms” Figure 10 “Test circuit”: updated. Section 11 “Waveforms” Table 10 “Test data” tPHZ and tPZH and tPLZ and tPZL values updated. Product data sheet Product data sheet Product data sheet Product specification Product specification HEF4094B_5 HEF4094B_4 HEF4094B_CNV_3 HEF4094B_CNV_2 - 20091216 HEF4094B_6 HEF4094B_5 HEF4094B_4 HEF4094B_CNV_3 HEF4094B_CNV_2 20091103 20090728 20081030 19950101 19950101 HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 16 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be HEF4094B_8 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 17 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4094B_8 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 08 — 2 April 2010 18 of 19 NXP Semiconductors HEF4094B 8-stage shift-and-store register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 April 2010 Document identifier: HEF4094B_8