HEF4517B_09

HEF4517B Dual 64-bit static shift register Rev. 06 — 10 December 2009 Product data sheet 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of the clock, regardless of the state of nPE/OE. When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode. When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications Industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C Type number HEF4517BP HEF4517BT Package Name DIP16 SO16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 7.5 mm Version SOT38-4 SOT162-1 NXP Semiconductors HEF4517B Dual 64-bit static shift register 5. Functional diagram 7 4 1D 1CP 64-BIT STATIC SHIFT REGISTER 3 1PE/OE INPUT/3-STATE-OUTPUT CIRCUITRY 1Q64 1Q48 1Q32 1Q16 5 2 6 1 9 12 2D 2CP 64-BIT STATIC SHIFT REGISTER 13 2PE/OE INPUT/3-STATE-OUTPUT CIRCUITRY 2Q64 2Q48 2Q32 2Q16 11 14 10 15 001aae694 Fig 1. Functional diagram HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 2 of 15 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 06 — 10 December 2009 © NXP B.V. 2009. All rights reserved. HEF4517B_6 NXP Semiconductors 1D D CP FF 1 O D CP O D CP O D CP O D CP O D CP O D CP O D CP O FF 16 FF 17 FF 32 FF 33 FF 48 FF 49 FF 64 1CP 1PE/OE 1Q16 1Q32 1Q48 1Q64 2D D CP FF 1 O D CP O D CP O D CP O D CP O D CP O D CP O D CP O FF 16 FF 17 FF 32 FF 33 FF 48 FF 49 FF 64 2CP Dual 64-bit static shift register 2PE/OE HEF4517B 2Q16 2Q32 2Q48 2Q64 001aae696 Fig 2. Logic diagram 3 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 6. Pinning information 6.1 Pinning HEF4517B 1Q16 1Q48 1PE/OE 1CP 1Q64 1Q32 1D VSS 1 2 3 4 5 6 7 8 001aae695 16 VDD 15 2Q16 14 2Q48 13 2PE/OE 12 2CP 11 2Q64 10 2Q32 9 2D Fig 3. Pin configuration 6.2 Pin description Table 2. Symbol 1Q16, 2Q16 1Q48, 2Q48 1PE/OE, 2PE/OE 1CP, 2CP 1Q64, 2Q64 1Q32, 2Q32 1D, 2D VSS VDD Pin description Pin 1, 15 2, 14 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 Description 3-state input/output 3-state input/output parallel input-enable/output-enable input clock input 3-state input/output 3-state input/output data input ground supply voltage supply voltage HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 4 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 7. Functional description Table 3. Inputs nCP nD ↑ nPE/OE data entered L into 1st bit data entered H into 1st bit X X L H Function table[1] Inputs/outputs nQ16 content of 16th bit displayed data at nQ16 entered into 17th bit no change Z nQ32 content of 32nd bit displayed data at nQ32 entered into 33rd bit no change Z nQ48 content of 48th bit displayed data at nQ48 entered into 49th bit no change Z nQ64 content of 64th bit displayed One 64-bit shift register. The content of the shift register is shifted over one stage Mode ↑ remains in ‘Z’ Four 16-bit shift register. The state content of the shift registers is shifted over one stage no change Z no change no change ↓ ↓ [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance state; ↑ = positive-going transition; ↓ = negative-going transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IIK VI IOK II/O IDD Tstg Tamb Ptot P [1] [2] Parameter supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation power dissipation Conditions VI < −0.5 V or VI > VDD + 0.5 V VO < −0.5 V or VO > VDD + 0.5 V Min −0.5 −0.5 −65 −40 Max +18 ±10 VDD + 0.5 ±10 ±10 50 +150 +85 750 500 100 Unit V mA V mA mA mA °C °C mW mW mW DIP16 package SO16 package per output [1] [2] - For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 5 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 9. Recommended operating conditions Table 5. Symbol VDD VI Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage input voltage ambient temperature input transition rise and fall rate in free air VDD = 5 V VDD= 10 V VDD= 15 V Conditions Min 3 0 −40 Typ Max 15 VDD +85 3.75 0.5 0.08 Unit V V °C μs/V μs/V μs/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH HIGH-level input voltage Conditions |IO| < 1 μA VDD 5V 10 V 15 V VIL LOW-level input voltage |IO| < 1 μA 5V 10 V 15 V VOH HIGH-level output voltage |IO| < 1 μA 5V 10 V 15 V VOL LOW-level output voltage |IO| < 1 μA 5V 10 V 15 V IOH HIGH-level output current VO = 2.5 V VO = 4.6 V VO = 9.5 V VO = 13.5 V IOL LOW-level output current VO = 0.4 V VO = 0.5 V VO = 1.5 V II IDD input leakage current supply current IO = 0 A 5V 5V 10 V 15 V 5V 10 V 15 V 15 V 5V 10 V 15 V CI input capacitance Tamb = −40 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.7 −0.52 −1.3 −3.6 0.52 1.3 3.6 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 50 100 200 Tamb = 25 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.4 −0.44 −1.1 −3.0 0.44 1.1 3.0 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±0.3 50 100 200 7.5 Tamb = 85 °C Min 3.5 7.0 11.0 4.95 9.95 14.95 −1.1 −0.36 −0.9 −2.4 0.36 0.9 2.4 Max 1.5 3.0 4.0 0.05 0.05 0.05 ±1.0 375 750 1500 V V V V V V V V V V V V mA mA mA mA mA mA mA μA μA μA μA pF Unit HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 6 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions nCP to nQn; see Figure 4 VDD 5V 10 V 15 V tPLH LOW to HIGH propagation delay nCP to nQn; see Figure 4 5V 10 V 15 V tPHZ HIGH to OFF-state propagation delay nPE/OE to nQn; see Figure 5 5V 10 V 15 V tPZH OFF-state to HIGH propagation delay nPE/OE to nQn; see Figure 5 5V 10 V 15 V tPLZ LOW to OFF-state propagation delay nPE/OE to nQn; see Figure 5 5V 10 V 15 V tPZL OFF-state to LOW propagation delay nPE/OE to nQn; see Figure 5 5V 10 V 15 V tt transition time nQn; see Figure 6 5V 10 V 15 V tsu set-up time nQn, nD to nCP; see Figure 7 5V 10 V 15 V th hold time nQn, nD to nCP; see Figure 7 5V 10 V 15 V tW pulse width nQn, nD to nCP; see Figure 7 5V 10 V 15 V fmax maximum frequency see Figure 7 5V 10 V 15 V [1] [1] [1] [1] Extrapolation formula 193 ns + (0.55 ns/pF)CL 74 ns + (0.23 ns/pF)CL 52 ns + (0.16 ns/pF)CL 163 ns + (0.55 ns/pF)CL 64 ns + (0.23 ns/pF)CL 42 ns + (0.16 ns/pF)CL Min - Typ 220 85 60 190 75 50 40 30 25 45 25 20 50 30 25 60 30 25 60 30 20 10 5 5 15 10 10 95 40 30 5 12 16 Max 440 170 120 380 150 100 80 60 50 90 50 40 100 60 50 120 60 50 120 60 40 190 80 60 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 10 ns + (1.00 ns/pF)CL 9 ns + (0.42 ns/pF)CL 6 ns + (0.28 ns/pF)CL 30 25 20 45 30 25 2 6 8 The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 7 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD 5V 10 V 15 V Typical formula for PD (μW) PD = 7000 × fi + Σ(fo × CL) × VDD2 PD = 28000 × fi + Σ(fo × CL) × VDD2 PD = 70000 × fi + Σ(fo × CL) × VDD2 where: fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(fo × CL) = sum of the outputs. 12. Waveforms VI nCP input 0V tPHL VOH nQn output VOL VM 001aaj914 VM tPLH Measurement points are given in Table 9 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 4. Table 9. Input VM 0.5VI Propagation delays for nCP to nQn Measurement points Output VM 0.5VDD VX 0.1VDD VY 0.9VDD HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 8 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register VI nPE/OE input 0V tPLZ VDD nQn output LOW-to-OFF OFF-to-LOW VM VOL tPHZ VOH nQn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aaj913 VM tPZL VX tPZH VY VM Measurement points are given in Table 9 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 5. Enable and disable times and 3-state propagation delays tt VOH nQn output VOL 10 % 90 % tt 001aaj916 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 6. Transition times for nQn 1/fmax VI nCP input 0V VM tsu th tW VI nQn, nD input 0V 001aae697 VM The shading indicates where the data (nQn and nD) is permitted to change for predictable output changes. Measurement points are given in Table 9 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 7. Waveforms showing minimum clock pulse width and maximum frequency and set-up and hold times for nQn (as data input) or nD to nCP HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 9 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW 001aaj781 VM VI positive pulse 0V VM a. Input waveforms VEXT VDD VI VO RL G RT DUT CL 001aaj915 b. Test circuit Test data is given in Table 10. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Table 10. Supply voltage Test circuit for switching times Test data Input VI VDD tr, tf ≤ 20 ns Load CL 50 pF RL 1 kΩ VEXT tPLH, tPHL open tPLZ, tPZL 2VDD tPHZ, tPZH GND 5 V to 15 V HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 10 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D seating plane ME A2 A L A1 c Z e b1 b 16 9 b2 MH wM (e 1) pin 1 index E 1 8 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 Fig 9. HEF4517B_6 Package outline SOT38-4 (DIP16) © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 11 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c y HE vMA Z 16 9 Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT162-1 (SO16) HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 12 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 14. Revision history Table 11. Revision history Release date 20091210 Data sheet status Product data sheet Product data sheet Product data sheet Product specification Product specification Change notice Supersedes HEF4517B_5 HEF4517B_4 HEF4517B_CNV_3 HEF4517B_CNV_2 Document ID HEF4517B_6 Modifications: HEF4517B_5 HEF4517B_4 HEF4517B_CNV_3 HEF4517B_CNV_2 • Section 9 “Recommended operating conditions” Δt/ΔV values updated. 20090728 20090406 19950101 19950101 HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 13 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4517B_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 10 December 2009 14 of 15 NXP Semiconductors HEF4517B Dual 64-bit static shift register 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 December 2009 Document identifier: HEF4517B_6