HEF4526BP,652

HEF4526B Programmable 4-bit binary down counter Rev. 5 — 22 November 2011 Product data sheet 1. General description The HEF4526B is a synchronous programmable 4-bit binary down counter with active HIGH and active LOW clock inputs (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (A0 to A3), a cascade feedback input (CF), four buffered parallel outputs (Q0 to Q3), a terminal count output (TC), an overriding asynchronous master reset input (MR) and a decoded TC output that can be used for divide-by-n applications. In single stage applications the TC output is connected to PL. CF allows cascade divide-by-n operation with no additional gates required. Information on A0 to A3 is loaded into the counter while PL is HIGH, independent of all other inputs except MR, which must be LOW. When PL and CP1 are LOW, the counter advances on a LOW-to-HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in the zero state (Q0 = Q1 = Q2 = Q3 = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of other inputs. The clock input is highly tolerant of slower clock rise and fall times due to Schmitt trigger action. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits      Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C. Type number Package Name Description Version HEF4526BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4526BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 4. Functional diagram 3 5 11 14 2 PL A0 A1 A2 A3 PARALLEL LOAD CIRCUITRY CD/SD 6 CP0 CP 4 CP1 BINARY DOWN COUNTER CD Q3 1 Q2 15 Q1 9 10 MR Q0 7 TC 12 ZERO DETECTOR 13 CF 001aae719 Fig 1. Functional diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP0 input CP1 input MR input Q0 Q1 Q2 Q3 001aak014 Fig 2. Timing diagram HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Q0 A1 Q1 A2 Q2 A3 NXP Semiconductors HEF4526B Product data sheet A0 Q3 PL Rev. 5 — 22 November 2011 All information provided in this document is subject to legal disclaimers. MR CD1 CD2 O FF T 1 O SD CD1 CD2 O FF T 2 O SD CD1 CD2 O FF T 3 O SD CD1 CD2 O FF T 4 O SD CP1 CF TC Fig 3. Logic diagram HEF4526B 3 of 19 © NXP B.V. 2011. All rights reserved. 001aae722 Programmable 4-bit binary down counter CP0 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 5. Pinning information 5.1 Pinning HEF4526B Q3 1 16 VDD A3 2 15 Q2 PL 3 14 A2 CP1 4 13 CF A0 5 12 TC CP0 6 11 A1 Q0 7 10 MR VSS 8 9 Q1 001aae720 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 to A3 5, 11, 14, 2 parallel input PL 3 parallel load input CP0 6 clock input (LOW-to-HIGH, triggered) CP1 4 clock input (HIGH-to-LOW, triggered) CF 13 cascade feedback input MR 10 asynchronous master reset input TC 12 terminal count output Q0 to Q3 7, 9, 15, 1 buffered parallel output VDD 16 supply voltage VSS 8 ground (0 V) HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 6. Functional description Table 3. Function table[1] MR PL CP0 CP1 Mode H X X X reset (asynchronous) L H X X preset (asynchronous) L L  H no change L L L  no change L L  X no change L L X  no change L L  L counter advances L L H  counter advances [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition. Table 4. Counting mode CF = HIGH; PL = LOW; MR = LOW. Count Outputs Q3 Q2 Q1 Q0 15 H H H H 14 H H H L 13 H H L H 12 H H L L 11 H L H H 10 H L H L 9 H L L H 8 H L L L 7 L H H H 6 L H H L 5 L H L H 4 L H L L 3 L L H H 2 L L H L 1 L L L H 0 L L L L HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Table 5. Single stage operation Divide-by-n; MR = LOW; CF = HIGH; CP1 = LOW. PL A3 A2 A1 A0 L X X X TC H H H TC H H H L 14 TC H H L H 13 TC H H L L 12 TC H L H H 11 TC H L H L 10 TC H L L H 9 TC H L L L 8 TC L H H H 7 TC L H H L 6 TC L H L H 5 TC L H L L 4 TC L L H H 3 TC L L H L 2 TC L L L H 1 TC L L L L no operation 0 1 Divide by TC output pulse width X 16 one clock period H 15 clock pulse HIGH 2 3 4 15 5 14 6 13 7 12 11 10 9 8 001aae721 Fig 5. State diagram HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 7. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature total power dissipation Ptot P power dissipation Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V to any supply terminal DIP16 package [1] SO16 package [2] per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA - 10 mA - 100 mA 65 +150 C 40 +85 C - 750 mW - 500 mW - 100 mW 8. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VDD supply voltage 3 VI input voltage 0 Tamb ambient temperature in free air 40 t/V input transition rise and fall rate VCC = 5 V - HEF4526B Product data sheet Conditions Min Typ Max Unit - 15 V - VDD V - +85 C - 3.75 s/V VCC = 10 V - - 0.5 s/V VCC = 15 V - - 0.08 s/V All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 9. Static characteristics Table 8. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Min VIH VIL VOH VOL IOL IOH HIGH-level input voltage Tamb = 85 C Min Min Max Unit Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA HIGH-level output current VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 mA LOW-level input voltage IO < 1 A HIGH-level output voltage IO < 1 A LOW-level output voltage LOW-level output current II input leakage current IDD supply current CI IO < 1 A Max Tamb = 25 C input capacitance HEF4526B Product data sheet IO < 1 A VO = 4.6 V 5V - 0.52 - 0.44 - 0.36 mA VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA 15 V - 0.3 - 0.3 - 1.0 A 5V - 20 - 20 - 150 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A - - - - 7.5 - - pF IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 10. Dynamic characteristics Table 9. Dynamic characteristics VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions VDD CP0, CP1 to Qn; see Figure 6 CP0, CP1 to TC; see Figure 6 PL to Qn; see Figure 6 MR to Qn Extrapolation formula Min Typ Max Unit 123 ns + (0.55 ns/pF)CL - 150 300 ns 10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 183 ns + (0.55 ns/pF)CL - 210 420 ns 10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns 15 V 62 ns + (0.16 ns/pF)CL - 70 140 ns 5V 173 ns + (0.55 ns/pF)CL - 200 400 ns 10 V 69 ns + (0.23 ns/pF)CL - 80 160 ns 15 V 52 ns + (0.16 ns/pF)CL - 60 120 ns 5V 113 ns + (0.55 ns/pF)CL - 140 280 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 32 ns + (0.16 ns/pF)CL - 40 80 ns 123 ns + (0.55 ns/pF)CL - 150 300 ns 10 V 54 ns + (0.23 ns/pF)CL - 65 130 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 183 ns + (0.55 ns/pF)CL - 210 420 ns 10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns 15 V 62 ns + (0.16 ns/pF)CL - 70 140 ns 5V 153 ns + (0.55 ns/pF)CL - 180 360 ns 10 V 59 ns + (0.23 ns/pF)CL - 70 140 ns 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V [1] 15 V tPLH LOW to HIGH propagation delay CP0, CP1 to Qn; see Figure 6 CP0, CP1 to TC; see Figure 6 PL to Qn; see Figure 6 5V [1] 15 V tt tsu th transition time set-up time hold time HEF4526B Product data sheet see Figure 6 An to PL; see Figure 6 An to PL; see Figure 6 5V [1] 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 30 0 - ns 10 V 20 0 - ns 15 V 15 0 - ns 5V 30 5 - ns 10 V 20 5 - ns 15 V 15 5 - ns All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Table 9. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter Conditions tW CP0 input; LOW; see Figure 6 pulse width VDD CP1 input; HIGH; see Figure 6 PL input; HIGH; see Figure 6 MR input; LOW maximum frequency fmax PL = LOW; see Figure 6 Extrapolation formula Min Typ Max Unit 5V 80 40 - ns 10 V 40 20 - ns 15 V 30 15 - ns 5V 80 40 - ns 10 V 40 20 - ns 15 V 30 15 - ns 5V 100 50 - ns 10 V 40 20 - ns 15 V 32 16 - ns 5V 130 65 - ns 10 V 50 25 - ns 15 V 40 20 - ns 6 12 - MHz 10 V 12 25 - MHz 15 V 16 32 - MHz 5V [2] [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] In the divide-by-n mode (PL connected to TC), the CP0 or CP1 pulse width must be greater than the maximum HIGH to LOW propagation delay for CP0 or CP1 to TC. Table 10. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (W) where: 5V PD = 1000  fi + (fo  CL)  VDD 2 10 V PD = 4000  fi + (fo  CL)  VDD 2 15 V PD = 10000  fi + (fo  CL)  VDD2 fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, (fo  CL) = sum of the outputs. HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 11. Waveforms 1/fmax Vl CP0 input VM 0V tW Vl CP1 input VM 0V tW VOH Qn output VM VOL tPLH tPLH tPHL VOH TC output VM VOL tPHL tPLH 001aae724 a. Propagation delays for CP0, CP1 to Qn, and TC, minimum CP0 and CP1 pulse widths and maximum frequency Vl VM PL input 0V tsu th tW Vl VM An input 0V tPLH tPHL VOH 90% Qn output 10% VOL tt tt 001aae723 b. Propagation delays for PL and An to Qn, setup and hold times for PL to An, Qn transition times and minimum PL pulse width Measurement points are given in Table 11. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig 6. Waveforms showing switching times HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter tW VI 90 % 90 % negative pulse VM VM 10 % 0V VI 10 % tf tr tr tf 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD VI VO G DUT CL RT 001aag182 b. Test circuit Test data is given in Table 11; Definitions for test circuit: DUT = Device Under Test; CL = Load capacitance, including jig and probe capacitance; RL = Load resistance; RT = Termination resistance, should be equal to the output impedance Zo of the pulse generator. Fig 7. Test circuit for switching times Table 11. Measurement points and test data Supply voltage 5 V to 15 V Input Load VI VM tr, tf CL RL VDD 0.5VI  20 ns 50 pF 1 k 12. Application information Some examples of HEF4526B applications are: • Divide-by-n counter • Programmable frequency divider HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter cycle inhibit VDD Q0 Q1 Q2 Q3 PL Q0 Q1 Q2 Q3 PL VDD CF clock CF MR HEF4526B TC (L.S.D.) CP1 MR HEF4526B TC (M.S.D.) CP1 CP0 A0 CP0 A0 A1 A2 A3 A1 A2 A3 Counting cycle: 10 kΩ (4x) S 10 kΩ (4x) n0 S n1 VDD VDD master reset 15 14 . . . n0 . . 1 0 L.S.D. counter n1 . . 1 stop at 0 LOW M.S.D. counter 001aae725 L.S.D. = Least Significant Digit; M.S.D. = Most Significant Digit. Fig 8. Typical 2-stage programmable down counter (one cycle) application. f0 = fi/n Q0 Q1 Q2 Q3 PL Q0 Q1 Q2 Q3 PL CF MR CP1 clock CP0 A0 VDD HEF4526B TC MR (L.S.D.) A1 A2 CF CP1 CP0 A0 A3 HEF4526B TC (M.S.D.) A1 A2 A3 Counting cycle: 10 kΩ (4x) S master reset n0 VDD 10 kΩ (4x) S n1 VDD 15 14 . . . . . n0 . . 2 1 0 L.S.D. counter n1 . . 2 1 0 M.S.D. counter 001aae726 L.S.D. = Least Significant Digit; M.S.D. = Most Significant Digit. Fig 9. Typical 2-stage programmable frequency divider application HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 10. Package outline SOT38-4 (DIP16) HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4526B v.5 20111122 Product data sheet - HEF4526B v.4 Modifications: • • Section Applications removed Table 8: IOH minimum values changed to maximum HEF4526B v.4 20090921 Product data sheet - HEF4526B_CNV v.3 HEF4526B_CNV v.3 19950101 Product specification - HEF4526B_CNV v.2 HEF4526B_CNV v.2 19950101 Product specification - - HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 16 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 17 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4526B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 22 November 2011 © NXP B.V. 2011. All rights reserved. 18 of 19 HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 November 2011 Document identifier: HEF4526B