HTCICC6401EW/C1,00

HITAG RO64 HTCICC64 Rev. 3.1 — 17 July 2008 152131 Product data sheet COMPANY PROPRIETARY 1. General description The HITAG product line is well known and established in the contactless identification market. Due to the open marketing strategy of NXP Semiconductors there are various manufacturers well established for both the transponders / cards as well as the Read/Write Devices. All of them supporting HITAG transponder IC's. With the new HITAG RO64, NXP is addressing the low end LF market, by offering a preprogrammed, read-only IC variant. The advantages of this transponder IC are: • • • • proven HITAG performance easy to assemble because of mega-bumps strong RF-modulation low cost manufacturing because of preprogrammed TTF code and 210 pF Cres HITAG RO64 operates in an continuos TTF mode where he modulates the readerfield with it´s preprogrammed 64 bit memory content 2. Features 2.1 Features list       Integrated Circuit for Contactless Identification Transponders and Cards Integrated resonance capacitor of 210 pF with ± 5% tolerance over full production Frequency range 100 to 150 kHz. 64 bit preprogrammed TTF response 10 years data retention Delivery form: sawn, gold-megabumped 8” Wafer 3. Ordering information Table 1. Ordering information Type number HTCICC6401EW/C1 Package Name Description Version Wafer Au-bumped die on sawn wafer - HITAG RO64 NXP Semiconductors HTCICC64 4. Block diagram The HITAG RO64 Transponder requires no external power supply. The contactless interface generates the power supply and the system clock via the resonant circuitry by inductive coupling to the Read/Write Device (RWD). The interface also demodulates data transmitted from the RWD to the HITAG RO64 Transponder, and modulates the magnetic field for data transmission from the HITAG RO64 Transponder to the RWD. Data are stored in a non-programmable memory (EEPROM). 64 bit Fig 1. Block diagram 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 2 of 13 HITAG RO64 NXP Semiconductors HTCICC64 5. Functional description 5.1 Memory organization P P P P Cloum Cloum Cloum Cloum 0: 1: 2: 3: DBit 31 DBit 27 DBit 23 DBit 19 DBit 15 DBit 11 DBit 7 DBit 30 DBit 26 DBit 22 DBit 18 DBit 14 DBit 10 DBit 6 DBit 3 DBit 2 DBit 29 DBit 25 DBit 21 DBit 17 DBit 13 DBit 9 DBit 5 DBit 1 DBit 28 DBit 24 DBit 20 DBit 16 DBit 12 DBit 8 DBit 4 DBit 0 Fig 2. Memory organization The memory is preprogrammed as shown in Figure 2. This data gets continuously sent back as soon as the transponder has sufficient energy. 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 3 of 13 HITAG RO64 NXP Semiconductors HTCICC64 6. Protocol timing 6.1 HITAG RO64 Transponder waiting time before transmitting data in TTF Mode y=0.95a Fig 3. HITAG S Transponder waiting time before transmitting data in TTF Mode After switching on the powering field, the HITAG RO64 Transponder waits a time tTTF before transmitting data if it is configured in TTF Mode. Table 2. tTTF HITAG RO Transponder programming time Min Typ Max Unit 565 585 625 T0 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 4 of 13 HITAG RO64 NXP Semiconductors HTCICC64 7. State Diagram 7.1 General Description of States Power Off The powering magnetic field is switched off or the HITAG RO64 Transponder is out of field. Transponder Talks First (TTF) The HITAG RO64 Transponder enters this State after being powered up. Entered this State, the HITAG RO64 Transponder continuously transmits the preprogrammed memory data. This data gets transmitted Manchester coded with 2kbit/s. 8. Mechanical specification 8.1 Wafer • • • • Diameter: 200 mm Thickness: 280 μm ± 15 μm PGDW: 25080 PCM location: reticle area 8.2 Wafer backside • Material: • Treatment: • Roughness: Si ground and stress release Ra max. 0.5 μm, Rt max. 5 μm 8.3 Chip dimensions • Chip size: x = 1030 μm, y = 990 μm • Scribe line: x-line: 80 μm y-line: 80 μm 8.4 Passivation on front • Type: • Material: • Thickness: Sandwich structure PSG / Nitride (on top) 500 nm / 600 nm 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 5 of 13 HITAG RO64 NXP Semiconductors HTCICC64 8.5 Au bump • • • • • Bump material: > 99.9 % pure Au Bump hardness: 35 – 80 HV 0.005 Bump shear strength: > 70 MPa Bump height: 18 μm Bump height uniformity: – within a die: ± 2 μm – within a wafer: ± 3 μm – wafer to wafer: ± 4 μm • Bump flatness: • Bump size: ± 1.5 μm 200 x 500 μm – IN1, IN2: – VSS, Vdde, TestIO1: 60 x 60 μm • Bump size variation: ± 5 μm • Under bump metallization: sputtered TW 8.6 Fail die identification All fail dies are inked according to electrical test results. Electronic wafer mapping covers the electrical test results and additionally the results of mechanical / visual inspection. Remark: Ink dots are not corrected after mechanical/visual inspection. 1. Pads VSS, Vdde and TestIO are disconnected for sawn wafers 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 6 of 13 HITAG RO64 NXP Semiconductors HTCICC64 9. Chip orientation and bondpad locations 9.1 Chip orientation and bondpad locations (5) TestIO y IN 1 (6) (1) (3) (7) Vdde IN 2 (7) Vss IN 2 center coordinates x [µm] y [µm] 0.0 0.0 526.0 0.0 -170.0 689.0 606.0 689.0 696.0 689.0 (9) PAD IN 1 IN 2 TestIO Vdde Vss (8) x (4) (2) (1) (2) (3) (4) (5) (6) (7) (8) (9) Chip step on wafer, x-dimension Chip step on wafer, y-dimension IC size, x-dimension IC size, y-dimension IN 1 bump center to IC edge, x-dimension IN 1 bump center to IC edge, y-dimension IN 1/IN 2 corner bevelling Sawline with, x-dimension Sawline with, y-dimension 1070µm 1110µm 990µm 1030µm 232µm 279µm 30µm 80µm 80µm IN 1/IN 2 bump size, x-dimension IN 1/IN 2 bump size, y-dimension TestIO/Vdde/Vss bump size, x-dimension TestIO/Vdde/Vss bump size, y-dimension 200µm 500µm 60µm 60µm TestIO/Vdde/Vss are disconnected Fig 4. Chip orientation and bondpad locations HTCICC64 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 7 of 13 HITAG RO64 NXP Semiconductors HTCICC64 10. Limiting values 10.1 Absolute maximum ratings Table 3. Absolute maximum ratings[1][2] Symbol Parameter Conditions Min Typ Max Unit Tstg storage temperature range - -55 - +140 °C Tj junction temperature - -55 - +140 °C VESD ESD voltage immunity JEDEC JESD 22-A114-B Human Body Model ±2 − kVpeak ±20 − mApeak Imax IN1-IN2 maximum input peak current - - [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 11. Recommended operating conditions Table 4. Operating conditions Symbol Parameter Conditions Min Typ[1] Max Unit Top operating temperature - -25 - +85 °C IIN1-IN2 input current - - - ±10 mApeak VIN1-IN2 rd minimum operating voltage - - ±3.5 ±4.5 Vpeak fop operating frequency - 100 125 150 kHz [1] Typical ratings are not guaranteed. These values listed are at room temperature. 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 8 of 13 HITAG RO64 NXP Semiconductors HTCICC64 12. Characteristics Table 5. Characteristics Top = -25 to +85 °C Symbol Parameter Conditions Min Typ[1] Max Unit Cres input capacitance between IN1 – IN2[2] VIN1-IN2 = 2 Vrms 199 210 221 pf Pmin rd minimum operating supply power [3][4] VIN1-IN2 = VIN1-IN2 rd - 20 - μW Vclk clock recovery sensitivity - - 100 mVpp mmod response modulation index[5] - 85 - % tret data retention 10 - - years V high – V mod m mod = -------------------------------V high + V mod Tamb ≤ 55 °C [1] Typical ratings are not guaranteed. These values listed are at room temperature. [2] Measured with an HP4285A LCR meter at 125 kHz. [3] Including losses in resonant capacitor and rectifier. [4] Determined with: Qcoil = 20, Lcoil = 7.5 mH, optimal tuned resonance circuit. [5] Definition according to Figure 5 Vmod Vhigh Vhigh = 6.3 Vp, Qcoil = 20, Lcoil = 7.5 mH Modulator ON Envelope of VIN1 - IN2 Modulator OFF Fig 5. Response modulation index 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 9 of 13 HITAG RO64 NXP Semiconductors HTCICC64 13. Final wafertest specification Minimum yield per wafer: 30 % of 25080 potential good dies. 14. References [1] General quality specification [2] General specification for 8” wafer [3] Bumped wafer specification [4] Application note HITAG S coil design guide 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 10 of 13 HITAG RO64 NXP Semiconductors HTCICC64 15. Revision history Table 6: Revision history Document ID Release date Data sheet status 152131 20080717 Product data sheet • 152130 Product data sheet addendum 152130 - Initial version 152131 Product data sheet Supersedes Correction of the sentence “Data are stored in a non-programmable memory (EEPROM)” in Section 4 “Block diagram” on page 2 18 March 2008 • Change notice © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 11 of 13 HITAG RO64 NXP Semiconductors HTCICC64 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. HITAG — is a trademark of NXP B.V. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 152131 Product data sheet © NXP B.V. 2011. All rights reserved. Rev. 3.1 — 17 July 2008 12 of 13 HITAG RO64 NXP Semiconductors HTCICC64 18. Tables Table 1. Table 2. Table 3. Ordering information . . . . . . . . . . . . . . . . . . . . .1 HITAG RO Transponder programming time . . . .4 Absolute maximum ratings[1][2] . . . . . . . . . . . . . .8 Table 4. Table 5. Table 6: Operating conditions . . . . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 19. Figures Fig 1. Fig 2. Fig 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Memory organization . . . . . . . . . . . . . . . . . . . . . . .3 HITAG S Transponder waiting time before transmitting data in TTF Mode . . . . . . . . . . . . . . . .4 Fig 4. Fig 5. Chip orientation and bondpad locations HTCICC64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Response modulation index . . . . . . . . . . . . . . . . . 9 16.2 16.3 16.4 17 18 19 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20. Contents 1 2 2.1 3 4 5 5.1 6 6.1 7 7.1 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 10 10.1 11 12 13 14 15 16 16.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features list . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Memory organization . . . . . . . . . . . . . . . . . . . . 3 Protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . 4 HITAG RO64 Transponder waiting time before transmitting data in TTF Mode . . . . . . . . . . . . . 4 State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Description of States . . . . . . . . . . . . . . 5 Mechanical specification . . . . . . . . . . . . . . . . . 5 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Wafer backside . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chip dimensions . . . . . . . . . . . . . . . . . . . . . . . . 5 Passivation on front . . . . . . . . . . . . . . . . . . . . . 5 Au bump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Fail die identification . . . . . . . . . . . . . . . . . . . . . 6 Chip orientation and bondpad locations . . . . . 7 Chip orientation and bondpad locations . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Final wafertest specification. . . . . . . . . . . . . . 10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 12 13 13 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 July 2008 Document identifier: 152131