LPC1850_1109

LPC1850/30/20/10 32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller Rev. 2.2 — 9 September 2011 Preliminary data sheet 1. General description The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals. Remark: This data sheet describes the Rev ‘-’ and the Rev ‘A’ versions of parts LPC1850/30/20/10. 2. Features and benefits  Processor core  ARM Cortex-M3 processor, running at frequencies of up to 150 MHz.  ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  Non-maskable Interrupt (NMI) input.  JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.  Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.  System tick timer.  On-chip memory  200 kB SRAM for code and data use.  Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.  64 kB ROM containing boot code and on-chip software drivers.  32-bit One-Time Programmable (OTP) memory for general-purpose use.  Clock generation unit  Crystal oscillator with an operating range of 1 MHz to 25 MHz. NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller  12 MHz internal RC oscillator trimmed to 1 % accuracy over temperature and voltage.  Ultra-low power RTC crystal oscillator.  Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the third PLL can be used as audio PLL.  Clock output.  Configurable digital peripherals:  State Configurable Timer (SCT) subsystem on AHB.  Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCT, and ADC0/1.  Serial interfaces:  Quad SPI Flash Interface (SPIFI) with four lanes and data rates of up to 40 MB per second total.  10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).  One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip PHY.  One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY. USB interface electrical test software included in ROM USB stack.  Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support synchronous mode and a smart card interface conforming to ISO7816 specification.  Two C_CAN 2.0B controllers with one channel each.  Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.  One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.  One standard I2C-bus interface with monitor mode and standard I/O pins.  Two I2S interfaces with DMA support, each with one input and one output.  Digital peripherals:  External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices.  LCD controller with DMA support and a programmable display resolution of up to 1024H  768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.  SD/MMC card interface.  Eight-channel General-Purpose DMA (GPDMA) controller can access all memories on the AHB and all DMA-capable AHB slaves.  Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors and open-drain modes.  GPIO registers are located on the AHB for fast access. GPIO ports have DMA support. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 2 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller      Up to 8 GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources.  Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  Four general-purpose timer/counters with capture and match capabilities.  One motor control PWM for three-phase motor control.  One Quadrature Encoder Interface (QEI).  Repetitive Interrupt timer (RI timer).  Windowed watchdog timer.  Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers.  Alarm timer; can be battery powered. Analog peripherals:  One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.  Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Security:  Hardware-based AES security engine programmable through an on-chip API.  Two 128-bit secure OTP memories for AES key storage and customer use.  Unique ID for each device. Power:  Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain.  RTC power domain can be powered separately by a 3 V battery supply.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.  Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.  Brownout detect with four separate thresholds for interrupt and forced reset.  Power-On Reset (POR). Available as 208-pin, 144-pin, and 100-pin LQFP packages and as 256-pin, 180-pin, and 100-pin BGA packages. 3. Applications  Industrial  Consumer  White goods  RFID readers  e-Metering LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 3 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1. Ordering information Package Name LPC1850FET256 LPC1850FET180 LPC1830FET256 LPC1830FET180 LPC1830FET100 LPC1820FET100 LBGA256 Description Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm Plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm Version SOT740-2 SOT570-3 SOT459-1 SOT740-2 SOT570-3 SOT486-1 SOT486-1 SOT407-1 SOT486-1 Type number TFBGA180 Thin fine-pitch ball grid array package; 180 balls LBGA256 LPC1850FBD208 LQFP208 TFBGA180 Thin fine-pitch ball grid array package; 180 balls Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm Plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm Plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1830FBD144 LQFP144 LPC1820FBD144 LQFP144 LPC1820FBD100 LQFP100 LPC1810FET100 LPC1810FBD144 LQFP144 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 4.1 Ordering options Table 2. Ordering options Total SRAM LCD Ethernet USB0 (Host, Device, OTG) yes yes yes no no no no no no no no no yes yes yes yes yes yes yes no no no no no yes yes yes yes yes yes yes yes yes yes no no USB1 ADC PWM (Host, channels Device)/ ULPI interface yes/yes yes/yes yes/yes yes/yes yes/yes yes/no yes/no no no no no no 8 8 8 8 8 4 8 4 8 5 4 8 yes yes yes yes yes no yes no yes no no yes QEI GPIO Package Type number LPC1850FET256 200 kB LPC1850FET180 200 kB LPC1850FBD208 200 kB LPC1830FET256 200 kB LPC1830FET180 200 kB LPC1830FET100 200 kB LPC1830FBD144 200 kB LPC1820FET100 168 kB LPC1820FBD144 168 kB LPC1820FBD100 168 kB LPC1810FET100 136 kB LPC1810FBD144 136 kB yes yes yes yes yes no no no no no no no 164 118 164 164 118 49 83 49 83 49 49 83 LBGA256 TFBGA180 LQFP208 LBGA256 TFBGA180 TFBGA100 LQFP144 TFBGA100 LQFP144 LQFP100 TFBGA100 LQFP144 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 4 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 5. Block diagram SWD/TRACE PORT/JTAG LPC1850/30/20/10 HIGH-SPEED PHY TEST/DEBUG INTERFACE GPDMA ARM CORTEX-M3 I-code bus BRIDGE 0 WWDT USART0 UART1 SSP0 TIMER0 TIMER1 SCU GPIO interrupts GPIO GROUP0 interrupt GPIO GROUP1 interrupt D-code bus system bus ETHERNET(1) 10/100 MAC IEEE 1588 HIGHSPEED USB0(1) HOST/ DEVICE/ OTG USB1(1) HOST/ DEVICE LCD(1) SD/ MMC masters slaves AHB MULTILAYER MATRIX slaves SPIFI EMC 64 kB ROM BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE BRIDGE MOTOR CONTROL PWM(1) I2C0 I2S0 I2S1 C_CAN1 RI TIMER USART2 USART3 TIMER2 TIMER3 SSP1 I2C1 10-bit DAC C_CAN0 10-bit ADC0 10-bit ADC1 CGU CCU1 CCU2 RGU ALARM TIMER BACKUP REGISTERS POWER MODE CONTROL CONFIGURATION REGISTERS EVENT ROUTER OTP MEMORY 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM 16/32 kB AHB SRAM 16 kB + 16 kB AHB SRAM(1) AES HS GPIO SCT QEI(1) RTC GIMA 12 MHz IRC RTC POWER DOMAIN RTC OSC = connected to GPDMA 002aaf218 (1) Not available on all parts (see Table 2). Fig 1. LPC1850/30/20/10 block diagram LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 5 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 6.1 Pinning LPC1850/30FET256 2 1 A B C D E F G H J K L M N P R T 002aaf230 ball A1 index area 4 3 5 6 7 8 9 10 11 12 13 14 15 16 ball A1 index area 1 A B C D E F G H J K L M N P LPC1850/30FET180 2 3 4 5 6 7 8 9 10 11 12 13 14 002aag365 Transparent top view Transparent top view Fig 2. Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA180 package ball A1 index area 1 A B C D E F G H J K 2 LPC1830/20/10FET100 3 4 5 6 7 8 9 10 002aag366 Transparent top view Fig 4. Pin configuration TFBGA100 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 6 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 208 157 144 1 156 1 109 108 73 72 75 51 002aag369 002aag368 © NXP B.V. 2011. All rights reserved. LPC1850FBD208 LPC1830/20/10FBD144 52 104 53 105 36 37 002aag367 Fig 5. Pin configuration LQFP208 package Fig 6. Pin configuration LQFP144 package 100 1 LPC1820FBD100 25 26 50 Fig 7. Pin configuration LQFP100 package 6.2 Pin description On the LPC1850/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA to PF, with up to 20 pins used per port. Each digital pin may support up to eight different digital functions, including General Purpose I/O (GPIO), selectable through the SCU registers. Note that the pin name is not indicative of the GPIO port assigned to it. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 76 7 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 Multiplexed digital pins P0_0 L3 x G2 x 32 22 [3] I; PU I/O I/O I I/O Type GPIO0[0] — General purpose digital input/output pin. SSP1_MISO — Master In Slave Out for SSP1. ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). R — Function reserved. R — Function reserved. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O GPIO0[1] — General purpose digital input/output pin. SSP1_MOSI — Master Out Slave in for SSP1. ENET_COL — Ethernet Collision detect (MII interface). R — Function reserved. R — Function reserved. R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. GPIO0[4] — General purpose digital input/output pin. CTIN_3 — SCT input 3. Capture input 1 of timer 1. EMC_A5 — External memory address line 5. R — Function reserved. R — Function reserved. SSP0_SSEL — Slave Select for SSP0. R — Function reserved. R — Function reserved. I/O I I I/O I/O - P0_1 M2 x G1 x 34 23 [3] I; PU I/O P1_0 P2 x H1 x 38 25 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 8 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P1_1 R2 x K2 x 42 28 [3] I; PU I/O O I/O I/O - Type GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 5). CTOUT_7 — SCT output 7. Match output 3 of timer 1. EMC_A6 — External memory address line 6. R — Function reserved. R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved. R — Function reserved. GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 5). CTOUT_6 — SCT output 6. Match output 2 of timer 1. EMC_A7 — External memory address line 7. R — Function reserved. R — Function reserved. SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. R — Function reserved. GPIO0[10] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. EMC_OE — LOW active Output Enable signal. USB0_IND1 — USB0 port indicator LED control output 1. SSP1_MISO — Master In Slave Out for SSP1. R — Function reserved. SD_RST — SD/MMC reset signal for MMC4.4 card. GPIO0[11] — General purpose digital input/output pin. CTOUT_9 — SCT output 9. Match output 1 of timer 2. R — Function reserved. EMC_BLS0 — LOW active Byte Lane select signal 0. USB0_IND0 — USB0 port indicator LED control output 0. SSP1_MOSI — Master Out Slave in for SSP1. R — Function reserved. SD_VOLT1 — SD/MMC bus voltage select output 1. O I/O I/O O O O I/O O O O O I/O O P1_2 R3 x K1 x 43 29 [3] I; PU I/O P1_3 P5 x J1 x 44 30 [3] I; PU I/O P1_4 T3 x J2 x 47 32 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 9 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P1_5 R5 x J4 x 48 33 [3] I; PU I/O O O O Type GPIO1[8] — General purpose digital input/output pin. CTOUT_10 — SCT output 10. Match output 2 of timer 2. R — Function reserved. EMC_CS0 — LOW active Chip Select 0 signal. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). SSP1_SSEL — Slave Select for SSP1. R — Function reserved. SD_POW — . GPIO1[9] — General purpose digital input/output pin. CTIN_5 — SCT input 5. Capture input 2 of timer 2. R — Function reserved. EMC_WE — LOW active Write Enable signal. R — Function reserved. R — Function reserved. R — Function reserved. SD_CMD — SD/MMC command signal. GPIO1[0] — General purpose digital input/output pin. U1_DSR — Data Set Ready input for UART1. CTOUT_13 — SCT output 13. Match output 1 of timer 3. EMC_D0 — External memory data line 0. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active high). R — Function reserved. R — Function reserved. R — Function reserved. I/O O I O I/O I O I/O O - P1_6 T4 x K4 x 49 34 [3] I; PU I/O P1_7 T5 x G4 x 50 35 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 10 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P1_8 R7 x H5 x 51 36 [3] I; PU I/O O O I/O O Type GPIO1[1] — General purpose digital input/output pin. U1_DTR — Data Terminal Ready output for UART1. CTOUT_12 — SCT output 12. Match output 0 of timer 3. EMC_D1 — External memory data line 1. R — Function reserved. R — Function reserved. R — Function reserved. SD_VOLT0 — SD/MMC bus voltage select output 0. GPIO1[2] — General purpose digital input/output pin. U1_RTS — Request to Send output for UART1. CTOUT_11 — SCT output 11. Match output 3 of timer 2. EMC_D2 — External memory data line 2. R — Function reserved. R — Function reserved. R — Function reserved. SD_DAT0 — SD/MMC data bus line 0. GPIO1[3] — General purpose digital input/output pin. U1_RI — Ring Indicator input for UART1. CTOUT_14 — SCT output 14. Match output 2 of timer 3. EMC_D3 — External memory data line 3. R — Function reserved. R — Function reserved. R — Function reserved. SD_DAT1 — SD/MMC data bus line 1. GPIO1[4] — General purpose digital input/output pin. U1_CTS — Clear to Send input for UART1. CTOUT_15 — SCT output 15. Match output 3 of timer 3. EMC_D4 — External memory data line 4. R — Function reserved. R — Function reserved. R — Function reserved. SD_DAT2 — SD/MMC data bus line 2. O O I/O I/O I O I/O I/O I O I/O I/O P1_9 T7 x J5 x 52 37 [3] I; PU I/O P1_10 R8 x H6 x 53 38 [3] I; PU I/O P1_11 T9 x J7 x 55 39 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 11 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P1_12 R9 x K7 x 56 40 [3] I; PU I/O I I/O I I/O Type GPIO1[5] — General purpose digital input/output pin. U1_DCD — Data Carrier Detect input for UART1. R — Function reserved. EMC_D5 — External memory data line 5. T0_CAP1 — Capture input 1 of timer 0. R — Function reserved. R — Function reserved. SD_DAT3 — SD/MMC data bus line 3. GPIO1[6] — General purpose digital input/output pin. U1_TXD — Transmitter output for UART1. R — Function reserved. EMC_D6 — External memory data line 6. T0_CAP0 — Capture input 0 of timer 0. R — Function reserved. R — Function reserved. SD_CD — SD/MMC card detect input. GPIO1[7] — General purpose digital input/output pin. U1_RXD — Receiver input for UART1. R — Function reserved. EMC_D7 — External memory data line 7. T0_MAT2 — Match output 2 of timer 0. R — Function reserved. R — Function reserved. R — Function reserved. GPIO0[2] — General purpose digital input/output pin. U2_TXD — Transmitter output for USART2. R — Function reserved. ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). T0_MAT1 — Match output 1 of timer 0. R — Function reserved. R — Function reserved. R — Function reserved. O I/O I I I I/O O O I O - P1_13 R10 x H8 x 60 41 [3] I; PU I/O P1_14 R11 x J8 x 61 42 [3] I; PU I/O P1_15 T12 x K8 x 62 43 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 12 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P1_16 M7 x H9 x 64 44 [3] I; PU I/O I I O I Type GPIO0[3] — General purpose digital input/output pin. U2_RXD — Receiver input for USART2. R — Function reserved. ENET_CRS — Ethernet Carrier Sense (MII interface). T0_MAT0 — Match output 0 of timer 0. R — Function reserved. R — Function reserved. ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). GPIO0[12] — General purpose digital input/output pin. U2_UCLK — Serial clock input/output for USART2 in synchronous mode. R — Function reserved. ENET_MDIO — Ethernet MIIM data input and output. T0_CAP3 — Capture input 3 of timer 0. CAN1_TD — CAN1 transmitter output. R — Function reserved. R — Function reserved. GPIO0[13] — General purpose digital input/output pin. U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. R — Function reserved. ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). T0_MAT3 — Match output 3 of timer 0. CAN1_RD — CAN1 receiver input. R — Function reserved. R — Function reserved. I/O I/O I O I/O O O I - P1_17 M8 x H10 x 66 45 [4] I; PU I/O P1_18 N12 x J10 x 67 46 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 13 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P1_19 M11 x K9 x 68 47 [3] I; PU I Type ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). SSP1_SCK — Serial clock for SSP1. R — Function reserved. R — Function reserved. CLKOUT — Clock output pin. R — Function reserved. I2S0_RX_MCLK — I2S receive master clock. I2S1_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. GPIO0[15] — General purpose digital input/output pin. SSP1_SSEL — Slave Select for SSP1. R — Function reserved. ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). T0_CAP2 — Capture input 2 of timer 0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. U0_TXD — Transmitter output for USART0. EMC_A13 — External memory address line 13. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active high). GPIO5[0] — General purpose digital input/output pin. R — Function reserved. T3_CAP0 — Capture input 0 of timer 3. ENET_MDC — Ethernet MIIM clock. I/O O O I/O I/O O I O I/O O I/O I O P1_20 M10 x K10 x 70 48 [3] I; PU I/O P2_0 T16 x G10 x 75 50 [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 14 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P2_1 N15 x G7 x 81 54 [3] I; PU I I/O O Type R — Function reserved. U0_RXD — Receiver input for USART0. EMC_A12 — External memory address line 12. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). GPIO5[1] — General purpose digital input/output pin. R — Function reserved. T3_CAP1 — Capture input 1 of timer 3. R — Function reserved. R — Function reserved. U0_UCLK — Serial clock input/output for USART0 in synchronous mode. EMC_A11 — External memory address line 11. USB0_IND1 — USB0 port indicator LED control output 1. GPIO5[2] — General purpose digital input/output pin. CTIN_6 — SCT input 6. Capture input 1 of timer 3. T3_CAP2 — Capture input 2 of timer 3. R — Function reserved. R — Function reserved. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). U3_TXD — Transmitter output for USART3. CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. GPIO5[3] — General purpose digital input/output pin. R — Function reserved. T3_MAT0 — Match output 0 of timer 3. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active HIGH). I/O I I/O I/O O I/O I I I/O O I I/O O O P2_2 M15 x F5 x 84 56 [3] I; PU - P2_3 J12 x D8 x 87 57 [4] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 15 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P2_4 K11 x D9 x 88 58 [4] I; PU I/O I I I/O O O Type R — Function reserved. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). U3_RXD — Receiver input for USART3. CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. GPIO5[4] — General purpose digital input/output pin. R — Function reserved. T3_MAT1 — Match output 1 of timer 3. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). R — Function reserved. CTIN_2 — SCT input 2. Capture input 2 of timer 0. USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur. I I/O O O ADCTRIG1 — ADC trigger input 1. GPIO5[5] — General purpose digital input/output pin. R — Function reserved. T3_MAT2 — Match output 2 of timer 3. USB0_IND0 — USB0 port indicator LED control output 0. R — Function reserved. U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. EMC_A10 — External memory address line 10. USB0_IND0 — USB0 port indicator LED control output 0. GPIO5[6] — General purpose digital input/output pin. CTIN_7 — SCT input 7. T3_CAP3 — Capture input 3 of timer 3. R — Function reserved. I I I/O I/O O I/O I I - P2_5 K14 x D10 x 91 61 [4] I; PU - P2_6 K16 x G9 x 95 64 [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 16 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P2_7 H14 x C10 x 96 65 [3] I; PU I/O Type GPIO0[7] — General purpose digital input/output pin. ISP entry pin. If this pin is pulled LOW at reset, the part enters ISP mode using USART0. CTOUT_1 — SCT output 1. Match output 1 of timer 0. U3_UCLK — Serial clock input/output for USART3 in synchronous mode. EMC_A9 — External memory address line 9. R — Function reserved. R — Function reserved. T3_MAT3 — Match output 3 of timer 3. R — Function reserved. R — Function reserved. Boot pin (see Table 5) CTOUT_0 — SCT output 0. Match output 0 of timer 0. U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. EMC_A8 — External memory address line 8. GPIO5[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 5). CTOUT_3 — SCT output 3. Match output 3 of timer 0. U3_BAUD — for USART3. EMC_A0 — External memory address line 0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO0[14] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U2_TXD — Transmitter output for USART2. EMC_A1 — External memory address line 1. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. O I/O I/O O O I/O I/O I/O O I/O I/O O O I/O - P2_8 J16 x C6 x 98 67 [3] I; PU - P2_9 H16 x B10 x 102 70 [3] I; PU I/O P2_10 G16 x E8 x 104 71 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 17 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P2_11 F16 x A9 x 105 72 [3] I; PU I/O O I I/O - Type GPIO1[11] — General purpose digital input/output pin. CTOUT_5 — SCT output 5. Match output 1 of timer 1. U2_RXD — Receiver input for USART2. EMC_A2 — External memory address line 2. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO1[12] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 0 of timer 1. R — Function reserved. EMC_A3 — External memory address line 3. R — Function reserved. R — Function reserved. R — Function reserved. U2_UCLK — Serial clock input/output for USART2 in synchronous mode. GPIO1[13] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. R — Function reserved. EMC_A4 — External memory address line 4. R — Function reserved. R — Function reserved. R — Function reserved. U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. I2S0_RX_SCK — I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S0_RX_MCLK — I2S receive master clock. I2S0_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S0_TX_MCLK — I2S transmit master clock. SSP0_SCK — Serial clock for SSP0. R — Function reserved. R — Function reserved. R — Function reserved. O I/O I/O I I/O I/O O I/O O I/O - P2_12 E15 x B9 x 106 73 [3] I; PU I/O P2_13 C16 x A10 x 108 75 [3] I; PU I/O P3_0 F13 x A8 x 112 78 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 18 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P3_1 G11 x F7 x 114 79 [3] I; PU I/O Type I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. CAN0_RD — CAN receiver input. USB1_IND1 — USB1 Port indicator LED control output 1. GPIO5[8] — General purpose digital input/output pin. R — Function reserved. LCD_VD15 — LCD data. R — Function reserved. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. CAN0_TD — CAN transmitter output. USB1_IND0 — USB1 Port indicator LED control output 0. GPIO5[9] — General purpose digital input/output pin. R — Function reserved. LCD_VD14 — LCD data. R — Function reserved. R — Function reserved. R — Function reserved. SSP0_SCK — Serial clock for SSP0. SPIFI_SCK — Serial clock for SPIFI. CGU_OUT1 — CGU spare clock output 1. R — Function reserved. I2S0_TX_MCLK — I2S transmit master clock. I2S1_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O I O I/O O I/O O O I/O O I/O O O O I/O P3_2 F11 x G6 x 116 80 [3] I; PU I/O P3_3 B14 x A7 x 118 81 [5] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 19 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P3_4 A15 x B8 x 119 82 [3] I; PU I/O I/O O I/O Type GPIO1[14] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SPIFI_SIO3 — I/O lane 3 for SPIFI. U1_TXD — Transmitter output for UART1. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. LCD_VD13 — LCD data. GPIO1[15] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SPIFI_SIO2 — I/O lane 2 for SPIFI. U1_RXD — Receiver input for UART1. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I2S1_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. LCD_VD12 — LCD data. GPIO0[6] — General purpose digital input/output pin. R — Function reserved. SSP0_SSEL — Slave Select for SSP0. SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1. R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved. R — Function reserved. I/O O I/O I I/O I/O O I/O I/O I/O - P3_5 C12 x B7 x 121 84 [3] I; PU I/O P3_6 B13 x C7 x 122 85 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 20 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P3_7 C11 x D7 x 123 86 [3] I; PU I/O I/O I/O I/O - Type R — Function reserved. R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. SPIFI_MOSI — Input 0 in SPIFI quad mode; SPIFI output IO0. GPIO5[10] — General purpose digital input/output pin. SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. SSP0_MOSI — Master Out Slave in for SSP0. SPIFI_CS — SPIFI serial flash chip select. GPIO5[11] — General purpose digital input/output pin. SSP0_SSEL — Slave Select for SSP0. R — Function reserved. R — Function reserved. GPIO2[0] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. NMI — External interrupt input to NMI. R — Function reserved. R — Function reserved. LCD_VD13 — LCD data. U3_UCLK — Serial clock input/output for USART3 in synchronous mode. R — Function reserved. GPIO2[1] — General purpose digital input/output pin. CTOUT_1 — SCT output 1. Match output 1 of timer 0. LCD_VD0 — LCD data. R — Function reserved. R — Function reserved. LCD_VD19 — LCD data. U3_TXD — Transmitter output for USART3. ENET_COL — Ethernet Collision detect (MII interface). ADC0_1 — ADC0, input channel 1. I/O I/O I/O I/O O I O I/O O O O O I I P3_8 C10 x E7 x 124 87 [3] I; PU - P4_0 D5 x - x 1 - [3] I; PU I/O P4_1 A1 x - x 3 - [6] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 21 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P4_2 D3 x - x 8 - [3] I; PU I/O O O O I - Type GPIO2[2] — General purpose digital input/output pin. CTOUT_0 — SCT output 0. Match output 0 of timer 0. LCD_VD3 — LCD data. R — Function reserved. R — Function reserved. LCD_VD12 — LCD data. U3_RXD — Receiver input for USART3. R — Function reserved. GPIO2[3] — General purpose digital input/output pin. CTOUT_3 — SCT output 0. Match output 3 of timer 0. LCD_VD2 — LCD data. R — Function reserved. R — Function reserved. LCD_VD21 — LCD data. U3_BAUD — for USART3. R — Function reserved. ADC0_0 — ADC0, input channel 0. GPIO2[4] — General purpose digital input/output pin. CTOUT_2 — SCT output 2. Match output 2 of timer 0. LCD_VD1 — LCD data. R — Function reserved. R — Function reserved. LCD_VD20 — LCD data. U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. R — Function reserved. DAC — DAC output. GPIO2[5] — General purpose digital input/output pin. CTOUT_5 — SCT output 5. Match output 1 of timer 1. LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. O O O I/O I O O O I/O O O O - P4_3 C2 x - x 7 - [6] I; PU I/O P4_4 B1 x - x 9 - [6] I; PU I/O P4_5 D2 x - x 10 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 22 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P4_6 C1 x - x 11 - [3] I; PU I/O O O - Type GPIO2[6] — General purpose digital input/output pin. CTOUT_4 — SCT output 4. Match output 0 of timer 1. LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. LCD_DCLK — LCD panel clock. GP_CLKIN — General purpose clock input to the CGU. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I2S1_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I2S0_TX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. LCD_VD9 — LCD data. R — Function reserved. GPIO5[12] — General purpose digital input/output pin. LCD_VD22 — LCD data. CAN1_TD — CAN1 transmitter output. R — Function reserved. R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3. LCD_VD11 — LCD data. R — Function reserved. GPIO5[13] — General purpose digital input/output pin. LCD_VD15 — LCD data. CAN1_RD — CAN1 receiver input. R — Function reserved. I/O I/O I O I/O O O I O I/O O I - P4_7 H4 x - x 14 - [3] I P4_8 E2 x - x 15 - [3] I; PU - P4_9 L2 x - x 33 - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 23 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P4_10 M3 x - x 35 - [3] I; PU I O I/O O - Type R — Function reserved. CTIN_2 — SCT input 2. Capture input 2 of timer 0. LCD_VD10 — LCD data. R — Function reserved. GPIO5[14] — General purpose digital input/output pin. LCD_VD14 — LCD data. R — Function reserved. R — Function reserved. GPIO2[9] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. EMC_D12 — External memory data line 12. R — Function reserved. U1_DSR — Data Set Ready input for UART1. T1_CAP0 — Capture input 0 of timer 1. R — Function reserved. R — Function reserved. GPIO2[10] — General purpose digital input/output pin. MCI2 — Motor control PWM channel 2, input. EMC_D13 — External memory data line 13. R — Function reserved. U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. T1_CAP1 — Capture input 1 of timer 1. R — Function reserved. R — Function reserved. GPIO2[11] — General purpose digital input/output pin. MCI1 — Motor control PWM channel 1, input. EMC_D14 — External memory data line 14. R — Function reserved. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. T1_CAP2 — Capture input 2 of timer 1. R — Function reserved. R — Function reserved. O I/O I I I I/O O I I I/O O I - P5_0 N3 x - x 37 - [3] I; PU I/O P5_1 P3 x - x 39 - [3] I; PU I/O P5_2 R4 x - x 46 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 24 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P5_3 T8 x - x 54 - [3] I; PU I/O I I/O I I - Type GPIO2[12] — General purpose digital input/output pin. MCI0 — Motor control PWM channel 0, input. EMC_D15 — External memory data line 15. R — Function reserved. U1_RI — Ring Indicator input for UART1. T1_CAP3 — Capture input 3 of timer 1. R — Function reserved. R — Function reserved. GPIO2[13] — General purpose digital input/output pin. MCOB0 — Motor control PWM channel 0, output B. EMC_D8 — External memory data line 8. R — Function reserved. U1_CTS — Clear to Send input for UART1. T1_MAT0 — Match output 0 of timer 1. R — Function reserved. R — Function reserved. GPIO2[14] — General purpose digital input/output pin. MCOA1 — Motor control PWM channel 1, output A. EMC_D9 — External memory data line 9. R — Function reserved. U1_DCD — Data Carrier Detect input for UART1. T1_MAT1 — Match output 1 of timer 1. R — Function reserved. R — Function reserved. GPIO2[15] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. EMC_D10 — External memory data line 10. R — Function reserved. U1_TXD — Transmitter output for UART1. T1_MAT2 — Match output 2 of timer 1. R — Function reserved. R — Function reserved. O I/O I O O I/O I O O I/O O O - P5_4 P9 x - x 57 - [3] I; PU I/O P5_5 P10 x - x 58 - [3] I; PU I/O P5_6 T13 x - x 63 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 25 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P5_7 R12 x - x 65 - [3] I; PU I/O O I/O I O - Type GPIO2[7] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A. EMC_D11 — External memory data line 11. R — Function reserved. U1_RXD — Receiver input for UART1. T1_MAT3 — Match output 3 of timer 1. R — Function reserved. R — Function reserved. R — Function reserved. I2S0_RX_MCLK — I2S receive master clock. R — Function reserved. R — Function reserved. I2S0_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[0] — General purpose digital input/output pin. EMC_DYCS1 — SDRAM chip select 1. U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I2S0_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. R — Function reserved. T2_CAP0 — Capture input 2 of timer 2. R — Function reserved. R — Function reserved. O I/O O I/O I/O I - P6_0 M12 x H7 x 73 - [3] I; PU - P6_1 R15 x G5 x 74 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 26 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P6_2 L13 x J9 x 78 - [3] I; PU I/O O I/O I/O Type GPIO3[1] — General purpose digital input/output pin. EMC_CKEOUT1 — SDRAM clock enable 1. U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I2S0_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. R — Function reserved. T2_CAP1 — Capture input 1 of timer 2. R — Function reserved. R — Function reserved. GPIO3[2] — General purpose digital input/output pin. USB0_PWR_EN — VBUS drive signal (towards external charge pump or power management unit); indicates that the VBUS signal must be driven (active HIGH). R — Function reserved. EMC_CS1 — LOW active Chip Select 1 signal. R — Function reserved. T2_CAP2 — Capture input 2 of timer 2. R — Function reserved. R — Function reserved. GPIO3[3] — General purpose digital input/output pin. CTIN_6 — SCT input 6. Capture input 1 of timer 3. U0_TXD — Transmitter output for USART0. EMC_CAS — LOW active SDRAM Column Address Strobe. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I O O I I O O - P6_3 P15 x - x 79 - [3] I; PU I/O P6_4 R16 x F6 x 80 53 [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 27 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P6_5 P16 x F9 x 82 55 [3] I; PU I/O O I O - Type GPIO3[4] — General purpose digital input/output pin. CTOUT_6 — SCT output 6. Match output 2 of timer 1. U0_RXD — Receiver input for USART0. EMC_RAS — LOW active SDRAM Row Address Strobe. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO0[5] — General purpose digital input/output pin. EMC_BLS1 — LOW active Byte Lane select signal 1. R — Function reserved. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). R — Function reserved. T2_CAP3 — Capture input 3 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A15 — External memory address line 15. R — Function reserved. USB0_IND1 — USB0 port indicator LED control output 1. GPIO5[15] — General purpose digital input/output pin. T2_MAT0 — Match output 0 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A14 — External memory address line 14. R — Function reserved. USB0_IND0 — USB0 port indicator LED control output 0. GPIO5[16] — General purpose digital input/output pin. T2_MAT1 — Match output 1 of timer 2. R — Function reserved. R — Function reserved. O O I I/O O I/O O I/O O I/O O - P6_6 L14 x - x 83 - [3] I; PU I/O P6_7 J13 x - x 85 - [3] I; PU - P6_8 H13 x - x 86 - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 28 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P6_9 J15 x F8 x 97 66 [3] I; PU I/O O O - Type GPIO3[5] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. EMC_DYCS0 — SDRAM chip select 0. R — Function reserved. T2_MAT2 — Match output 2 of timer 2. R — Function reserved. R — Function reserved. GPIO3[6] — General purpose digital input/output pin. MCABORT — Motor control PWM, LOW-active fast abort. R — Function reserved. EMC_DQMOUT1 — Data mask 1 used with SDRAM and static devices. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. EMC_CKEOUT0 — SDRAM clock enable 0. R — Function reserved. T2_MAT3 — Match output 2 of timer 3. R — Function reserved. R — Function reserved. GPIO2[8] — General purpose digital input/output pin. CTOUT_7 — SCT output 7. Match output 3 of timer 1. R — Function reserved. EMC_DQMOUT0 — Data mask 0 used with SDRAM and static devices. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. O O O O O O - P6_10 H15 x - x 100 - [3] I; PU I/O P6_11 H12 x C9 x 101 69 [3] I; PU I/O P6_12 G15 x - x 103 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 29 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P7_0 B16 x - x 110 - [3] I; PU I/O O O - Type GPIO3[8] — General purpose digital input/output pin. CTOUT_14 — SCT output 14. Match output 2 of timer 3. R — Function reserved. LCD_LE — Line end signal. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO3[9] — General purpose digital input/output pin. CTOUT_15 — SCT output 15. Match output 3 of timer 3. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. LCD_VD19 — LCD data. LCD_VD7 — LCD data. R — Function reserved. U2_TXD — Transmitter output for USART2. R — Function reserved. GPIO3[10] — General purpose digital input/output pin. CTIN_4 — SCT input 4. Capture input 2 of timer 1. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. LCD_VD18 — LCD data. LCD_VD6 — LCD data. R — Function reserved. U2_RXD — Receiver input for USART2. R — Function reserved. GPIO3[11] — General purpose digital input/output pin. CTIN_3 — SCT input 3. Capture input 1 of timer 1. R — Function reserved. LCD_VD17 — LCD data. LCD_VD5 — LCD data. R — Function reserved. R — Function reserved. R — Function reserved. O I/O O O O I I/O O O I I O O - P7_1 C14 x - x 113 - [3] I; PU I/O P7_2 A16 x - x 115 - [3] I; PU I/O P7_3 C13 x - x 117 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 30 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P7_4 C8 x - x 132 - [6] I; PU I/O O O O O I Type GPIO3[12] — General purpose digital input/output pin. CTOUT_13 — SCT output 13. Match output 1 of timer 3. R — Function reserved. LCD_VD16 — LCD data. LCD_VD4 — LCD data. TRACEDATA[0] — Trace data, bit 0. R — Function reserved. R — Function reserved. ADC0_4 — ADC0, input channel 4. GPIO3[13] — General purpose digital input/output pin. CTOUT_12 — SCT output 12. Match output 0 of timer 3. R — Function reserved. LCD_VD8 — LCD data. LCD_VD23 — LCD data. TRACEDATA[1] — Trace data, bit 1. R — Function reserved. R — Function reserved. ADC0_3 — ADC0, input channel 3. GPIO3[14] — General purpose digital input/output pin. CTOUT_11 — SCT output 1. Match output 3 of timer 2. R — Function reserved. LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). R — Function reserved. TRACEDATA[2] — Trace data, bit 2. R — Function reserved. R — Function reserved. O O O O I O O O - P7_5 A7 x - x 133 - [6] I; PU I/O P7_6 C7 x - x 134 - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 31 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P7_7 B6 x - x 140 - [6] I; PU I/O O O O O I Type GPIO3[15] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. LCD_PWR — LCD panel power enable. R — Function reserved. TRACEDATA[3] — Trace data, bit 3. ENET_MDC — Ethernet MIIM clock. R — Function reserved. ADC1_6 — ADC1, input channel 6. GPIO4[0] — General purpose digital input/output pin. USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition; this signal monitors over-current on the USB bus (external circuitry required to detect over-current condition). R — Function reserved. MCI2 — Motor control PWM channel 2, input. R — Function reserved. R — Function reserved. R — Function reserved. T0_MAT0 — Match output 0 of timer 0. GPIO4[1] — General purpose digital input/output pin. USB0_IND1 — USB0 port indicator LED control output 1. R — Function reserved. MCI1 — Motor control PWM channel 1, input. R — Function reserved. R — Function reserved. R — Function reserved. T0_MAT1 — Match output 1 of timer 0. GPIO4[2] — General purpose digital input/output pin. USB0_IND0 — USB0 port indicator LED control output 0. R — Function reserved. MCI0 — Motor control PWM channel 0, input. R — Function reserved. R — Function reserved. R — Function reserved. T0_MAT2 — Match output 2 of timer 0. © NXP B.V. 2011. All rights reserved. P8_0 E5 x - x - - [4] I; PU I/O O [2] I O P8_1 H5 x x [4] I; PU I/O O I O P8_2 K4 x - x - - [4] I; PU I/O O I O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 32 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P8_3 J3 x - x - - [3] I; PU I/O I/O O O O Type GPIO4[3] — General purpose digital input/output pin. USB1_ULPI_D2 — ULPI link bidirectional data line 2. R — Function reserved. LCD_VD12 — LCD data. LCD_VD19 — LCD data. R — Function reserved. R — Function reserved. T0_MAT3 — Match output 3 of timer 0. GPIO4[4] — General purpose digital input/output pin. USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved. LCD_VD7 — LCD data. LCD_VD16 — LCD data. R — Function reserved. R — Function reserved. T0_CAP0 — Capture input 0 of timer 0. GPIO4[5] — General purpose digital input/output pin. USB1_ULPI_D0 — ULPI link bidirectional data line 0. R — Function reserved. LCD_VD6 — LCD data. LCD_VD8 — LCD data. R — Function reserved. R — Function reserved. T0_CAP1 — Capture input 1 of timer 0. GPIO4[6] — General purpose digital input/output pin. USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. R — Function reserved. LCD_VD5 — LCD data. LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). R — Function reserved. R — Function reserved. T0_CAP2 — Capture input 2 of timer 0. I/O O O I I/O O O I I O O I P8_4 J2 x - x - - [3] I; PU I/O P8_5 J1 x - x - - [3] I; PU I/O P8_6 K3 x - x - - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 33 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P8_7 K1 x - x - - [3] I; PU I/O O O O I Type GPIO4[7] — General purpose digital input/output pin. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. R — Function reserved. LCD_VD4 — LCD data. LCD_PWR — LCD panel power enable. R — Function reserved. R — Function reserved. T0_CAP3 — Capture input 3 of timer 0. R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CGU_OUT0 — CGU spare clock output 0. I2S1_TX_MCLK — I2S1 transmit master clock. GPIO4[12] — General purpose digital input/output pin. MCABORT — Motor control PWM, LOW-active fast abort. R — Function reserved. R — Function reserved. R — Function reserved. ENET_CRS — Ethernet Carrier Sense (MII interface). R — Function reserved. SSP0_SSEL — Slave Select for SSP0. GPIO4[13] — General purpose digital input/output pin. MCOA2 — Motor control PWM channel 2, output A. R — Function reserved. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. ENET_RX_ER — Ethernet receive error (MII interface). R — Function reserved. SSP0_MISO — Master In Slave Out for SSP0. I O O O I I/O O I/O I I/O P8_8 L1 x - x - - [3] I; PU - P9_0 T1 x - x - - [3] I; PU I/O P9_1 N6 x - x - - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 34 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P9_2 N8 x - x - - [3] I; PU I/O O I/O Type GPIO4[14] — General purpose digital input/output pin. MCOB2 — Motor control PWM channel 2, output B. R — Function reserved. R — Function reserved. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. ENET_RXD3 — Ethernet receive data 3 (MII interface). R — Function reserved. SSP0_MOSI — Master Out Slave in for SSP0. GPIO4[15] — General purpose digital input/output pin. MCOA0 — Motor control PWM channel 0, output A. USB1_IND1 — USB1 Port indicator LED control output 1. R — Function reserved. R — Function reserved. ENET_RXD2 — Ethernet receive data 2 (MII interface). R — Function reserved. U3_TXD — Transmitter output for USART3. R — Function reserved. MCOB0 — Motor control PWM channel 0, output B. USB1_IND0 — USB1 Port indicator LED control output 0. R — Function reserved. GPIO5[17] — General purpose digital input/output pin. ENET_TXD2 — Ethernet transmit data 2 (MII interface). R — Function reserved. U3_RXD — Receiver input for USART3. I I/O O O I O O O I/O O I P9_3 M6 x - x - - [3] I; PU I/O P9_4 N10 x - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 35 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 P9_5 M9 x - x 69 - [3] I; PU O O I/O O O Type R — Function reserved. MCOA1 — Motor control PWM channel 1, output A. USB1_VBUS_EN — USB1 VBUS power enable. R — Function reserved. GPIO5[18] — General purpose digital input/output pin. ENET_TXD3 — Ethernet transmit data 3 (MII interface). R — Function reserved. U0_TXD — Transmitter output for USART0. GPIO4[11] — General purpose digital input/output pin. MCOB1 — Motor control PWM channel 1, output B. USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current condition; this signal monitors over-current on the USB1 bus (external circuitry required to detect over-current condition). R — Function reserved. R — Function reserved. ENET_COL — Ethernet Collision detect (MII interface). R — Function reserved. U0_RXD — Receiver input for USART0. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I2S1_RX_MCLK — I2S1 receive master clock. CGU_OUT1 — CGU spare clock output 1. R — Function reserved. GPIO4[8] — General purpose digital input/output pin. QEI_IDX — Quadrature Encoder Interface INDEX input. R — Function reserved. U2_TXD — Transmitter output for USART2. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. O O I I O O I O - P9_6 L11 x - x 72 - [3] I; PU I/O PA_0 L12 x - x - - [3] I; PU - PA_1 J14 x - x - - [4] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 36 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PA_2 K15 x - x - - [4] I; PU I/O I I - Type GPIO4[9] — General purpose digital input/output pin. QEI_PHB — Quadrature Encoder Interface PHB input. R — Function reserved. U2_RXD — Receiver input for USART2. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. GPIO4[10] — General purpose digital input/output pin. QEI_PHA — Quadrature Encoder Interface PHA input. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_9 — SCT output 9. Match output 1 of timer 2. R — Function reserved. EMC_A23 — External memory address line 23. GPIO5[19] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_10 — SCT output 10. Match output 2 of timer 2. LCD_VD23 — LCD data. R — Function reserved. GPIO5[20] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. I O I/O I/O O O I/O - PA_3 H11 x - x - - [4] I; PU I/O PA_4 G13 x - x - - [3] I; PU - PB_0 B15 x - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 37 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PB_1 A14 x - x - - [3] I; PU I O I/O O - Type R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. LCD_VD22 — LCD data. R — Function reserved. GPIO5[21] — General purpose digital input/output pin. CTOUT_6 — SCT output 6. Match output 2 of timer 1. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_D7 — ULPI link bidirectional data line 7. LCD_VD21 — LCD data. R — Function reserved. GPIO5[22] — General purpose digital input/output pin. CTOUT_7 — SCT output 7. Match output 3 of timer 1. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_D6 — ULPI link bidirectional data line 6. LCD_VD20 — LCD data. R — Function reserved. GPIO5[23] — General purpose digital input/output pin. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. USB1_ULPI_D5 — ULPI link bidirectional data line 5. LCD_VD15 — LCD data. R — Function reserved. GPIO5[24] — General purpose digital input/output pin. CTIN_5 — SCT input 5. Capture input 2 of timer 2. R — Function reserved. R — Function reserved. I/O O I/O O I/O O I/O O I/O O I/O I - PB_2 B12 x - x - - [3] I; PU - PB_3 A13 x - x - - [3] I; PU - PB_4 B11 x - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 38 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PB_5 A12 x - x - - [3] I; PU I/O O I/O I O - Type R — Function reserved. USB1_ULPI_D4 — ULPI link bidirectional data line 4. LCD_VD14 — LCD data. R — Function reserved. GPIO5[25] — General purpose digital input/output pin. CTIN_7 — SCT input 7. LCD_PWR — LCD panel power enable. R — Function reserved. R — Function reserved. USB1_ULPI_D3 — ULPI link bidirectional data line 3. LCD_VD13 — LCD data. R — Function reserved. GPIO5[26] — General purpose digital input/output pin. CTIN_6 — SCT input 6. Capture input 1 of timer 3. LCD_VD19 — LCD data. R — Function reserved. ADC0_6 — ADC0, input channel 6. R — Function reserved. USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock generated by the PHY. R — Function reserved. ENET_RX_CLK — Ethernet Receive Clock (MII interface). LCD_DCLK — LCD panel clock. R — Function reserved. R — Function reserved. SD_CLK — SD/MMC card clock. ADC1_1 — ADC1, input channel 1. USB1_ULPI_D7 — ULPI link bidirectional data line 7. R — Function reserved. U1_RI — Ring Indicator input for UART1. ENET_MDC — Ethernet MIIM clock. GPIO6[0] — General purpose digital input/output pin. R — Function reserved. T3_CAP0 — Capture input 0 of timer 3. SD_VOLT0 — SD/MMC bus voltage select output 0. I/O O I/O I O I I I/O O I/O I I O I/O I O PB_6 A6 x - x - - [6] I; PU - PC_0 D4 x - x - - [6] I; PU - PC_1 E4 - - x - - [3] I; PU I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 39 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PC_2 F6 - - x - - [3] I; PU I/O I O I/O O Type USB1_ULPI_D6 — ULPI link bidirectional data line 6. R — Function reserved. U1_CTS — Clear to Send input for UART1. ENET_TXD2 — Ethernet transmit data 2 (MII interface). GPIO6[1] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SD_RST — SD/MMC reset signal for MMC4.4 card. USB1_ULPI_D5 — ULPI link bidirectional data line 5. R — Function reserved. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. ENET_TXD3 — Ethernet transmit data 3 (MII interface). GPIO6[2] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SD_VOLT1 — SD/MMC bus voltage select output 1. ADC1_0 — ADC1, input channel 0. R — Function reserved. USB1_ULPI_D4 — ULPI link bidirectional data line 4. R — Function reserved. ENET_TX_EN — Ethernet transmit enable (RMII/MII interface). I/O I I/O GPIO6[3] — General purpose digital input/output pin. R — Function reserved. T3_CAP1 — Capture input 1 of timer 3. SD_DAT0 — SD/MMC data bus line 0. R — Function reserved. USB1_ULPI_D3 — ULPI link bidirectional data line 3. R — Function reserved. ENET_TX_ER — Ethernet Transmit Error (MII interface). GPIO6[4] — General purpose digital input/output pin. R — Function reserved. T3_CAP2 — Capture input 2 of timer 3. SD_DAT1 — SD/MMC data bus line 1. © NXP B.V. 2011. All rights reserved. PC_3 F5 - - x - - [6] I; PU I/O O [2] O I/O O I PC_4 F4 x [3] I; PU I/O - PC_5 G4 - - x - - [3] I; PU I/O O I/O I I/O LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 40 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PC_6 H6 - - x - - [3] I; PU I/O I I/O I I/O Type R — Function reserved. USB1_ULPI_D2 — ULPI link bidirectional data line 2. R — Function reserved. ENET_RXD2 — Ethernet receive data 2 (MII interface). GPIO6[5] — General purpose digital input/output pin. R — Function reserved. T3_CAP3 — Capture input 3 of timer 3. SD_DAT2 — SD/MMC data bus line 2. R — Function reserved. USB1_ULPI_D1 — ULPI link bidirectional data line 1. R — Function reserved. ENET_RXD3 — Ethernet receive data 3 (MII interface). GPIO6[6] — General purpose digital input/output pin. R — Function reserved. T3_MAT0 — Match output 0 of timer 3. SD_DAT3 — SD/MMC data bus line 3. R — Function reserved. USB1_ULPI_D0 — ULPI link bidirectional data line 0. R — Function reserved. ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII interface). GPIO6[7] — General purpose digital input/output pin. R — Function reserved. T3_MAT1 — Match output 1 of timer 3. SD_CD — SD/MMC card detect input. R — Function reserved. USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. R — Function reserved. ENET_RX_ER — Ethernet receive error (MII interface). GPIO6[8] — General purpose digital input/output pin. R — Function reserved. T3_MAT2 — Match output 2 of timer 3. SD_POW — . I/O I I/O O I/O I/O I I/O O I I I I/O O O PC_7 G5 - - - - - [3] I; PU - PC_8 N4 - - - - - [3] I; PU - PC_9 K2 - - - - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 41 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PC_10 M5 - - - - - [3] I; PU O I I/O O I/O Type R — Function reserved. USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. U1_DSR — Data Set Ready input for UART1. R — Function reserved. GPIO6[9] — General purpose digital input/output pin. R — Function reserved. T3_MAT3 — Match output 3 of timer 3. SD_CMD — SD/MMC command signal. R — Function reserved. USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. U1_DCD — Data Carrier Detect input for UART1. R — Function reserved. GPIO6[10] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. SD_DAT4 — SD/MMC data bus line 4. R — Function reserved. R — Function reserved. U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. R — Function reserved. GPIO6[11] — General purpose digital input/output pin. R — Function reserved. I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. SD_DAT5 — SD/MMC data bus line 5. I I I/O I/O O I/O I/O I/O PC_11 L5 - - - - - [3] I; PU - PC_12 L6 - - - - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 42 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PC_13 M1 - - - - - [3] I; PU O I/O I/O Type R — Function reserved. R — Function reserved. U1_TXD — Transmitter output for UART1. R — Function reserved. GPIO6[12] — General purpose digital input/output pin. R — Function reserved. I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. SD_DAT6 — SD/MMC data bus line 6. R — Function reserved. R — Function reserved. U1_RXD — Receiver input for UART1. R — Function reserved. GPIO6[13] — General purpose digital input/output pin. R — Function reserved. ENET_TX_ER — Ethernet Transmit Error (MII interface). SD_DAT7 — SD/MMC data bus line 7. R — Function reserved. CTOUT_15 — SCT output 15. Match output 3 of timer 3. EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices. R — Function reserved. GPIO6[14] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_CKEOUT2 — SDRAM clock enable 2. R — Function reserved. GPIO6[15] — General purpose digital input/output pin. SD_POW — . R — Function reserved. R — Function reserved. I/O I I/O O I/O O O I/O O I/O O - PC_14 N1 - - - - - [3] I; PU - PD_0 N2 - - - - - [3] I; PU - PD_1 P1 - - - - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 43 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PD_2 R1 - - - - - [3] I; PU O I/O I/O - Type R — Function reserved. CTOUT_7 — SCT output 7. Match output 3 of timer 1. EMC_D16 — External memory data line 16. R — Function reserved. GPIO6[16] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_6 — SCT output 7. Match output 2 of timer 1. EMC_D17 — External memory data line 17. R — Function reserved. GPIO6[17] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_8 — SCT output 8. Match output 0 of timer 2. EMC_D18 — External memory data line 18. R — Function reserved. GPIO6[18] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_9 — SCT output 9. Match output 1 of timer 2. EMC_D19 — External memory data line 19. R — Function reserved. GPIO6[19] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. O I/O I/O O I/O I/O O I/O I/O - PD_3 P4 - - - - - [3] I; PU - PD_4 T2 - - - - - [3] I; PU - PD_5 P6 - - - - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 44 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PD_6 R6 - - x - - [3] I; PU O I/O I/O - Type R — Function reserved. CTOUT_10 — SCT output 10. Match output 2 of timer 2. EMC_D20 — External memory data line 20. R — Function reserved. GPIO6[20] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTIN_5 — SCT input 5. Capture input 2 of timer 2. EMC_D21 — External memory data line 21. R — Function reserved. GPIO6[21] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTIN_6 — SCT input 6. Capture input 1 of timer 3. EMC_D22 — External memory data line 22. R — Function reserved. GPIO6[22] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_13 — SCT output 13. Match output 1 of timer 3. EMC_D23 — External memory data line 23. R — Function reserved. GPIO6[23] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. I I/O I/O I I/O I/O O I/O I/O - PD_7 T6 - - x - - [3] I; PU - PD_8 P8 - - x - - [3] I; PU - PD_9 T11 - - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 45 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PD_10 P11 - - x - - [3] I; PU I Type R — Function reserved. CTIN_1 — SCT input 1. Capture input 1 of timer 0. Capture input 1 of timer 2. EMC_BLS3 — LOW active Byte Lane select signal 3. R — Function reserved. GPIO6[24] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_CS3 — LOW active Chip Select 3 signal. R — Function reserved. GPIO6[25] — General purpose digital input/output pin. USB1_ULPI_D0 — ULPI link bidirectional data line 0. CTOUT_14 — SCT output 14. Match output 2 of timer 3. R — Function reserved. R — Function reserved. R — Function reserved. EMC_CS2 — LOW active Chip Select 2 signal. R — Function reserved. GPIO6[26] — General purpose digital input/output pin. R — Function reserved. CTOUT_10 — SCT output 10. Match output 2 of timer 2. R — Function reserved. R — Function reserved. CTIN_0 — SCT input 0. Capture input 0 of timer 0, 1, 2, 3. EMC_BLS2 — LOW active Byte Lane select signal 2. R — Function reserved. GPIO6[27] — General purpose digital input/output pin. R — Function reserved. CTOUT_13 — SCT output 13. Match output 1 of timer 3. R — Function reserved. O I/O O I/O I/O O O I/O O I O I/O O - PD_11 N9 x - x - - [3] I; PU - PD_12 N11 x - x - - [3] I; PU - PD_13 T14 x - - - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 46 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PD_14 R13 x - x - - [3] I; PU O I/O O - Type R — Function reserved. R — Function reserved. EMC_DYCS2 — SDRAM chip select 2. R — Function reserved. GPIO6[28] — General purpose digital input/output pin. R — Function reserved. CTOUT_11 — SCT output 11. Match output 3 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A17 — External memory address line 17. R — Function reserved. GPIO6[29] — General purpose digital input/output pin. SD_WP — SD/MMC card write protect input. CTOUT_8 — SCT output 8. Match output 0 of timer 2. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A16 — External memory address line 16. R — Function reserved. GPIO6[30] — General purpose digital input/output pin. SD_VOLT2 — SD/MMC bus voltage select output 2. CTOUT_12 — SCT output 12. Match output 0 of timer 3. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_A18 — External memory address line 18. GPIO7[0] — General purpose digital input/output pin. CAN1_TD — CAN1 transmitter output. R — Function reserved. R — Function reserved. I/O I/O I O I/O I/O O O I/O I/O O - PD_15 T15 x - x - - [3] I; PU - PD_16 R14 x - x - - [3] I; PU - PE_0 P14 x - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 47 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PE_1 N14 x - x - - [3] I; PU I/O I/O I - Type R — Function reserved. R — Function reserved. R — Function reserved. EMC_A19 — External memory address line 19. GPIO7[1] — General purpose digital input/output pin. CAN1_RD — CAN1 receiver input. R — Function reserved. R — Function reserved. ADCTRIG0 — ADC trigger input 0. CAN0_RD — CAN receiver input. R — Function reserved. EMC_A20 — External memory address line 20. GPIO7[2] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CAN0_TD — CAN transmitter output. ADCTRIG1 — ADC trigger input 1. EMC_A21 — External memory address line 21. GPIO7[3] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. NMI — External interrupt input to NMI. R — Function reserved. EMC_A22 — External memory address line 22. GPIO7[4] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. I I/O I/O O I I/O I/O I I/O I/O - PE_2 M14 x - x - - [3] I; PU I PE_3 K12 x - x - - [3] I; PU - PE_4 K13 x - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 48 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PE_5 N16 - - x - - [3] I; PU O O Type R — Function reserved. CTOUT_3 — SCT output 3. Match output 3 of timer 0. U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. EMC_D24 — External memory data line 24. GPIO7[5] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_2 — SCT output 2. Match output 2 of timer 0. U1_RI — Ring Indicator input for UART1. EMC_D25 — External memory data line 25. GPIO7[6] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_5 — SCT output 5. Match output 1 of timer 1. U1_CTS — Clear to Send input for UART1. EMC_D26 — External memory data line 26. GPIO7[7] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_4 — SCT output 4. Match output 0 of timer 0. U1_DSR — Data Set Ready input for UART1. EMC_D27 — External memory data line 27. GPIO7[8] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. I/O I/O O I I/O I/O O I I/O I/O O I I/O I/O - PE_6 M16 - - x - - [3] I; PU - PE_7 F15 - - x - - [3] I; PU - PE_8 F14 - - x - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 49 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PE_9 E16 - - x - - [3] I; PU I I I/O I/O - Type R — Function reserved. CTIN_4 — SCT input 4. Capture input 2 of timer 1. U1_DCD — Data Carrier Detect input for UART1. EMC_D28 — External memory data line 28. GPIO7[9] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTIN_3 — SCT input 3. Capture input 1 of timer 1. U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. EMC_D29 — External memory data line 29. GPIO7[10] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_12 — SCT output 12. Match output 0 of timer 3. U1_TXD — Transmitter output for UART1. EMC_D30 — External memory data line 30. GPIO7[11] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_11 — SCT output 11. Match output 3 of timer 2. U1_RXD — Receiver input for UART1. EMC_D31 — External memory data line 31. GPIO7[12] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. I O I/O I/O O O I/O I/O O I I/O I/O - PE_10 E14 - - x - - [3] I; PU - PE_11 D16 - - - - - [3] I; PU - PE_12 D15 - - - - - [3] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 50 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PE_13 G14 - - - - - [3] I; PU O I/O O I/O - Type R — Function reserved. CTOUT_14 — SCT output 14. Match output 2 of timer 3. I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). EMC_DQMOUT3 — Data mask 3 used with SDRAM and static devices. GPIO7[13] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. EMC_DYCS3 — SDRAM chip select 3. GPIO7[14] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. CTOUT_0 — SCT output 0. Match output 0 of timer 0. I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). EMC_CKEOUT3 — SDRAM clock enable 3. GPIO7[15] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. SSP0_SCK — Serial clock for SSP0. GP_CLKIN — General purpose clock input to the CGU. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. I2S1_TX_MCLK — I2S1 transmit master clock. O I/O O I/O O I/O I/O I O PE_14 C15 - - - - - [3] I; PU - PE_15 E13 - - - - - [3] I; PU - PF_0 D12 - - x - - [3] I;IA LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 51 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PF_1 E11 - - - - - [3] I; PU I/O I/O - Type R — Function reserved. R — Function reserved. SSP0_SSEL — Slave Select for SSP0. R — Function reserved. GPIO7[16] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. U3_TXD — Transmitter output for USART3. SSP0_MISO — Master In Slave Out for SSP0. R — Function reserved. GPIO7[17] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. R — Function reserved. U3_RXD — Receiver input for USART3. SSP0_MOSI — Master Out Slave in for SSP0. R — Function reserved. GPIO7[18] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. SSP1_SCK — Serial clock for SSP1. GP_CLKIN — General purpose clock input to the CGU. TRACECLK — Trace clock. R — Function reserved. R — Function reserved. R — Function reserved. I2S0_TX_MCLK — I2S transmit master clock. I2S0_RX_SCK — I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O I/O I/O I I/O I/O I/O I O O I/O PF_2 D11 - - x - - [3] I; PU - PF_3 E10 - - x - - [3] I; PU - PF_4 D10 x H4 x 120 83 [3] I;IA LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 52 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PF_5 E9 - - x - - [6] I; PU I/O I/O O I/O I Type R — Function reserved. U3_UCLK — Serial clock input/output for USART3 in synchronous mode. SSP1_SSEL — Slave Select for SSP1. TRACEDATA[0] — Trace data, bit 0. GPIO7[19] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. ADC1_4 — ADC1, input channel 4. R — Function reserved. U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. SSP1_MISO — Master In Slave Out for SSP1. TRACEDATA[1] — Trace data, bit 1. GPIO7[20] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. I2S1_TX_SDA — I2S1 transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. ADC1_3 — ADC1, input channel 3. R — Function reserved. U3_BAUD — for USART3. SSP1_MOSI — Master Out Slave in for SSP1. TRACEDATA[2] — Trace data, bit 2. GPIO7[21] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. I2S1_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. ADC1_7 — ADC1, input channel 7 or band gap output. I/O I/O O I/O I/O I I/O I/O O I/O I/O I/O PF_6 E7 - - x - - [6] I; PU - PF_7 B7 - - x - - [6] I; PU - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 53 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 PF_8 E6 - - x - - [6] I; PU I/O I O I/O I Type R — Function reserved. U0_UCLK — Serial clock input/output for USART0 in synchronous mode. CTIN_2 — SCT input 2. Capture input 2 of timer 0. TRACEDATA[3] — Trace data, bit 3. GPIO7[22] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. ADC0_2 — ADC0, input channel 2. R — Function reserved. U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. CTOUT_1 — SCT output 1. Match output 1 of timer 0. R — Function reserved. GPIO7[23] — General purpose digital input/output pin. R — Function reserved. R — Function reserved. R — Function reserved. ADC1_2 — ADC1, input channel 2. R — Function reserved. U0_TXD — Transmitter output for USART0. R — Function reserved. R — Function reserved. GPIO7[24] — General purpose digital input/output pin. R — Function reserved. SD_WP — SD/MMC card write protect input. R — Function reserved. ADC0_5 — ADC0, input channel 5. R — Function reserved. U0_RXD — Receiver input for USART0. R — Function reserved. R — Function reserved. GPIO7[25] — General purpose digital input/output pin. R — Function reserved. SD_VOLT2 — SD/MMC bus voltage select output 2. R — Function reserved. ADC1_5 — ADC1, input channel 5. © NXP B.V. 2011. All rights reserved. PF_9 D6 - - x - - [6] I; PU I/O O I/O I PF_10 A3 - - x - 98 [6] I; PU O I/O I I PF_11 A2 - - x - 100 [6] I; PU I I/O O I LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 [2] 54 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 Clock pins CLK0 N5 x K3 x 45 31 [5] O; PU O O I/O O I/O I Type EMC_CLK0 — SDRAM clock 0. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. SD_CLK — SD/MMC card clock. EMC_CLK01 — SDRAM clock 0 and clock 1 combined. SSP1_SCK — Serial clock for SSP1. ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MII interface) or Ethernet Reference Clock (RMII interface). EMC_CLK1 — SDRAM clock 1. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. R — Function reserved. CGU_OUT0 — CGU spare clock output 0. R — Function reserved. I2S1_TX_MCLK — I2S1 transmit master clock. EMC_CLK3 — SDRAM clock 3. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. SD_CLK — SD/MMC card clock. EMC_CLK23 — SDRAM clock 2 and clock 3 combined. I2S0_TX_MCLK — I2S transmit master clock. I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. O O O O O O I/O O O I/O CLK1 T10 x - - - - [5] O; PU CLK2 D14 x K6 x 99 68 [5] O; PU LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 55 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 CLK3 P12 x - - - - [5] O; PU O O O I/O Type EMC_CLK2 — SDRAM clock 2. CLKOUT — Clock output pin. R — Function reserved. R — Function reserved. R — Function reserved. CGU_OUT1 — CGU spare clock output 1. R — Function reserved. I2S1_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. JTAG interface control signal. Also used for boundary scan. Test Clock for JTAG interface (default) or Serial Wire (SW) clock. Test Reset for JTAG interface. Test Mode Select for JTAG interface (default) or SW debug data input/output. Test Data Out for JTAG interface (default) or SW trace output. Test Data In for JTAG interface. USB0 bidirectional D+ line. USB0 bidirectional D line. VBUS pin (power on USB cable). Indicates to the transceiver whether connected to an A-device (LOW) or a B-device (HIGH). 12.0 k (accuracy 1 %) on-board resistor to ground for current reference. I/O I/O I/O I/O USB1 bidirectional D+ line. USB1 bidirectional D line. I2C clock input/output. Open-drain output (for I2C-bus compliance). I2C data input/output. Open-drain output (for I2C-bus compliance). I O I/O I/O I/O I Debug pins DBGEN TCK/SWDCLK TRST TMS/SWDIO TDO/SWO TDI USB0 pins USB0_DP USB0_DM USB0_VBUS USB0_ID USB0_RREF USB1 pins USB1_DP USB1_DM I2C-bus pins L15 L16 x x D6 E6 x x 92 93 62 63 [10] L4 J5 M4 K6 K5 J4 F2 G2 F1 H2 H1 x x x x x x x x x x x A6 H2 B4 C4 H3 G3 E1 E2 E3 F1 F3 x x x x x x x x x x x 28 27 29 30 31 26 18 20 21 22 24 18 17 19 20 21 16 9 11 12 13 15 [3] I; PD I I; F [3] [3] [3] I; PU I I; PU I O; PU [3] [3] I; PU I - [7] [7] [7] [8] [8] F12 G12 x x E9 x 89 90 59 60 [9] [9] I; F I; F E10 x I2C0_SCL I2C0_SDA [10] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 56 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 Reset and wake-up pins RESET D9 x B6 x 128 91 [11] I; IA I Type External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. ADC input channel 0. Shared between 10-bit ADC0/1 and DAC. ADC input channel 1. Shared between 10-bit ADC0/1. ADC input channel 2. Shared between 10-bit ADC0/1. ADC input channel 3. Shared between 10-bit ADC0/1. ADC input channel 4. Shared between 10-bit ADC0/1. ADC input channel 5. Shared between 10-bit ADC0/1. ADC input channel 6. Shared between 10-bit ADC0/1. ADC input channel 7. Shared between 10-bit ADC0/1. I I I I I I I I I I I I O I O RTC controlled output. Input to the RTC 32 kHz ultra-low power oscillator circuit. Output from the RTC 32 kHz ultra-low power oscillator circuit. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. I O WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 ADC pins ADC0_0/ ADC1_0/DAC ADC0_1/ ADC1_1 ADC0_2/ ADC1_2 ADC0_3/ ADC1_3 ADC0_4/ ADC1_4 ADC0_5/ ADC1_5 ADC0_6/ ADC1_6 ADC0_7/ ADC1_7 RTC RTC_ALARM RTCX1 RTCX2 A9 A10 C9 D8 x x x x A4 - x - 130 93 - [11] I; IA I; IA I; IA I; IA [11] [11] [11] E3 C3 A4 B5 C6 B3 A5 C5 x x x x x x x x A2 A1 B3 A3 - x x x x x x x x 6 2 4 1 [8] I; IA I; IA I; IA I; IA I; IA I; IA I; IA I; IA [8] 143 99 139 96 138 144 142 136 - [8] [8] [8] [8] [8] [8] A11 A8 B8 x x x C3 A5 B5 x x x 129 92 125 88 126 89 [11] [8] - [8] Crystal oscillator pins XTAL1 XTAL2 D1 E1 x x B1 C1 x x 12 13 5 6 [8] - [8] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 57 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 Power and ground pins USB0_VDDA 3V3_DRIVER USB0 _VDDA3V3 USB0_VSSA _TERM USB0_VSSA _REF VDDA VBAT VDDREG F3 G3 H3 G1 B4 B10 F10, F9, L8, L7 E8 x x x x x x x D1 D2 D3 F2 B2 C5 E4, E5, F4 x x x x x x x 16 17 19 23 7 8 10 14 Separate analog 3.3 V power supply for driver. USB 3.3 V separate power supply voltage. Dedicated analog ground for clean reference for termination resistors. Dedicated clean analog ground for generation of reference currents and voltages. Analog power supply and ADC reference voltage. RTC power supply: 3.3 V on this pin supplies power to the RTC. Main regulator power supply. 137 95 127 90 94, 131, 59, 25 x [12] [12] VPP VDDIO x x - - Type OTP programming voltage. I/O power supply. Power supply for main regulator, I/O, and OTP. Ground. D7, x E12, F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 - F10, x K5 5, 36, 41, 71, 77, 107, 111, 141 VDD - - - 3, 24, 27, 49, 52, 74, 77, 97 2, 26, 51, 76 [13] [14] VSS G9, H7, J10, J11, K8 x C8, D4, D5, G8, J3, J6 x - - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 58 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. TFBGA180[1] Reset state LQFP208[1] LQFP100[1] Symbol LBGA256 Description TFBGA100 LQFP144 VSSIO C4, x D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 B2 B9 x - - x 4, 40, 76, 109 [13] [14] - - Type Ground. Analog ground. n.c. VSSA Not connected [1] [2] [3] [4] [5] [6] C2 - x - 135 94 - - x = available; - = not pinned out. I = input, O = output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDD(IO)); F = floating. 5 V tolerant pad with 15 ns glitch filter; provides digital I/O functions with TTL levels and hysteresis; normal drive strength. 5 V tolerant pad with 15 ns glitch filter providing digital I/O functions with TTL levels, and hysteresis; high drive strength. 5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP register. 5 V tolerant transparent analog pad. Transparent analog pad. Not 5 V tolerant. Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [7] [8] [9] [10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis. [12] On the TFBGA100 package, VPP is internally connected to VDDIO. [13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane. [14] On the TFBGA100 and LQFP100 packages, VSS is internally connected to VSSIO. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. [2] © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 59 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 60 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.3 AHB multilayer matrix TEST/DEBUG INTERFACE ARM CORTEX-M3 System bus I-code bus D-code bus 0 GPDMA 1 ETHERNET(1) USB0(1) USB1(1) LCD(1) SD/ MMC masters slaves 64 kB ROM 64/96 kB LOCAL SRAM 40 kB LOCAL SRAM 32 kB AHB SRAM 16 kB AHB SRAM(1) 16 kB AHB SRAM EXTERNAL MEMORY CONTROLLER AHB MULTILAYER MATRIX AHB REGISTER INTERFACES, APB, RTC DOMAIN PERIPHERALS = master-slave connection 002aaf880 (1) Not available on all parts (see Table 2). Fig 8. AHB multilayer matrix master and slave connections 7.4 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.4.1 Features • • • • • • Controls system exceptions and peripheral interrupts. In the LPC1850/30/20/10, the NVIC supports 32 vectored interrupts. 32 programmable interrupt priority levels, with hardware priority level masking. Relocatable vector table. Non-Maskable Interrupt (NMI). Software interrupt generation. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 61 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.4.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.5 Event router The event router combines various internal signals, interrupts, and the external interrupt pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down, and Deep power-down modes. Individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router. The event router can be battery powered. The following events if enabled in the event router can create a wake-up signal and/or an interrupt: • • • • • External pins WAKEUP0/1/2/3 and RESET Alarm timer, RTC, WWDT, BOD interrupts C_CAN and QEI interrupts Ethernet, USB0, USB1 signals Selected outputs of combined timers (SCT and timer0/1/3) 7.6 Global Input Multiplexer Array (GIMA) The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers, event router, or the ADCs. 7.6.1 Features • • • • • Single selection of a source. Signal inversion. Can capture a pulse if the input event source is faster than the target clock. Synchronization of input event and target clock. Single-cycle pulse generation for target. 7.7 System Tick timer (SysTick) The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. 7.8 On-chip static RAM The LPC1850/30/20/10 support up to 200 kB SRAM with separate bus master access for higher throughput and individual power control for low power operation. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 62 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.8.1 ISP (In-System Programming) mode In-System programming (ISP) is programming or reprogramming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. This can be done when the part resides in the end-user board. ISP allows to load data into on-chip SRAM and execute code from on-chip SRAM. 7.9 Boot ROM The internal ROM memory is used to store the boot code of the LPC1850/30/20/10. After a reset, the ARM processor will start its code execution from this memory. The boot ROM memory includes the following features: • ROM memory size is 64 kB. • Supports booting from USART interfaces and external static memory such as NOR flash, SPI flash, quad SPI flash. • Includes APIs for power control and OTP programming. • Includes SPIFI drivers. • Includes a flexible USB device stack that supports Human Interface Device (HID), Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers. AES capable parts also support: • CMAC authentication on the boot image. • Secure booting from an encrypted image. In development mode booting from a plain text image is possible. Development mode is terminated by programming the AES key. • API for AES programming. Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1. Table 4. Boot mode when OTP BOOT_SRC bits are programmed BOOT_SRC Description bit 0 0 1 0 1 0 1 0 Boot source is defined by the reset state of P1_1, P1_2, P2_8, and P2_9 pins. See Table 5. Boot from device connected to USART0 using pins P2_0 and P2_1. Boot from Quad SPI flash connected to the SPIFI interface using pins P3_3 to P3_8. Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. Boot from USB0. Boot mode BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 Pin state USART0 SPIFI EMC 8-bit EMC 16-bit EMC 32-bit USB0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 63 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 4. Boot mode when OTP BOOT_SRC bits are programmed BOOT_SRC Description bit 0 1 0 1 Boot from USB1. Boot from SPI flash connected to the SSP0 interface on P3_3, P3_6, P3_7 and P3_8[1]. Boot from device connected to USART3 using pins P2_3 and P2_4. Boot mode BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 USB1 SPI (SSP) USART3 0 1 1 1 0 0 1 0 0 [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Table 5. Boot mode when OPT BOOT_SRC bits are zero Pins P2_9 P2_8 LOW LOW LOW P1_2 LOW LOW HIGH P1_1 LOW HIGH LOW Boot from device connected to USART0 using pins P2_0 and P2_1. Boot from Quad SPI flash connected to the SPIFI interface on P3_3 to P3_8[1]. Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. Boot from USB0 Boot from USB1. Boot from SPI flash connected to the SSP0 interface on P3_3, P3_6, P3_7 and P3_8[1]. Boot from device connected to USART3 using pins P2_3 and P2_4. LOW LOW LOW Description Boot mode USART0 SPIFI EMC 8-bit EMC 16-bit LOW LOW HIGH HIGH EMC 32-bit LOW HIGH LOW LOW USB0 USB1 SPI (SSP) LOW LOW LOW HIGH HIGH HIGH LOW HIGH HIGH HIGH LOW HIGH USART3 [1] HIGH LOW LOW LOW The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 64 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.10 Memory mapping LPC1850/30/20/10 4 GB reserved 0xE010 0000 ARM private bus reserved SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved reserved reserved reserved high-speed GPIO reserved AES reserved APB peripherals #3 reserved APB peripherals #2 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 16 MB static external memory CS3 16 MB static external memory CS2 16 MB static external memory CS1 16 MB static external memory CS0 reserved 0x1800 0000 0x1400 0000 64 MB SPIFI data 1 GB reserved 0x1041 0000 0x1040 0000 0x1008 A000 64 kB ROM reserved 32 kB + 8 kB local SRAM (LPC1850/30/20/10) reserved 32 kB local SRAM (LPC1850/30/20) 64 kB local SRAM (LPC1850/30/20/10) 0x1000 0000 reserved 0x2400 0000 32 MB AHB SRAM bit banding 0x2200 0000 reserved 0x2001 0000 16 kB AHB SRAM (LPC1850/30/20/10) 16 kB AHB SRAM (LPC1850/30) 16 kB AHB SRAM (LPC1850/30) 16 kB AHB SRAM (LPC1850/30/20/10) local SRAM/ external static memory banks 0 GB 256 MB shadow area 0x2000 C000 0x2000 8000 0x2000 4000 0x2000 0000 0x1000 0000 0x0000 0000 002aaf228 0xFFFF FFFF 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 0x400F 8000 0x400F 4000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 reserved APB peripherals #1 reserved APB peripherals #0 reserved clocking/reset peripherals RTC domain peripherals reserved 0x4005 0000 0x4004 0000 0x4001 2000 AHB peripherals 256 MB dynamic external memory DYCS1 128 MB dynamic external memory DYCS0 0x4000 0000 0x3000 0000 0x2800 0000 0x1008 0000 0x1001 8000 0x1001 0000 Fig 9. LPC1850/30/20/10 Memory mapping (overview) All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. LPC1850_30_20_10 Preliminary data sheet Rev. 2.2 — 9 September 2011 65 of 142 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 2.2 — 9 September 2011 66 of 142 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors 0x400F 0000 0x400E 5000 0x400E 4000 0x400E 3000 0x400E 2000 0x400E 1000 0x400E 0000 0x400C 8000 0x400C 7000 0x400C 6000 0x400C 5000 0x400C 4000 0x400C 3000 0x400C 2000 0x400C 1000 0x400C 0000 0x400B 0000 0x400A 5000 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 reserved ADC1 ADC0 C_CAN0 DAC I2C1 GIMA QEI SSP1 timer3 timer2 USART3 USART2 RI timer reserved C_CAN1 I2S1 I2S0 I2C0 motor control PWM GPIO GROUP1 interrupt GPIO GROUP0 interrupt GPIO interrupts SCU timer1 timer0 SSP0 UART1 w/ modem USART0 WWDT LPC1850/30/20/10 0xFFFF FFFF APB3 peripherals external memories and ARM private bus 0x6000 0000 reserved peripheral bit band alias region reserved reserved reserved APB2 peripherals reserved 0x400F 8000 high-speed GPIO reserved AES reserved APB3 peripherals reserved APB1 peripherals APB2 peripherals reserved APB1 peripherals reserved APB0 peripherals reserved clocking/reset peripherals RTC domain peripherals APB0 peripherals reserved 0x4001 2000 AHB peripherals 0x4000 0000 SRAM memories external memory banks 0x0000 0000 002aaf229 reserved 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 reserved RTC OTP controller RTC domain peripherals event router CREG power mode control backup registers alarm timer ethernet reserved LCD USB1 USB0 AHB peripherals EMC SD/MMC SPIFI DMA reserved SCT clocking reset control peripherals RGU CCU2 CCU1 CGU 0x4006 0000 0x4005 4000 0x4005 3000 0x4005 2000 0x4005 1000 0x4005 0000 0x400F 4000 0x400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0x4006 0000 0x4005 0000 0x4004 0000 0x4004 7000 0x4004 6000 0x4004 5000 0x4004 4000 0x4004 3000 0x4004 2000 0x4004 1000 0x4004 0000 0x4001 2000 0x4001 0000 0x4000 9000 0x4000 8000 0x4000 7000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 32-bit ARM Cortex-M3 microcontroller LPC1850/30/20/10 Fig 10. LPC1850/30/20/10 Memory mapping (peripherals) NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.11 Security features 7.11.1 AES security engine The hardware AES security engine can decode data using the AES algorithm in conjunction with a 128-bit key. 7.11.1.1 Features • • • • Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI). Secure storage of keys. Support for CMAC hash calculation to authenticate encrypted data. Data is processed in little endian mode. This means that the first byte read from flash is integrated into the AES codeword as least significant byte. The 16th byte read from flash is the most significant byte of the first AES codeword. • AES engine performance of 1 byte/clock cycle. • DMA transfers supported through the GPDMA. 7.11.2 One-Time Programmable (OTP) memory The OTP provides 32 bit of memory for general purpose use and two 128-bit non-volatile memory blocks to store AES keys or other customer data. 7.12 General Purpose I/O (GPIO) The LPC1850/30/20/10 provides 8 GPIO ports with up to 16 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. All GPIO pins default to inputs with pull-up resistors enabled on reset. 7.12.1 Features • Accelerated GPIO functions: – GPIO registers are located on the AHB so that the fastest possible I/O timing can be achieved. – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and half-word addressable. – Entire port value can be written in one instruction. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 67 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller • Two GPIO group interrupts can be triggered by any pin or pins in each port. 7.13 AHB peripherals 7.13.1 State Configurable Timer (SCT) subsystem The SCT allows a wide variety of timing, counting, output modulation, and input capture operations. The inputs and outputs of the SCT are shared with the capture and match inputs/outputs of the 32-bit general purpose counter/timers. The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the two-counter case, in addition to the counter value the following operational elements are independent for each half: • State variable • Limit, halt, stop, and start conditions • Values of Match/Capture registers, plus reload or capture control values In the two-counter case, the following operational elements are global to the SCT, but the last three can use match conditions from either counter: • • • • • 7.13.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • • • • Two 16-bit counters or one 32-bit counter. Counter(s) clocked by bus clock or selected input. Up counter(s) or up-down counter(s). State variable allows sequencing across multiple counter cycles. Event combines input or output condition and/or counter match in a specified state. Events control outputs and interrupts. Selected event(s) can limit, halt, start, or stop a counter. Supports: – up to 8 inputs (one input connected internally) – up to 16 outputs – 16 match/capture registers – 16 events – 32 states 7.13.2 General Purpose DMA (GPDMA) The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 68 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller example, a bidirectional port requires one stream for transmit and one for receives. The source and destination areas can each be either a memory region or a peripheral for master 1, but only memory for master 0. 7.13.2.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • Two AHB bus masters for transferring data. These interfaces transfer data when a DMA request goes active. Master 1 can access memories and peripherals, master 0 can access memories only. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.13.3 SPI Flash Interface (SPIFI) The SPI Flash Interface (allows low-cost serial flash memories to be connected to the ARM Cortex-M3 processor with little performance penalty compared to parallel flash devices with higher pin count. After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Erasure and programming are handled by simple sequences of commands. Many serial flash devices use a half-duplex command-driven SPI protocol for device setup and initialization and then move to a half-duplex, command-driven 4-bit protocol for normal operation. Different serial flash vendors and devices accept or require different LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 69 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller commands and command formats. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. 7.13.3.1 Features • • • • • Interfaces to serial flash memory in the main memory map. Supports classic and 4-bit bidirectional serial protocols. Half-duplex protocol compatible with various vendors and devices. Data rates of up to 40 MB per second total. Supports DMA access. 7.13.4 SD/MMC card interface The SD/MMC card interface supports the following modes: • • • • Secure Digital memory (SD version 3.0) Secure Digital I/O (SDIO version 2.0) Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1) Multimedia Cards (MMC version 4.4) 7.13.5 External Memory Controller (EMC) The LPC1850/30/20/10 EMC is a Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. 7.13.5.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and NOR flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • 8/16/32 data and 24 address lines wide static memory support. On parts LPC1820/10 only 8/16 data lines are available. • 16 bit and 32 bit wide chip select SDRAM memory support. • Static memory features include: – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 70 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.13.6 High-speed USB Host/Device/OTG interface (USB0) Remark: USB0 is available on parts PC1850/30/20 (see Table 2). The USB OTG module allows the part to connect directly to a USB host such as a PC (in device mode) or to a USB device in host mode. 7.13.6.1 Features • • • • • • • Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals. Supports software Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG peripherals. • Contains UTMI+ compliant transceiver (PHY). • Supports interrupts. • This module has its own, integrated DMA engine. 7.13.7 High-speed USB Host/Device interface with ULPI (USB1) Remark: USB1 is available on parts LPC1850/30 (see Table 2). The USB1 interface can operate as a full-speed USB host/device interface or can connect to an external ULPI PHY for High-speed operation. 7.13.7.1 Features • • • • Complies with Universal Serial Bus specification 2.0. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals if connected to external ULPI PHY. • Supports all full-speed USB-compliant peripherals. • Supports interrupts. • This module has its own, integrated DMA engine. 7.13.8 LCD controller Remark: The LCD controller is available on the part LPC1850 only. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 71 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.13.8.1 Features • • • • AHB master interface to access frame buffer. Setup and control via a separate AHB slave interface. Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. Hardware cursor support for single-panel displays. 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. 16 bpp true-color non-palettized for color STN and TFT. 24 bpp true-color non-palettized for color TFT. Programmable timing for different display panels. 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. • • • • • • • • • • • • 7.13.9 Ethernet Remark: Ethernet is available on parts LPC1850/30 (see Table 2). 7.13.9.1 Features • • • • LPC1850_30_20_10 10/100 Mbit/s TCP/IP hardware checksum IP checksum DMA support All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 72 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller • Power management remote wake-up frame and magic packet detection • Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. – Back-pressure support for half-duplex operation. – Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation. • Support for IEEE 1588 time stamping and IEEE 1588 advanced time stamping (IEEE 1588-2008 v2). 7.14 Digital serial peripherals 7.14.1 UART Remark: The LPC1850/30/20/10 contain one UART with standard transmit and receive data lines. UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.14.1.1 Features • • • • • Maximum UART data bit rate of MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. control implementation. • Auto baud capabilities and FIFO control mechanism that enables software flow • Equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • Support for RS-485/9-bit/EIA-485 mode (UART1). • DMA support. 7.14.2 USART Remark: The LPC1850/30/20/10 contain three USARTs. In addition to standard transmit and receive data lines, the USARTs support a synchronous mode and a smart card mode. The USARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 73 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.14.2.1 Features • • • • • Maximum UART data bit rate of MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. control implementation. • Auto baud capabilities and FIFO control mechanism that enables software flow • • • • • Support for RS-485/9-bit/EIA-485 mode. USART3 includes an IrDA mode to support infrared communication. All USARTs have DMA support. Support for synchronous mode. Smart card mode conforming to ISO7816 specification 7.14.3 SSP serial I/O controller Remark: The LPC1850/30/20/10 contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.14.3.1 Features • Maximum SSP speed of Mbit/s (master) or Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA 7.14.4 I2C-bus interface Remark: The LPC1850/30/20/10 each contain two I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 74 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.14.4.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • • • • • • I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus. • Serial clock synchronization allows devices with different bit rates to communicate via • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.14.5 I2S interface Remark: The LPC1850/30/20/10 contain two I2S interfaces. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.14.5.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96, 192) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 75 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.14.6 C_CAN Remark: The LPC1850/30/20/10 contain two C_CAN controllers. Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of reliability. 7.14.6.1 Features • • • • • • • Conforms to protocol version 2.0 parts A and B. Supports bit rate of up to 1 Mbit/s. Supports 32 Message Objects. Each Message Object has its own identifier mask. Provides programmable FIFO mode (concatenation of Message Objects). Provides maskable interrupts. Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. • Provides programmable loop-back mode for self-test operation. 7.15 Counter/timers and motor control 7.15.1 General purpose 32-bit timers/external event counter Remark: The LPC1850/30/20/10 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.15.1.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 76 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 7.15.2 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 7.15.3 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.15.3.1 Features • • • • • • • • • • Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with “less than” interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). 7.15.4 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.15.4.1 Features • 32-bit counter. Counter can be free-running or be reset by a generated interrupt. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 77 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 7.15.5 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.15.5.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) uses the IRC as the clock source. 7.16 Analog peripherals 7.16.1 Analog-to-Digital Converter Remark: The LPC1850/30/20/10 contain two 10-bit ADCs. 7.16.1.1 Features • • • • • • • 10-bit successive approximation analog to digital converter. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 to VDDA. Sampling frequency up to 400 kSamples/s. Burst conversion mode for single or multiple inputs. Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer outputs 8 or 15, or the PWM output MCOA2. • Individual result registers for each A/D channel to reduce interrupt overhead. • DMA support. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 78 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.16.2 Digital-to-Analog Converter (DAC) 7.16.2.1 Features • • • • • • 10-bit resolution Integral Non-Linearity Differential Non-Linearity Monotonic by design (resistor string architecture) Controllable conversion speed Low power consumption 7.17 Peripherals in the RTC power domain 7.17.1 RTC The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. The RTC is clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference and is powered by its own power supply pin, VBAT. 7.17.1.1 Features • Measures the passage of time to maintain a calendar and clock. Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. • Ultra-low power design to support battery powered systems. Less than required for battery operation. Uses power from the CPU power supply when it is present. • • • • • Dedicated battery power supply pin. RTC power supply is isolated from the rest of the chip. Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution. Periodic interrupts can be generated from increments of any field of the time registers. Alarm interrupt can be generated for a specific date/time. 7.17.2 Alarm timer The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled. The alarm timer is part of the RTC power domain and can be battery powered. 7.18 System control 7.18.1 Configuration registers (CREG) The following settings are controlled in the configuration register block: • BOD trip settings • Oscillator output • DMA-to-peripheral muxing LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 79 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller • • • • Ethernet mode Memory mapping Timer/USART inputs Enabling the USB controllers In addition, the CREG block contains the part identification and part configuration information. 7.18.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. Analog I/Os for the ADCs and the DAC as well as most USB pins are on separate pads and are not controlled through the SCU. 7.18.3 Clock Generation Unit (CGU) The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be unrelated in frequency and phase and can have different clock sources within the CGU. One CGU base clock is routed to the CLKOUT pins. Multiple branch clocks are derived from each base clock. The branch clocks offer very flexible control for power-management purposes. All branch clocks are outputs of one of two Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. 7.18.4 Internal RC oscillator (IRC) The IRC is used as the clock source for the WWDT and/or as the clock that drives the PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1850/30/20/10 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.18.5 PLL0USB (for USB0) PLL0 is a dedicated PLL for the USB0 High-speed controller. PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz. 7.18.6 PLL0AUDIO (for audio) The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This PLL accepts an input clock frequency derived from an external oscillator or internal IRC. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired output frequency. The output frequency can be set to 32fs, 64fs, 128  fs, 256  fs, 384  fs and the sampling frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 80 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 7.18.7 System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.18.8 Reset Generation Unit (RGU) The RGU allows generation of independent reset signals for individual blocks and peripherals. 7.18.9 Power control The LPC1850/30/20/10 feature several independent power domains to control power to the core and the peripherals (see Figure 11). The RTC and its associated peripherals (the alarm timer, the CREG block, the OTP controller, the back-up registers, and the event router) are located in the RTC power-domain which can be powered by a battery supply or the main regulator. A power selector switch ensures that the RTC block is always powered on. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 81 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller LPC18xx VDDIO VSS REGULATOR VDDREG MAIN POWER DOMAIN to I/O pads to core to memories, peripherals, oscillators, PLLs VBAT POWER SELECTOR ULTRA LOW-POWER REGULATOR to RTC domain peripherals RESET WAKEUP0/1/2/3 to RTC I/O pads RTCX1 RTCX2 32 kHz OSCILLATOR RESET/WAKE-UP CONTROL BACKUP REGISTERS REAL-TIME CLOCK ALARM ALWAYS-ON/RTC POWER DOMAIN DAC VDDA VSSA ADC POWER DOMAIN ADC VPP OTP POWER DOMAIN USB0_VDDA3V_DRIVER USB0_VDDA3V3 USB0 POWER DOMAIN OTP USB0 002aag305 Fig 11. LPC1850/30/20/10 Power domains The LPC1850/30/20/10 support four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The LPC1850/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain. 7.19 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 82 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(REG)(3V3) VDD(IO) VDDA(3V3) VBAT VDD(3V3) Vprog(pf) VI Parameter regulator supply voltage (3.3 V) input/output supply voltage analog supply voltage (3.3 V) battery supply voltage supply voltage (3.3 V) polyfuse programming voltage input voltage Conditions on pin VDDREG on pin VDDIO on pin VDDA on pin VBAT on pin VDD; LQFP100 package only on pin VPP only valid when the VDD(IO) supply voltage is present 5 V tolerant I/O pins (see Table 3) ADC/DAC pins and digital I/O pins configured for an analog function (see Table 3) USB1 pins USB1_DP and USB1_DM (see Table 3) IDD ISS Ilatch Tstg Ptot(pack) VESD supply current ground current I/O latch-up current storage temperature total power dissipation (per package) electrostatic discharge voltage based on package heat transfer, not device power consumption human body model; all pins [6] [3] Min 2.2[2] 2.2 2.0 2.2 2.2 2.7 0.5 Max 3.6 3.6 3.6 3.6 3.6 3.6 5.5 Unit V V V V V V V VDDA(3V3) V [4] [4] V mA mA mA C W V per supply pin per ground pin (0.5VDD(IO)) < VI < (1.5VDD(IO)); Tj < 125 C - [5] [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] [3] [4] [5] [6] 2.0 V if VBAT  2.2 V. Including voltage on outputs in 3-state mode; at 2.0 V the speed will be reduced. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 83 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal characteristics VDD = 2.2 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Tj(max) Parameter maximum junction temperature Conditions Min Typ Max Unit C LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 84 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Supply pins VDD(IO) VDD(REG)(3V3) VDDA(3V3) VBAT VDD(3V3) IDD(REG)(3V3) input/output supply voltage regulator supply voltage (3.3 V) analog supply voltage (3.3 V) battery supply voltage supply voltage (3.3 V) on pin VDD; LQFP100 package only [2] Parameter Conditions Min 2.2 2.2 2.0 2.2 2.2 Typ[1] - Max 3.6 3.6 3.6 3.6 3.6 Unit V V V V V regulator supply current active mode; code (3.3 V) while(1){} executed from ; all peripherals disabled CCLK = 12 MHz; PLL disabled CCLK = 100 MHz; PLL enabled CCLK = 150 MHz; PLL enabled sleep mode deep sleep mode power-down mode deep power-down mode; RTC [3] - 10 40 55 60 30 4 - mA mA mA mA A A A [3] [3] [3] [3][4] [3][4] [3] IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present VDD(REG)(3V3) not present [5] [6] - - nA nA nA nA nA nA nA nA IDD(IO) I/O supply current deep sleep mode power-down mode deep power-down mode [7] [7] [7] [9] [9] [9] - IDD(ADC) ADC supply current deep sleep mode power-down mode deep power-down mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 85 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol VIH VIL Vhys Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage Conditions [8] Min Typ[1] Max 5.5 Unit V Digital pins - RESET pin 0.8  (Vps  0.35) 0.5 - [8] 0.3  (Vps  V 0.1) V [8] 0.05  (Vps  0.35) - Digital pins - normal drive strength IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = 6 mA IOL = 6 mA VOH = VDD(IO)  0.4 V VOL = 0.4 V [11] A A VI = VDD(IO); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(IO); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [10] IOZ - - A VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu Rpu(weak) Rpd(weak) 0.5 2.0 0.5 0.1VDD(IO) VDD(IO)  0.4 6 6 45 45 50 50 VDD(IO) 5.5 0.8 0.4 35 30 65 65 V V V V V V V mA mA mA mA A A A k k HIGH-level short-circuit drive HIGH; connected to output current ground LOW-level short-circuit output current pull-down current pull-up current drive LOW; connected to VDD(IO) VI = VDD(IO) VI = 0 V VDD(IO) < VI < 3.6 V weak pull-up resistance VI = 0 V weak pull-down resistance VI = VDD(IO) [11] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 86 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IIL IIH Parameter Conditions Min Typ[1] Max Unit A A Digital pins - high drive strength LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = 4 mA IOL = 4 mA VOH = VDD(IO)  0.4 V VOL = 0.4 V [11] VI = VDD(IO); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(IO); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [10] IOZ - - A VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu VDD(IO)  0.4 VDD(IO) V V V V V V V mA mA mA mA A A A HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD(IO) VI = 3.6 V VI = 0 V VDD(IO) < VI < 3.6 V [11] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 87 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IIL IIH Parameter Conditions Min Typ[1] Max Unit A A Digital pins - high-speed LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = 4 mA IOL = 4 mA VOH = VDD(IO)  0.4 V VOL = 0.4 V [11] VI = VDD(IO); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(IO); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active [10] IOZ - - A VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu VDD(IO)  0.4 - VDD(IO) V V V V V V V mA mA mA mA A A A V V V V A A HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD(IO) VI = 3.6 V VI = 0 V VDD(IO) < VI < 3.6 V [11] Open-drain I2C0-bus pins VIH VIL Vhys VOL ILI HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = mA VI = VDD(IO) VI = 5 V [12] - LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 88 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Oscillator pins Vi(XTAL1) Vo(XTAL2) USB pins VIC common-mode input voltage high-speed mode full-speed/low-speed mode chirp mode Vi(dif) [1] [2] [3] [4] [5] [6] [7] [8] [9] Parameter input voltage on pin XTAL1 output voltage on pin XTAL2 Conditions Min 0.5 0.5 Typ[1] - Max 1.2 1.2 Unit V V mV mV mV mV differential input voltage Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. The RTC typically fails when VBAT drops below 2.2 V and VDD(REG)(3V3) is less than 2.2 V. VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. Applies to parts LPC1850/30/20/10 Rev ‘-’ only. Conditions . On pin VBAT; IDD(REG)(3V3) = nA; VDD(REG)(3V3) = 3.3 V; VBAT < VDD(REG)(3V3); Tamb = 25 C. On pin VBAT; VBAT = 3.3 V; Tamb = 25 C. All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. Vps corresponds to the output of the power switch (see Figure 11) which is determined by the greater of VBAT and VDD(Reg)(3V3). VDDA(3V3) = 3.3 V; Tamb = 25 C. [10] VDD(IO) supply voltage must be present. [11] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] To VSS. 10.1 Power consumption Remark: All power consumption data in this section apply to Rev ‘-’ of the LPC1850/30/20/10 parts only. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 89 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 60 144 MHz IDD(REG)(3V3) (mA) 132 MHz 40 108 MHz 84 MHz 002aag121 60 MHz 20 36 MHz 12 MHz 0 2.0 2.4 2.8 3.2 VDD(REG)(3V3) (V) 3.6 Conditions: Tamb = 25 C; normal mode entered executing code while(1){} from ROM; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 12. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active mode 60 144 MHz IDD(REG)(3V3) 132 MHz (mA) 40 108 MHz 84 MHz 60 MHz 002aag122 20 36 MHz 12 MHz 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD(REG)(3V3) = 3.0 V, normal mode entered executing code while(1){} from ROM; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 13. Typical supply current versus temperature in active mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 90 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VDD(REG)(3V3) = 3.0 V; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 14. Typical supply current versus temperature in sleep mode 400 IDD(REG)(3V3) (μA) 300 VDD(REG)(3V3) = 3.6 V 3.4 V 3.0 V 2.6 V 2.2 V 002aag123 200 100 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VBAT = 0 V; VDD(IO) = 0 V; PD0_SLEEP0_MODE = 0x003F 00AA. Fig 15. Typical supply current versus temperature in Deep-sleep mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 91 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 60 IDD(REG)(3V3) (μA) VDD(REG)(3V3) = 3.6 V 40 3.0 V 2.6 V 2.2 V 002aag124 20 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VBAT = 0 V; VDD(IO) = 0 V; PD0_SLEEP0_MODE = 0x003F FCBA. Fig 16. Typical supply current versus temperature in Power-down mode 10.0 IDD(REG)(3V3) (μA) 8.0 VDD(REG)(3V3) = 3.6 V 2.2 V 002aag125 6.0 4.0 2.0 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VBAT = 0 V; VDD(IO) = 0 V; PD0_SLEEP0_MODE = 0x003F FF7F. Fig 17. Typical supply current versus temperature in Deep power-down mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 92 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 9. Power consumption for individual peripherals Tamb = 25 C; VDD(REEG)(3V3) = 3.3 V. Peripheral IRC ADC DAC I2C0 I2C1 I2S SSP0 SSP1 USART0 UART1 USART2 USART3 USB0 USB1 Ethernet [1] Conditions Typical IDD(REG)(3V3)[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 10.2 Power consumption Remark: All power consumption data in this section apply to Rev ‘A’ of the LPC1850/30/20/10 parts only. X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: Tamb = 25 C; normal mode entered executing code while(1){} from ROM; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 18. Typical supply current versus regulator supply voltage VDD(REEG)(3V3) in active mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 93 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VDD(REG)(3V3) = 3.0 V, normal mode entered executing code while(1){} from ROM; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 19. Typical supply current versus temperature in active mode X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VDD(REG)(3V3) = 3.0 V; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 20. Typical supply current versus temperature in sleep mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 94 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VBAT = 0 V; VDD(IO) = 0 V. Fig 21. Typical supply current versus temperature in Deep-sleep mode X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VBAT = 0 V; VDD(IO) = 0 V. Fig 22. Typical supply current versus temperature in Power-down mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 95 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aac984 X X X X X X X (X) X X X Conditions: VBAT = 0 V; VDD(IO) = 0 V. Fig 23. Typical supply current versus temperature in Deep power-down mode 10.3 Electrical pin characteristics X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Fig 24. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Fig 25. Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 96 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller X X (X) X 001aab173 X X (X) X 001aab173 X X X X X X X X (X) X X X X X X X X X (X) X X X X X Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; standard port pins. Fig 26. Typical pull-up current Ipu versus input voltage VI Fig 27. Typical pull-down current Ipd versus input voltage VI LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 97 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11. Dynamic characteristics 11.1 External clock Table 10. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(IO) over specified ranges.[1] Symbol Parameter fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL [1] [2] Conditions Min 1 40 Tcy(clk)  Tcy(clk)  - Typ[2] - Max 25 1000 Unit MHz ns ns ns ns ns oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCLCX Tcy(clk) tCHCX tCLCH 002aaa907 Fig 28. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 98 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.2 IRC and RTC oscillators Table 11. Dynamic characteristic: IRC and RTC oscillators Tamb = 40 C to +85 C;  VDD(IO)  .[1] Symbol fosc(RC) fi(RTC) [1] [2] Parameter internal RC oscillator frequency RTC input frequency Conditions - Min - Typ[2] 12.00 32.768 Max - Unit MHz kHz Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. X X (X) X 001aab173 X X X X X X X X (X) X X X Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD(IO)  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 29. Internal RC oscillator frequency versus temperature 11.3 I2C-bus Table 12. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C.[1] Symbol fSCL Parameter SCL clock frequency Conditions Standard-mode Fast-mode Fast-mode Plus tf fall time [3][4][5][6] Min 0 0 0 - Max 100 400 1 300 Unit kHz kHz MHz ns of both SDA and SCL signals Standard-mode Fast-mode Fast-mode Plus 20 + 0.1  Cb - 300 120 ns ns LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 99 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 12. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C.[1] Symbol tLOW Parameter LOW period of the SCL clock Conditions Standard-mode Fast-mode Fast-mode Plus tHIGH HIGH period of the SCL clock Standard-mode Fast-mode Fast-mode Plus tHD;DAT data hold time [2][3][7] Min 4.7 1.3 0.5 4.0 0.6 0.26 0 0 0 250 100 50 Max - Unit s s s s s s s s s ns ns ns Standard-mode Fast-mode Fast-mode Plus tSU;DAT data set-up time [8][9] Standard-mode Fast-mode Fast-mode Plus [1] [2] [3] [4] [5] Parameters are valid over operating temperature range unless otherwise specified. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. [8] [9] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 100 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller tf SDA 70 % 30 % tf 70 % 30 % 70 % 30 % tHD;DAT tSU;DAT tVD;DAT tHIGH SCL 70 % 30 % 70 % 30 % tLOW 70 % 30 % S 1 / fSCL 002aaf425 Fig 30. I2C-bus pins clock timing 11.4 I2S-bus interface Table 13. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Conditions and data refer to I2S0 and I2S1 pins. Symbol tr tf tWH tWL Parameter rise time fall time pulse width HIGH pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK on pins I2Sx_TX_SCK and I2Sx_RX_SCK Conditions [1] [1] [1] Min - Max Unit ns ns ns common to input and output [1] output tv(Q) input tsu(D) th(D) [1] data output valid time data input set-up time data input hold time on pin I2Sx_TX_SDA on pin I2Sx_RX_SDA on pin I2Sx_RX_SDA [1] - ns ns ns [1] [1] CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 101 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2Sx_TX_SCK tWH I2Sx_TX_SDA tWL tv(Q) I2Sx_TX_WS tv(Q) 002aag497 Fig 31. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH I2Sx_RX_SDA tWL tsu(D) th(D) I2Sx_RX_WS tsu(D) tsu(D) 002aag498 Fig 32. I2S-bus timing (receive) LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 102 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.5 SSP interface Table 14. Symbol Tcy(PCLK) Tcy(clk) Dynamic characteristics: SSP pins in SPI mode Parameter PCLK cycle time clock cycle time full-duplex mode when only transmitting SSP master tDS tDH tv(Q) th(Q) SSP slave tDS tDH tv(Q) th(Q) data set-up time data hold time data output valid time data output hold time in SPI mode in SPI mode in SPI mode in SPI mode [3][4] [3][4] [1] Conditions Min Max - Unit ns ns ns data set-up time data hold time data output valid time data output hold time in SPI mode in SPI mode in SPI mode in SPI mode [2] [2] [2] [2]  Tcy(PCLK) + - Tcy(clk)  Tcy(PCLK) +  Tcy(PCLK) + ns ns ns ns ns ns ns ns [3][4] [3][4] [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). Tamb = 40 C to 85 C; VDD(REG)(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V. Tcy(clk) = 12  Tcy(PCLK). Tamb = 25 C; VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V. [2] [3] [4] LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 103 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID CPHA = 1 th(Q) tv(Q) MOSI DATA VALID DATA VALID tDS MISO DATA VALID tDH DATA VALID th(Q) CPHA = 0 002aae829 Fig 33. SSP master timing in SPI mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 104 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tv(Q) MISO DATA VALID DATA VALID tDH DATA VALID th(Q) CPHA = 1 tDS MOSI DATA VALID tv(Q) MISO DATA VALID tDH DATA VALID th(Q) DATA VALID CPHA = 0 002aae830 Fig 34. SSP slave timing in SPI mode LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 105 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.6 External memory interface Table 15. Dynamic characteristics: Static external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol Read cycle tCSLAV tCSLOEL tCSLBLSL tOELOEH Parameter[1] parameters[2] CS LOW to address valid time CS LOW to OE LOW time CS LOW to BLS LOW time OE LOW to OE HIGH time RD1 RD2 RD3; PB = 1 RD4 + Tcy(clk)  WAITOEN + Tcy(clk)  WAITOEN + Tcy(clk)  WAITOEN ns ns ns Conditions[1] Min Typ Max Unit (WAITRD  (WAITRD  WAITOEN + 1)  WAITOEN + 1)  Tcy(clk)  Tcy(clk)  [3] (WAITRD  ns WAITOEN + 1)  Tcy(clk)  (WAITRD  WAITOEN +1)  Tcy(clk)  + Tcy(clk)  (1 + WAITWEN) ns tam memory access time RD5 (WAITRD  WAITOEN +1)  Tcy(clk)  (WAITRD  WAITOEN +1)  Tcy(clk)  + Tcy(clk)  (1 + WAITWEN) th(D) tCSHBLSH tCSHOEH tOEHANV tdeact tCSLAV tCSLDV tCSLWEL tCSLBLSL tWELWEH data input hold time CS HIGH to OE HIGH time OE HIGH to address invalid time deactivation time CS LOW to address valid time CS LOW to data valid time CS LOW to WE LOW time CS LOW to BLS LOW time WE LOW to WE HIGH time RD6 [4] ns ns ns ns ns ns ns ns ns CS HIGH to BLS HIGH time PB = 1 RD7 WR1 WR2 WR3; PB = 1 WR4; PB = 1 WR5; PB = 1 + Tcy(clk)  (1 + WAITWEN) Write cycle parameters[2] (WAITWR  (WAITWR  ns (WAITWR  WAITWEN + 1)  WAITWEN + 1)  WAITWEN + 1)  Tcy(clk)  Tcy(clk)  Tcy(clk)  (WAITWR  (WAITWR  ns (WAITWR  WAITWEN + 3)  WAITWEN + 3)  WAITWEN + 3)  Tcy(clk)  Tcy(clk)  Tcy(clk)  + Tcy(clk) [5] tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 tWEHDNV tWEHEOW tBLSHDNV tWEHANV tdeact tCSLBLSL WE HIGH to data invalid time WE HIGH to end of write time BLS HIGH to data invalid time WR6; PB = 1 WR7; PB = 1 PB = 1 + Tcy(clk) + Tcy(clk) + Tcy(clk) + Tcy(clk) + Tcy(clk) + Tcy(clk) ns ns ns ns ns ns + Tcy(clk) + Tcy(clk) WE HIGH to address invalid PB = 1 time deactivation time CS LOW to BLS LOW WR8; PB = 0; PB = 1 WR9; PB = 0 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 106 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 15. Dynamic characteristics: Static external memory interface …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol tBLSLBLSH Parameter[1] Conditions[1] Min Typ Max Unit BLS LOW to BLS HIGH time WR10; PB = 0 (WAITWR  (WAITWR  (WAITWR  ns WAITWEN + 1)  WAITWEN + 1)  WAITWEN + 1)  Tcy(clk) + Tcy(clk) + Tcy(clk) + [5] tBLSHEOW tBLSHDNV BLS HIGH to end of write time BLS HIGH to data invalid time WR11; PB = 0 WR12; PB = 0 ns ns [1] [2] [3] [4] [5] Parameters are shown as RDn or WDn in Figure 35 as indicated in the Conditions column. Parameters specified for 40 % of VDD(IO) for rising edges and 60 % of VDD(IO) for falling edges. Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid. End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1). EMC_Ax RD1 EMC_CSx WR8 RD2 EMC_OE RD4 RD7 WR9 EMC_BLSx EMC_WE RD5 RD5 RD5 EMC_Dx EOR EOW 002aag214 WR1 WR10 WR11 RD6 WR2 WR12 Fig 35. External static memory read/write access (PB = 0) LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 107 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller EMC_Ax RD1 EMC_CSx RD2 EMC_OE RD3 EMC_BLSx RD7 WR3 EMC_WE RD5 RD5 RD5 RD5 EMC_Dx EOR EOW 002aag215 WR1 WR8 RD4 RD7 WR4 WR8 WR5 WR7 RD6 WR2 WR6 Fig 36. External static memory read/write access (PB = 1) EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE RD5 RD5 RD5 RD5 EMC_Dx 002aag216 Fig 37. External static memory burst read cycle Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol Tcy(clk) td(SV) th(S) td(RASV) th(RAS) td(CASV) th(CAS) LPC1850_30_20_10 Parameter clock cycle time chip select valid delay time chip select hold time row address strobe valid delay time row address strobe hold time column address strobe valid delay time column address strobe hold time Conditions Min Typ Max Unit ns ns ns ns ns ns ns Common to read and write cycles All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 108 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol td(WV) th(W) td(GV) th(G) td(AV) th(A) tsu(D) th(D) td(QV) th(Q) Parameter write valid delay time write hold time output enable valid delay time output enable hold time address valid delay time address hold time data input set-up time data input hold time data output valid delay time data output hold time Conditions Min Typ Max Unit ns ns ns ns ns ns ns ns ns ns Read cycle parameters Write cycle parameters Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 CL = 30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol td(SV) th(S) td(RASV) th(RAS) td(CASV) th(CAS) td(WV) th(W) td(GV) th(G) td(AV) th(A) tsu(D) th(D) td(QV) th(Q) Parameter chip select valid delay time chip select hold time row address strobe valid delay time row address strobe hold time column address strobe valid delay time column address strobe hold time write valid delay time write hold time output enable valid delay time output enable hold time address valid delay time address hold time data input set-up time data input hold time data output valid delay time data output hold time Conditions Min Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Common to read and write cycles Read cycle parameters Write cycle parameters LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 109 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Tcy(clk) EMC_CLKx td(CS) th(CS) EMC_DYCSx td(RAS) EMC_RAS th(RAS) td(CAS) EMC_CAS EMC_WE th(CAS) td(DQM) EMC_DQMOUTx td(A) EMC_Ax tsu(D) th(D) EMC_Dx th(A) th(DQM) 002aag205 Fig 38. Dynamic external memory interface signal timing (read access) LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 110 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.7 USB interface Table 18. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO), unless otherwise specified. Symbol tr tf tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver 10 % to 90 % must reject as EOP; see Figure 39 must accept as EOP; see Figure 39 [1] Conditions 10 % to 90 % 10 % to 90 % tr / tf Min Typ - Max - Unit ns ns % V ns ns ns ns ns see Figure 39 see Figure 39 tEOPR2 EOP width at receiver [1] - - ns [1] Characterized but not implemented as production test. Guaranteed by design. TPERIOD crossover point differential data lines crossover point extended source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 39. Differential data-to-EOP transition skew and EOP width 11.8 Ethernet Table 19. Dynamic characteristics: Ethernet Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol Parameter RMII mode fclk clk clock frequency clock duty cycle for ENET_RX_CLK [1] [1] Conditions Min Max Unit MHz % LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 111 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 19. Dynamic characteristics: Ethernet Tamb = 40 C to 85 C, VDD(REG)(3V3) = . Symbol Parameter tsu set-up time Conditions for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_TXDn, ENET_TX_EN, ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_TX_CLK for ENET_TXDn, ENET_TX_EN, ENET_TX_ER for ENET_TXDn, ENET_TX_EN, ENET_TX_ER for ENET_RX_CLK for ENET_RXDn, ENET_RX_ER, ENET_RX_DV for ENET_RXDn, ENET_RX_ER, ENET_RX_DV [1][2] Min Max - Unit ns th hold time [1][2] - ns MII mode fclk clk tsu th fclk clk tsu th clock frequency clock duty cycle set-up time hold time clock frequency clock duty cycle set-up time hold time [1] [1] [1][2] - MHz % ns ns MHz % ns ns [1][2] [1] [1] [1][2] [1][2] [1] [2] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device. Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or output level. ENET_RX_CLK ENET_TX_CLK ENET_RXD[n] ENET_RX_DV ENET_RX_ER ENET_TXD[n] ENET_TX_EN ENET_TX_ER tsu th 002aag210 Fig 40. Ethernet timing LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 112 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 11.9 SD/MMC Table 20. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol fclk tsu(D) th(D) td(QV) th(Q) Parameter clock frequency data input set-up time Conditions on pin SD_CLK; data transfer mode on pin SD_CLK; identification mode on pins SD_CMD, SD_DATn as inputs 6 6 3.5 Min Max 25 25 23 Unit MHz MHz ns ns ns ns data input hold time on pins SD_CMD, SD_DATn as inputs data output valid delay time data output hold time on pins SD_CMD, SD_DATn as outputs on pins SD_CMD, SD_DATn as outputs Tcy(clk) SD_CLK td(QV) SD_CMD (O) SD_DATn (O) th(Q) tsu(D) SD_CMD (I) SD_DATn (I) th(D) 002aag204 Fig 41. SD/MMC timing LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 113 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 12. ADC/DAC electrical characteristics Table 21. ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; ADC frequency 4.5 MHz; unless otherwise specified. Symbol VIA Cia ED EL(adj) EO EG ET Rvsi Ri fclk(ADC) fc(ADC) [1] [2] [3] [4] [5] [6] [7] [8] [9] Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance input resistance ADC clock frequency ADC conversion frequency Conditions Min 0 [1][2][3] [1][4] [1][5] [1][6] [1][7] Typ - Max VDDA(3V3) Unit V pF LSB LSB LSB % LSB k M MHz kSamples/s - [8][9] - Conditions: VSSA = 0 V, VDDA(3V3) = 3.3 V. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 42. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 42. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 42. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 42. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 42. Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF. Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 114 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller offset error EO 1023 gain error EG 1022 1021 1020 1019 1018 (2) 7 code out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 1018 1019 1020 1021 1022 1023 1024 0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal) 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 42. 10-bit ADC characteristics LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 115 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 22. DAC electrical characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified Symbol ED EL(adj) EO EG CL RL Parameter differential linearity error integral non-linearity offset error gain error load capacitance load resistance Conditions Min Typ Max Unit LSB LSB % % pF k LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 116 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 13. Application information 13.1 LCD panel signal usage Table 23. LCD panel connections for STN single panel mode 4-bit mono STN single panel LPC18xx pin used LCD_VD[23:8] LCD_VD7 LCD_VD6 LCD_VD5 LCD_VD4 LCD_VD3 LCD_VD2 LCD_VD1 LCD_VD0 LCD_LP LCD_ENAB/ LCDM LCD_FP LCD_DCLK LCD_LE LCD_PWR GP_CLKIN Table 24. P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCD function UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE CDPWR LCDCLKIN 8-bit mono STN single panel LPC18xx pin used P8_4 P8_5 P8_6 P8_7 P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCD function UD[7] UD[6] UD[5] UD[4] UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN Color STN single panel LPC18xx pin used P8_4 P8_5 P8_6 P8_7 P4_2 P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCD function UD[7] UD[6] UD[5] UD[4] UD[3] UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN External pin LCD panel connections for STN dual panel mode 4-bit mono STN dual panel LPC18xx pin used LCD function LD[3] LD[2] LD[1] LD[0] UD[3] P8_5 P8_6 P8_7 P4_2 8-bit mono STN dual panel LPC18xx pin used PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P4_8 P7_5 LCD function LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] UD[7] UD[6] UD[5] UD[4] UD[3] Color STN dual panel LPC18xx pin used PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P4_8 P7_5 P8_4 P8_5 P8_6 P8_7 P4_2 LCD function LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] UD[7] UD[6] UD[5] UD[4] UD[3] © NXP B.V. 2011. All rights reserved. External pin LCD_VD[23:16] LCD_VD15 LCD_VD14 LCD_VD13 LCD_VD12 LCD_VD11 LCD_VD10 LCD_VD9 LCD_VD8 LCD_VD7 LCD_VD6 LCD_VD5 LCD_VD4 LCD_VD3 LPC1850_30_20_10 P4_9 P4_10 P4_8 P7_5 P4_2 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 117 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 24. LCD panel connections for STN dual panel mode 4-bit mono STN dual panel LPC18xx pin used LCD function UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN 8-bit mono STN dual panel LPC18xx pin used P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCD function UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN Color STN dual panel LPC18xx pin used P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCD function UD[2] UD[1] UD[0] LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN External pin LCD_VD2 LCD_VD1 LCD_VD0 LCD_LP LCD_ENAB/ LCDM LCD_FP LCD_DCLK LCD_LE LCD_PWR GP_CLKIN Table 25. External pin P4_3 P4_4 P4_1 P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCD panel connections for TFT panels TFT 12 bit (4:4:4 mode) LPC18xx pin used LCD function BLUE3 BLUE2 BLUE1 BLUE0 GREEN3 GREEN2 GREEN1 GREEN0 RED3 RED2 RED1 RED0 TFT 16 bit (5:6:5 mode) LPC18xx pin used PB_0 PB_1 PB_2 PB_3 P7_1 PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P8_4 P8_5 P8_6 P8_7 P4_2 LCD function BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED4 RED3 RED2 RED1 RED0 TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC18xx pin LCD used function PB_0 PB_1 PB_2 PB_3 P7_1 P7_2 PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P8_4 P8_5 P8_6 P8_7 P4_2 P4_3 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 intensity GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 intensity RED4 RED3 RED2 RED1 RED0 intensity P7_3 P7_4 PB_4 PB_5 PB_6 P8_3 P4_9 P4_10 P4_8 P7_5 P8_4 P8_5 P8_6 P8_7 P4_2 P4_3 P4_4 LPC18xx pin used LCD function BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED7 RED6 RED5 RED4 RED3 RED2 RED1 © NXP B.V. 2011. All rights reserved. LCD_VD23 PB_0 LCD_VD22 PB_1 LCD_VD21 PB_2 LCD_VD20 PB_3 LCD_VD19 LCD_VD18 LCD_VD17 LCD_VD16 LCD_VD15 PB_4 LCD_VD14 PB_5 LCD_VD13 PB_6 LCD_VD12 P8_3 LCD_VD11 LCD_VD9 LCD_VD8 LCD_VD7 LCD_VD6 LCD_VD5 LCD_VD4 LCD_VD3 LCD_VD2 LCD_VD1 LPC1850_30_20_10 P8_4 P8_5 P8_6 P8_7 - LCD_VD10 - All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 118 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 25. External pin LCD panel connections for TFT panels TFT 12 bit (4:4:4 mode) LPC18xx pin used LCD function LCDLP TFT 16 bit (5:6:5 mode) LPC18xx pin used P7_6 LCD function LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC18xx pin LCD used function P7_6 P4_6 P4_5 P4_7 P7_0 P7_7 PF_4 LCDLP LPC18xx pin used P4_1 P7_6 LCD function RED0 LCDLP LCDENAB/ LCDM LCDFP LCDDCLK LCDLE LCDPWR LCDCLKIN LCD_VD0 LCD_LP P7_6 LCD_ENAB P4_6 /LCDM LCD_FP LCD_LE LCD_PWR GP_CLKIN P4_5 P7_0 P7_7 PF_4 LCD_DCLK P4_7 LCDENAB/ P4_6 LCDM LCDFP LCDDCLK LCDLE LCDPWR P4_5 P4_7 P7_0 P7_7 LCDENAB/ P4_6 LCDM LCDFP LCDDCLK LCDLE LCDPWR P4_5 P4_7 P7_0 P7_7 LCDCLKIN PF_4 LCDCLKIN PF_4 13.2 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see LPC18xx user manual). The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The oscillator can operate in one of two modes: slave mode and oscillation mode. • In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (CC in Figure 43), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this configuration can be left unconnected. • External components and models used in oscillation mode are shown in Figure 44, and in Table 26 and Table 27. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 44 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS and CP are supplied by the crystal manufacturer. Table 26. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Maximum crystal series resistance RS < 200  < 200  < 200  4 MHz < 200  < 200  < 200  8 MHz < 200  < 200  External load capacitors CX1, CX2 33 pF, 33 pF 39 pF, 39 pF 56 pF, 56 pF 18 pF, 18 pF 39 pF, 39 pF 56 pF, 56 pF 18 pF, 18 pF 39 pF, 39 pF Fundamental oscillation frequency 2 MHz LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 119 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Maximum crystal series resistance RS < 160  < 160  < 120  < 80  < 100  < 80  External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 33 pF, 33 pF 18 pF, 18 pF 33 pF, 33 pF Table 26. Fundamental oscillation frequency 12 MHz 16 MHz 20 MHz Table 27. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) high frequency mode Maximum crystal series resistance RS < 80  < 80  < 100  External load capacitors CX1, Cx2 18 pF, 18 pF 39 pF, 39 pF 47 pF, 47 pF Fundamental oscillation frequency 15 MHz 20 MHz LPC1xxx XTAL1 Ci 100 pF Cg 002aae835 Fig 43. Slave mode operation of the on-chip oscillator LPC18xx L XTAL1 XTAL2 = XTAL CL CP RS CX1 CX2 002aag031 Fig 44. Oscillator modes with external crystal model used for CX1/CX2 evaluation LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 120 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 121 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 14. Package outline LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm SOT740-2 D B A ball A1 index area A2 E A A1 detail X e1 e 1/2 e b ∅v M C A B ∅w M C T R P N M L K J H G F E D C B A C y1 C y e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.55 A1 0.45 0.35 A2 1.1 0.9 b 0.55 0.45 D 17.2 16.8 E 17.2 16.8 e 1 e1 15 e2 15 v 0.25 w 0.1 y 0.12 y1 0.35 OUTLINE VERSION SOT740-2 REFERENCES IEC --JEDEC MO-192 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-06-16 05-08-04 Fig 45. Package outline of the LBGA256 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 122 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 e b ∅v ∅w M M CAB C C y1 C y P N M L K J H G F E D C B A e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 1.20 1.06 0.95 A1 0.40 0.35 0.30 A2 0.80 0.71 0.65 b 0.50 0.45 0.40 D 12.1 12.0 11.9 E 12.1 12.0 11.9 e 0.8 e1 10.4 e2 10.4 v 0.15 w 0.05 y 0.12 y1 0.1 OUTLINE VERSION SOT570-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 08-07-09 10-04-15 Fig 46. Package outline of the TFBGA180 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 123 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 156 157 105 104 ZE e E HE A A2 A1 (A 3) θ Lp L detail X wM bp pin 1 index 208 53 1 52 e bp D HD wM ZD B vM A vM B 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.12 w 0.08 y 0.08 ZD 1.43 1.08 ZE 1.43 1.08 θ 7o o 0 30.15 30.15 29.85 29.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT459-1 REFERENCES IEC 136E30 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-06 03-02-20 Fig 47. Package outline of the LQFP208 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 124 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm SOT926-1 D B A ball A1 index area A2 E A A1 detail X e1 e 1/2 e b ∅v ∅w M M C CAB C y1 C y K J H G F E D C B A e e2 1/2 e ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.4 0.3 A2 0.8 0.65 b 0.5 0.4 D 9.1 8.9 E 9.1 8.9 e 0.8 e1 7.2 e2 7.2 v 0.15 w 0.05 y 0.08 y1 0.1 OUTLINE VERSION SOT926-1 REFERENCES IEC --JEDEC --JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-12-09 05-12-22 Fig 48. Package outline of the TFBGA100 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 125 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 108 109 73 72 ZE e E HE A A2 A1 (A 3) θ Lp L detail X wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 θ 7o o 0 22.15 22.15 21.85 21.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-14 03-02-20 Fig 49. Package outline for the LQFP144 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 126 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L θ Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 θ 7o o 0 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 50. Package outline for the LQFP100 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 127 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 15. Soldering Footprint information for reflow soldering of LBGA256 package SOT740-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL occupied area solder resist SP SR detail X DIMENSIONS in mm P 1.00 SL 0.450 SP 0.450 SR 0.600 Hx Hy sot740-2_fr 17.500 17.500 Fig 51. Reflow soldering of the LBGA256 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 128 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL occupied area solder resist SP SR detail X DIMENSIONS in mm P 0.80 SL 0.400 SP 0.400 SR 0.550 Hx Hy sot570-3_fr 12.575 12.575 Fig 52. Reflow soldering of the TFBGA180 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 129 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 P1 (0.125) Hy Gy By Ay C D2 (8×) Bx Ax Generic footprint pattern D1 Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By C 1.500 D1 0.280 D2 0.400 Gx Gy Hx Hy sot459-1_fr 0.560 31.300 31.300 28.300 28.300 28.500 28.500 31.550 31.550 Fig 53. Reflow soldering of the LQFP208 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 130 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 P1 (0.125) Hy Gy By Ay C D2 (8×) Bx Ax Generic footprint pattern D1 Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By C 1.500 D1 0.280 D2 0.400 Gx Gy Hx Hy sot486-1_fr 0.560 23.300 23.300 20.300 20.300 20.500 20.500 23.550 23.550 Fig 54. Reflow soldering of the LQFP144 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 131 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL occupied area solder resist SP SR detail X DIMENSIONS in mm P 0.80 SL 0.330 SP 0.400 SR 0.480 Hx 9.400 Hy 9.400 sot926-1_fr Fig 55. Reflow soldering of the TFBGA100 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 132 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 P1 (0.125) Hy Gy By Ay C D2 (8×) Bx Ax Generic footprint pattern D1 Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By C 1.500 D1 0.280 D2 0.400 Gx Gy Hx Hy sot407-1 0.560 17.300 17.300 14.300 14.300 14.500 14.500 17.550 17.550 Fig 56. Reflow soldering of the LQFP100 package LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 133 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 16. Abbreviations Table 28. Acronym ADC AES AHB APB API BOD BGA CAN CMAC CSMA/CD DAC DMA EOP ETB ETM GPIO IRC IrDA JTAG LCD LSB LQFP MAC MCU MIIM n.c. OTG PHY PLL PWM RMII SDRAM SPI SSI SSP TCP/IP TTL UART ULPI LPC1850_30_20_10 Abbreviations Description Analog-to-Digital Converter Advanced Encryption Standard Advanced High-performance Bus Advanced Peripheral Bus Application Programming Interface BrownOut Detection Ball Grid Array Controller Area Network Cipher-based Message Authentication Code Carrier Sense Multiple Access with Collision Detection Digital-to-Analog Converter Direct Memory Access End Of Packet Embedded Trace Buffer Embedded Trace Macrocell General Purpose Input/Output Internal RC Infrared Data Association Joint Test Action Group Liquid Crystal Display Least Significant Bit Low Quad Flat Package Media Access Control MicroController Unit Media Independent Interface Management not connected On-The-Go PHYsical layer Phase-Locked Loop Pulse Width Modulator Reduced Media Independent Interface Synchronous Dynamic Random Access Memory Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transmission Control Protocol/Internet Protocol Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter UTMI+ Low Pin Interface All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 134 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Abbreviations …continued Description Universal Synchronous Asynchronous Receiver/Transmitter Universal Serial Bus USB 2.0 Transceiver Macrocell Interface Table 28. Acronym USART USB UTMI LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 135 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 17. Revision history Table 29. Revision history Release date Data sheet status 20110909 Preliminary data sheet Preliminary data sheet Change notice Supersedes LPC1850_30_20_10 v.2.1 LPC1850_30_20_10 v.2 Document ID LPC1850_30_20_10 v.2.2 Modifications: LPC1850_30_20_10 v.2.1 Modifications: • • • • • • Pin P7_2, column LQFP144: replaced 113 by 115 in Table 3. LQFP100 pin package added in Table 3. Number of ADC channels, QEI, and Motor control PWM added in Table 2. Pin P2_7 designated as ISP entry pin. Description of ISP mode added (see Section 7.8.1). Updates related to the Rev ‘A’ version of parts LPC1850/30/20/10: – VI updated for I/O pins in Table 6. – Boot pins corrected in Table 3 and Table 5: Pin P2_7 replaced by pin P2_9 as boot pin. Pin level corrected for 4th boot pin (pin P2_9) in Table 5. – USART3 boot mode added in Table 5. – Memory map updated: SPIFI data added at address 0x1400 000 in Figure 9. – Boot ROM size increased to 64 kB in Section 2 and Figure 9. 20110822 • Updated pin P2_2, CTOUT_6 changed to CTIN_6 in Table 3. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 136 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 29. Revision history …continued Release date Data sheet status 20110713 Objective data sheet Change notice Supersedes LPC1850_30_20_10 v.1.2 Document ID LPC1850_30_20_10 v.2 Modifications: • • • • • • • • • • • • • • • • Power consumption data added (Figure 12 to Figure 17). Pin PC_0 in Table 3: function ENET_RX_CLK changed to n.c. and function SDIO_CLK changed to function ENET_RX_CLK. Pin PC_8 in Table 3: ENET_RX_DV applies to RMII/MII interfaces. Rename pins CAN1_RD and CAN1_TD to CAN0_RD and CAN0_TD in Table 3. Rename all I2S pins to I2S0 pins. Condition for RTC operation updated in Table 8, Table note 2. Figure 11 “LPC1850/30/20/10 Power domains” added. “n.c.” changed to “Reserved” in Table 3. Section 11.6: characterization parameters and timing diagrams updated. Prefix for all SD/MMC pins changed to “SD” in Table 3. Prefix for all EMC pins changed to “EMC” in Table 3. Section 11.4 added. Section 11.8 added. Section 11.9 added. LQFP144 pinout added in Table 3. Updates related to the Rev ‘A’ version of parts LPC1850/30/20/10: – Pin P6_0 in Table 3: function I2S_RX_CLK moved to function level 5. – Pin PF_0 in Table 3: function GP_CLKIN added. – Pin PA_1 in Table 3: function U2_TXD added. – Pin PA_2 in Table 3: function U2_RXD added. – Pin PC_0 in Table 3: reset state changed to I; PU. – Pin P1_16 in Table 3: ENET_CRS_DV moved to function level 7. – Pad descriptions updated in Table 3, Table note 3 to Table note 11. – Added function levels four to seven/eight for each pin in Table 3. – Second C_CAN interface (C_CAN1) added. – Second I2S interface (I2S1) added. – Audio PLL added (Section 2 and Section 7.18.6). – All SDIO functions moved to the function levels four to seven in Table 3. – High-speed GPIO block moved to address 0x400F 4000 in Figure 9 and Figure 10. – GPIO interrupts and GPIO group0 and group1 interrupt added in Figure 1, Figure 9, Figure 10, Section 2, and Section 7.12. – Number of GPIO ports increased to eight. – Total number of GPIO pins increased to 164. – GIMA block added (Section 7.6). – Band gap output added to pin PF_7. – Package outline and soldering information added for all packages. LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 137 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Table 29. Revision history …continued Release date Data sheet status 20110217 Objective data sheet Change notice Supersedes LPC1850_30_20_10 v.1 Document ID LPC1850_30_20_10 v.1.2 Modifications: • • • • • • • • • RMII removed from description of pin functions ENET_RXD2, ENET_RXD3, ENET_ER. ENET_REF_CLK removed from pin function ENET_RX_CLK (Table 3). Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2) added (Section 2 and Section 7.12.9). All pins with default state n.c. are inputs with pull-ups enabled on reset (Table 3). SPIFI functions removed from pins PA_0, PA_3, PC_4, PC_5, PC_8, PE_2 in Table 3. Reset states added for multiple pins in Table 3. Editorial updates. Section 13.2 “Crystal oscillator” added. Pin P2_7 designated as boot pin 3 in Table 3. USB0 and USB1 added to boot sources in Table 4 and Table 5. Objective data sheet - LPC1850_30_20_10 v.1 20110103 LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 138 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2011. All rights reserved. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. Preliminary data sheet Rev. 2.2 — 9 September 2011 139 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 140 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 20. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 60 Architectural overview . . . . . . . . . . . . . . . . . . 60 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 60 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 61 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.4.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 62 7.5 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.6 Global Input Multiplexer Array (GIMA) . . . . . . 62 7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.7 System Tick timer (SysTick) . . . . . . . . . . . . . . 62 7.8 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 62 7.8.1 ISP (In-System Programming) mode . . . . . . . 63 7.9 Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.10 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 65 7.11 Security features. . . . . . . . . . . . . . . . . . . . . . . 67 7.11.1 AES security engine . . . . . . . . . . . . . . . . . . . . 67 7.11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.11.2 One-Time Programmable (OTP) memory . . . 67 7.12 General Purpose I/O (GPIO) . . . . . . . . . . . . . 67 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.13 AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 68 7.13.1 State Configurable Timer (SCT) subsystem . . 68 7.13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.13.2 General Purpose DMA (GPDMA) . . . . . . . . . . 68 7.13.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.13.3 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 69 7.13.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.13.4 SD/MMC card interface . . . . . . . . . . . . . . . . . 70 7.13.5 External Memory Controller (EMC). . . . . . . . . 70 7.13.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.13.6 High-speed USB Host/Device/OTG interface (USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.13.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.13.7 High-speed USB Host/Device interface with ULPI (USB1) . . . . . . . . . . . . . . . . . . . . . . 71 7.13.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.13.8 7.13.8.1 7.13.9 7.13.9.1 7.14 7.14.1 7.14.1.1 7.14.2 7.14.2.1 7.14.3 7.14.3.1 7.14.4 7.14.4.1 7.14.5 7.14.5.1 7.14.6 7.14.6.1 7.15 7.15.1 7.15.1.1 7.15.2 7.15.3 7.15.3.1 7.15.4 7.15.4.1 7.15.5 7.15.5.1 7.16 7.16.1 7.16.1.1 7.16.2 7.16.2.1 7.17 7.17.1 7.17.1.1 7.17.2 7.18 7.18.1 7.18.2 7.18.3 7.18.4 7.18.5 7.18.6 7.18.7 7.18.8 7.18.9 7.19 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital serial peripherals. . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSP serial I/O controller. . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/timers and motor control . . . . . . . . . General purpose 32-bit timers/external event counter . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motor control PWM . . . . . . . . . . . . . . . . . . . . Quadrature Encoder Interface (QEI) . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Repetitive Interrupt (RI) timer. . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Windowed WatchDog Timer (WWDT) . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog peripherals . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-to-Analog Converter (DAC). . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripherals in the RTC power domain . . . . . . RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . System control . . . . . . . . . . . . . . . . . . . . . . . . Configuration registers (CREG) . . . . . . . . . . . System Control Unit (SCU) . . . . . . . . . . . . . . Clock Generation Unit (CGU) . . . . . . . . . . . . Internal RC oscillator (IRC) . . . . . . . . . . . . . . PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation Unit (RGU) . . . . . . . . . . . . Power control . . . . . . . . . . . . . . . . . . . . . . . . . Emulation and debugging . . . . . . . . . . . . . . . 71 72 72 72 73 73 73 73 74 74 74 74 75 75 75 76 76 76 76 76 77 77 77 77 77 78 78 78 78 78 79 79 79 79 79 79 79 79 80 80 80 80 80 81 81 81 82 continued >> LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 2.2 — 9 September 2011 141 of 142 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 12 13 13.1 13.2 13.3 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 83 Thermal characteristics . . . . . . . . . . . . . . . . . 84 Static characteristics. . . . . . . . . . . . . . . . . . . . 85 Power consumption . . . . . . . . . . . . . . . . . . . . 89 Power consumption . . . . . . . . . . . . . . . . . . . . 93 Electrical pin characteristics . . . . . . . . . . . . . . 96 Dynamic characteristics . . . . . . . . . . . . . . . . . 98 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 98 IRC and RTC oscillators . . . . . . . . . . . . . . . . . 99 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 101 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 103 External memory interface . . . . . . . . . . . . . . 106 USB interface . . . . . . . . . . . . . . . . . . . . . . . 111 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 ADC/DAC electrical characteristics . . . . . . . 114 Application information. . . . . . . . . . . . . . . . . 117 LCD panel signal usage . . . . . . . . . . . . . . . . 117 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 119 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . 121 Package outline . . . . . . . . . . . . . . . . . . . . . . . 122 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 134 Revision history . . . . . . . . . . . . . . . . . . . . . . . 136 Legal information. . . . . . . . . . . . . . . . . . . . . . 139 Data sheet status . . . . . . . . . . . . . . . . . . . . . 139 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 140 Contact information. . . . . . . . . . . . . . . . . . . . 140 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 September 2011 Document identifier: LPC1850_30_20_10